Chapter 11. Digital Integrated Circuit Design II. $Date: 2016/04/21 01:22:37 $ ECE 426/526, Chapter 11.

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1 Digital Integrated Circuit Design II ECE 426/526, $Date: 2016/04/21 01:22:37 $ Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR (daasch@ece.pdx.edu) Course Website [Note links are parsed by Adober Reader but may not be parsed by browser viewers] 1 Apr il 2016 Partitioning expands from cells along familiar organization lines Data-path addition, subtraction, multiplication and other operations Data-path operations can be unary, binar y and multi nary operands Wide majority is digital Addition and multiplication are associative and commutative Inputs are equivalent provides a symmetry in the design Symmetr ic circuits easier to predict critical path (Carryout not Sum) Memor y volatile and non-volatile 2 Apr il 2016

2 EPROMS, Flash, PLAs and ROMS Static RAM, Dynamic RAM Memor y blends digital and analog Control systems Often overlooked is the coordination of flow into and out of the system as well as between subunits Major ity digital (some analog if PLL is grouped here) Special Purpose cells Critical functions typically have requirements unique to process Many are analog IO may use different transistor oxide thickness Clocks (PLL) and other distribution schemes such as H- tree 3 Apr il 2016 Each subsystem reveals a common design trade-off Space area of the part (yield), number of transistors (logic complexity), switching capacitance (power) Time propagation delay, clock cycles, average instr uctions completed per cycle The trade-off is simple on its face Minimum area is a single bit data-path (memory etc.) and maximum delay (clock cycles perhaps N 2 or more) lowest IPC Maximum area is a word parallel, concurrent instruction data-path and minimum clock cycles (perhaps 1) Addition is a good case to demonstrate linear, either t N or area N relationships between space and time Multiplication is a good case to demonstrate quadratic t N 2 or area N 2 relationships between space and time 4 Apr il 2016

3 General design guidelines Use asymmetric transistor sizing Cr itical path input (carry) is at top of stacked transistors Reduce size of off-cr itical path transistors to minimum Oversize critical path drivers Bubble push (alternate positive and negative logic) New designs appear ing for single bit full-adders are constantly Common approach is to share products (i.e. Major ity is one way to compute 3 input ExOR) Tr ansmission gates typically multiplexers and low transistor count Ex-OR Static logic merge carry and sum, multi-level logic 5 Apr il 2016 Differential and Dynamic all the tricks of complements, feedback clocking Asingle 1-bit adder combined with appropriate registers and control provides a complete solution to N-bit addition Registers feed LSB (least significant bit) to MSB (most significant bit) into the A and B inputs, respectively Athird (single bit) register collects and recycles the output carr y (a component of the state) Final sums are computed and captured serially Control counts the bits from 0 to N (or N-1) clock cycles Ripple carry adders combine more adders for what improvement in the space time tradeoff Registers feed parallel words LSB to MSB into the bit-wise adders 6 Apr il 2016

4 Carr y signals propagate from LSB to MSB (the ripple) and eliminate the need for the carry save register Final sums computed serially and captured in parallel Control counts operations A+B rather than the bits in the word Carr y-lookahead adders reorganize addition to exploit more of the concurrency in the data-path operation Decompose the sum and carry logic into two pieces Propagation = Ai +Bi Propagation moves the incoming carry input to the carry output Generation = Ai Bi Generation creates a carry out independent of the carry input 7 Apr il 2016 The binary sum in P and G is Sum = Pi +Gi 1:0 where the Gi 1:0 tracks the results of all bits of lower than i and Gi :j = Gi :k + Pi :k Gk 1:j Pi :j = Pi :k Pk 1:j Carr y is also a function of P and G Carry = Gi :0 = Gi + PiGi 1:0 P and G are functions of the inputs Ai and Bi Ripple carry hidden in the computation of the G Computations that are independent can be evaluated concurrently 8 Apr il 2016

5 Final sum is completed in parallel Valency organizes the inputs into increasing larger fan-in Same limits to increasing valency (fan-in) Fan-in increases logic effor t (delay slope) Fan-in increases diffusion areas (wider transistors) for larger parasitic delay Weste-Harr is PG diagrams visually capture area delay tradeoff (example Figure 10.16) Area and delay character istics For asynthesized 32 bit adder the ratio of delay toarea is about 10 to 1 For asynthesized 64 bit adder the ratio of delay toarea is about 25 to 1 9 Apr il 2016 Many circuits reflect the same tradeoff in space and time with equations that have the for m Xi +1 = A Xi + C Other logic circuits displaying same character istics are subtraction and prior ity encoding Adder comparison (Table 10.3 and area delay char t) The Classification of the tree adders is based on number of logic levels, the fan-out requires (branching effor t B = Π bi ), the wiring tracks (similar to standard cell routing tracks) The chart summar izes adders two different words sizes Many best adders use more than logic for the Boolean function (S and Carry) Control logic is generally multiplexer and clocks (domino) 10 Apr il 2016

6 Both show basic space-time trade-off Increasing complexity lowers all latency (delays) Increasing complexity reduces the effects of word size Note that some mix simple ripple and more complex (more control) carry select adders 1/0 detectors, magnitude comparison (zero detection) examples of high fan-in circuits Input limited Long N 2 delays for series chain Fast growing logic effor t lng(n ) = log2 4 3 log2 N = log2 N log = log 2 N log 2 4/3 High subthreshold leakage from parallel chain Unsigned or signed equality is a large fan-in NOR (bit-wise match) or large fan-in NAND (bit-wise difference) 11 Apr il 2016 Similar fan-in for K = A + B test Many of binar y operators require 2 input XOR and XNOR Simple to design generally larger transistor counts (standard 4 2-NAND) Simple networ ks require detailed circuit simulation 10.61(g) Multiplication comes in two for ms Array adders use repeated addition Algor ithmic adders reduce the operation of multiplication to logical shifts, addition and subtraction Four terms to know Multiplier Multiplicand quantities to be multiplied together For example, inthe expression A B, A isthe multiplier and Bisthe multiplicand 12 Apr il 2016

7 Partial Product bitwise AND of multiplicand and multiplier Product (running product) Result of multiplication (r unning product computed serially from LSB to MSB) Ser ial multiplication as simple as a single full adder cell Adder outputs Sum shifts Control manages three inputs to present to the adder Bit carry and partial sum pair New bitwise product (Xi Yi ) Carr y is recirculated using CSA For 2Nbit words adder is used N 2 clocks Substitution of a single ripple or other adder Extra adder width reduces the clock count from N 2 to N 13 Apr il 2016 Recycle partial sums or shift weight of multiplicand Substitute an orthogonal array of ripple or other adders Array multiplication typically a carry-save adder NxN regular grid reduces to the clock cycles to 1 Cr itical path is longest column of partial product bits (N ) To this point the data is assumed to be a fixed-point integer Other data operands such as floating point and signed numbers are routinely considered Booth Multiplication and the use of data representation Exchange the array adder for a FSM (finite-state machine) Algor ithm dr iven by the multiplier replaces repeated bitwise multiplication and addition 2 s complement data in multiplication provides a useful case study 14 Apr il 2016

8 The encoding of data is an option in the design Data in 2 s complement simplifies arithmetic addition, subtraction and multiplication Subtraction requires a little more hardware than addition Bitwise section of PG includes an instruction bit to selectively invert Group section of PG includes an conversion of instruction bit (subtract) to data bit LSB Carry-in Difficult to multiply terms such as Y x 3 (b11) or Y x 7 (b111) are replaced by asimple sequence of subtract, shift, add Y 3 = Y (-1 + 4) Y 7 = Y ( -b1 + b1000) The combinations are also simplified for example 15 Apr il 2016 Y 0x703 = 0x x3 (Booth) Y 0x703 = Y [( -b1 + b1000) 0x ( -b1 + b100) 0x 1] The use of a simple binary shift to maintain the proper location of the binary arithmetic Booth Multiplication can be completed in any 2 r radix (2 r is the base of the number system) In radix 2 (r = 1) a single bit of the product is determined each step, radix 4 two bits and so on 16 Apr il 2016

9 Radix 2 Booth Encoding of Multiplication OpCode RSHFT PP Right Shift Par tial Product 0 0 RSHFT PP 0 1 SUBTRACT MULTIPLICAND, RSHFT PP 1 0 ADD MULTIPLICAND, RSHFT PP 1 1 RSHFT PP Xi Xi 1 For (Xi, Xi 1) = (00) or (Xi, Xi 1) = (11) are shifts, no ar ithmetic at all Current value of the right-most bit of the partial product is the next digit in the final product For (Xi, Xi 1) = (10) subtraction followed by shift The needed arithmetic preceding the shift accounts for -1 (in earlier Booth equation) Current value of the right-most bit of the partial product is the next digit in the final product 17 Apr il 2016 For (Xi, Xi 1) = (01) addition followed byshift The needed arithmetic preceding the shift accounts for 0b1000 (in earlier Booth equation) Current value of the right-most bit of the partial product is the next digit in the final product 18 Apr il 2016