# A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology

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3 Inf. Sci. Lett. 2, No. 3, (2013) / Table 1: Comparison of different code s generator Present (Muralidharan, (Cho, et. al, 2011) Study et.al, 2011) Technology (nm) Transistor counts Multiplication time (ns) Chip Area (mm 2 ) Power Diss (mw) Fig. 4: Hybrid carry network Fig. 3: Lookahead adder network C pb is the carry signal of the most-significant bit of the previous module. Table 1 shows comparison of different code s generator. Note that since each module is calculating with module carry-out of one, the carry into the LSB location of each module is 0, i.e., s i = p i + c p?? and c i = g i when it is the least-significant-bit of a module. Note that s i = p i + c i 1, but c i 1 is (c pb.g 0 i 1 ) + (c pb.g 1 i 1 ). A decreased form for this equation c i 1 is (c pb.g i i 3 ) + (c pb.g i i 3 ), this is (c pb.g 1 i 1 )which is equal to (c pb.g 1 i 1 ). For each module, we also require to determine the final value of the sum-in from the most-significant bit location, which is used to calculate from two copies of the next module. Let c bl show the sum-out from the higher bit position of the lth module, for 1<=l<=k (there are k units). Once again, the calculation logic needed c bl where it is the module generate for the lth unit for 2<=l<=k. B= d[b]+1 2 n +1 n/2 = (1+b 0 2b 1 )+ (b 2i 1 + b 2i 2b 2i+1 )2 2i i=1 2 n +1 The basic Wallace carry chain unit is presented in Figure 4. Outputs are obtained from the appropriate points in the network. In order to make the Wallace carry propagation as fast as possible, each transistor chain is designed to approximately result the bit module where it is substituted. The second step (and higher level if required) P cc units are substituted in left holes in the expression of second step P cc units to decrease the width of the wiring. Some equations of the Wallace carry chain module are possible since not all of the inputs were used in all of the blocks. In the basic Wallace carry propagation presented in Figure 4 the expression of chain transistors used to compute the block chain differs from the line of transistors used for chain the produce signals only in the wiring of P 0. This removes the intermediate inputs. The carry-in shown in Figure 4 contains three extra transistors for calculating carry out. This carry out expression is used once at the top of the array. Multiplier architecture is shown in Figure 1. It uses four to two counter chain in different rows. Different contributions have been presented for different parts of Figure 1. 4 The Network propagation tree The counter floor plan is presented in Figure 4. Metal three is used for long vertical lines carrying the input signals, the bit chain and produce inputs, the computed carries, and the outputs. Metal two runs horizontally, and is used for local signals. The third module is a stack of three bit V cc cells connected in pairs to form seven bit carry lookahead modules. A ONE carry is input to each block in this row. The fourth row consists of propagate carry modules with a carry in of ZERO. Next are the exclusive-nor gates for computing the sums from the chain carries and the bit sums. The forth row is the carry array. The last row consists of counters, which select between the seven bits sum outputs. The idea of this multiplier is based on the architecture of a low-power multiplier with modified Booth algorithm (Cho, et. al, 2011). A Booth encoder using counter array requires nearly half the size of a conventional array multiplier and decreases delay. One method to modify this circuit structure is to improve the final chain adder structure, thereby decreasing the carry delay. In our circuit simulation, a dynamic counter with P cc is used (Figure 4). This calculates the data flow of the multiplier in a modified new method. The final multiplication output is

4 162 P. Asadi: A New network multiplier using modified high order encoder... Fig. 5: Three to two compressor Fig. 6: High-speed summation tree computed in the subsequent synthesis phase. This multiplication algorithm incorporates some timing constraints since there are nearly N/2 dynamic signal and N static sum delays. Circuits simulated on the gate synthesis have the following timing constraints Table 2: Comparison between bit multipliers Multipliers Present Study (Wang, et. al, 2011) (Nakamoto, et. al, 2011) Technology (nm) Transistor counts Multiplication time (ns) Chip Area (mm 2 ) Power Diss. (mw) { 1 µ(xn 1 + y n 1 )<0 t 1 = 0 µ(x n 1 + y n 1 ) 0 This includes a multiplication frequency at 300 MHz for arithmetic processor. The area of the 32-bit * 32-bit multiplier takes 5.6 mm 2. In this way, it is more efficient to compute the P cc counter than the dynamic adder array. A comparison with a new implementation for low power multiplier structure is presented in Figure 4 (Chen, et. al, 2012). A 64-bit *64-bit multiplier and a 108-bit adder have been simulated in arithmetic chip. The chip implements a part of the dynamic counter cell. Simulation results of both counter and modules have been verified with 60nm CMOS technology. The array adds eight trees and six compressors (eight-expressions). It will run with 300-MHz arithmetic processor. 5 Efficient array elements The circuits for CMOS counters and XOR gates are well known (Muralidharan, et.al, 2011), and the standard implementations were used for these modules with the dimensions computed to provide the appropriate current output. The XNOR gate and compressor modules effectively included three gates in one module. These kinds of module were used often in implementation and incorporating three gates in one module consumed less area than three separate modules. The exclusive-nor gate proved more complicated implementation task. The structure of the design obtains high speed and low power. The traditional DCVS exclusive-nor gate was rather slow and is high-power consumption unit, so a variation on the high speed CMOS exclusive-nor was used. The algorithm of the circuit is such that the internal connection driving the output gate could overshoot V dd by high noise. This issue may be explained by simulating the voltages across the gate-output capacitances (C gd ) of the p-channel transistors n 1 and n 2, as shown in Figure 5. When both signals change from low to high, the n-channel transistors p1 and p2 will shut down and removes the V int node. The voltage between the gate-output capacitances increases at V dd, but the gate input is now near the V dd rather than one circuit so the node V int increases above V dd. The maximum power occurs if the three signals change simultaneously and increases as the time between the three rising sides is increased. The results of a Cadence simulation of the exclusive-nor module are presented in Figure 5. V int is clearly seen to increase V dd ; it is therefore important to connect a guard ring into this module in order to remove the possibility of occurring noise problems. As stated previously, all the modules used in this implementation incorporated signal strength in any case, so decreased noise problems would have taken effect. As mentioned

6 164 P. Asadi: A New network multiplier using modified high order encoder... [8] Nakamoto, R., et. al, 4-bit SFQ Multiplier Based on Booth Encoder, IEEE Transactions on Applied Superconductivity, 21, (2011). [9] Seidel, P. M., et. al, Secondary Radix Recodings for Higher Radix Multipliers, IEEE Transactions on Computers, 54, (2005). [10] Seo, Y. H., et. al, A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (2010). [11] Wang, J. P., et. al, High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19, (2011).

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