Function Table of an Odd-Parity Generator Circuit

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1 Implementation of an Odd-Parity Generator Circuit The first step in implementing any circuit is to represent its operation in terms of a Truth or Function table. The function table for an 8-bit data as input has 2 8 has 256 input combinations, which becomes unmanageable. Therefore, for the sake of simplicity a 4-bit data with odd parity is assumed. The receiver circuit is also based on the 4-bit data. The function table for the 4-bit data is shown. Figure 14.1 Input Output Input Output D 3 D 2 D 1 D P D 3 D 2 D 1 D P Table 14.1 Function Table of an Odd-Parity Generator Circuit The function table represents the 16 possible combinations of 4 data bits. The 4 data bits are represented by variables D3, D2, D1 and D. The output P represents the state of the Parity bit. Since Odd-Parity is being used therefore the 4-bit data and the parity bit should add up to give odd number of 1s. The function table shows the Parity bit set to 1 when the 16, 4-bit data input combinations have no 1s or an even number of 1s. The information in the function table is mapped directly to a four variable K-map to simplify the Boolean expression represented by the Odd-Parity generator function. None of the 1s mapped in the K-map are adjacent to each other thus the function mapped to the K-map can not be simplified. Figure 14.1 D 3 D 2 \D 1 D Figure 14.1 Karnaugh map of the Odd-Parity Generator Function However, using the Rules of Boolean algebra, applying Demorgan s theorems and knowing the function table of XOR and XNOR gates the Boolean expression can be simplified. Simplifying the expression based on SOP form results in A BCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Virtual University of Pakistan Page 142

2 = A B( = A B( = ( C D + CD)( AB + AB) + ( ( AB + AB) = ( C D)( A B) + ( C D)( A B) = ( A B) ( C D) Figure 14.2 Odd-Parity Generator Circuit The parity generator circuit shown checks the 4-bit number, generates a parity bit which along with the 4-bit data is transmitted. The receiver calculates the parity bit of the received 4-bit data and compares it with the parity sent. If the received and calculated parity bits are the same, then no error has occurred. An XOR gate is used to detect parity errors. Table 14.2 Input Output Received Calculated Error Output Parity Bit Parity Bit Table 14.2 Detecting Error at Receiver End Operation of Odd-Parity Generator Circuit The timing diagram shows the operation of the Odd-Parity generator circuit. Figure The A, B, C and D timing diagrams represent the changing 4-bit data values. During time interval t the 4-bit data value is, during time interval t1, the data value changes to 1. Similarly during time intervals t2, t3, t4 up to t8 the data values change to 1, 11, 1 and 1 respectively. During interval t the output of the two XOR gates is and, therefore the output of the XNOR gate is 1. At interval t1, the outputs of the two XOR gates is 1 and, therefore the output of the XNOR gate is. The output P can similarly be traced for intervals t2 to t8. Virtual University of Pakistan Page 143

3 D C B A t t1 t2 t3 t4 t5 t6 t7 t8 P Figure 14.3 Timing Diagram of Odd-Parity Generator Circuit XOR and XNOR Gates XOR and XNOR gates are used to implement the Odd-Parity Generator Circuit. An XNOR is also used to check for single bit errors at the Receiver end. Both, the XOR and XNOR gates perform simple comparison functions. The XOR gate detects dissimilar inputs, where as the XNOR gate looks for similar inputs. Both, the gates can be considered as functional devices as each gate performs a simple specific function. The XOR and XNOR gates are implemented using a combination of NOT, AND and OR gates. Since the function performed by the XOR and XNOR gate is commonly used in digital circuits therefore XOR and XNOR gates are available in Integrated circuit form which can be readily used instead of implementing an XOR and XNOR circuit based on NOT-AND-OR combination of gates. The function table for the Parity Error detector circuit is identical to the truth table of an XOR gate. Boolean expression representing the function of an XOR gate is A B + AB which is implemented using a combination NOT, AND and OR gates. Figure 14.3 Implementation of XOR Gate The XNOR gate is also implemented using a combination of NOT, AND and OR gates. The function of the XNOR gate is represented in term of Boolean expression as A B + AB. Figure 14.4 Virtual University of Pakistan Page 144

4 Figure 14.4 Implementation of XNOR Gate Combinational Function Devices Digital circuits are formed by the combination of Logic Gates. Most Combinational circuits perform standard and useful functions such as addition, comparison, decoding and encoding, multiplexing and de-multiplexing, selection and enabling of devices and many more operations. Implementation of these standard functional devices through combination of gates takes up considerable space, therefore these functional devices are implemented as MSI or Medium Scale Integrated Chips. The simplest of these functional devices can be considered to be the NAND and NOR gates which perform the AND-NOT and OR-NOT functions. The XOR and XNOR Gates are also a combination of NOT-AND-OR gates which perform functions to detect dissimilar and similar inputs. Half Adder and Full Adder A single bit binary adder circuit basically adds two bits and a carry bit, generated by the addition of the least significant bits. The output of the single bit adder circuit generates a sum bit and a carry bit. A single digit binary adder circuit therefore has three inputs, one representing single bit number A, the other representing the single bit number B and the third bit represents the single bit carry. The single bit binary adder has two bit output. One bit represents the Sum between numbers A and B. The other bit represents the carry bit generated due to addition. In Digital logic terminology the adder which has been described is known as a full adder. An adder circuit that only has two bit input representing the two single bit numbers A and B and does not have the carry bit input from the least significant digit is regarded as a half-adder. The block diagrams represent a Half-Adder and a Full-Adder. Figure Half-Adder A Half-Adder can be fully described in terms of its Function table, its Sum and Carry Out Boolean Expressions and the circuit Implementation. Virtual University of Pakistan Page 145

5 A A B B C out C in C out Half-Adder Figure 14.5 Full-Adder Block diagrams of Half-Adder and Full-Adder Half-Adder Function Table The Half-Adder has a 2-bit input and a 2-bit output. The function table of the Half-Adder has two input columns representing the two single bit numbers A and B. The function table also has two output columns representing the Sum bit and Carry Out bit. Table 14.3 Input Output A B Sum Carry Out Table 14.3 Half-Adder Function Table Half-Adder Sum & Carry Out Boolean Expressions The Sum and Carry Out expressions of the Half-Adder can be determined from the function table. The Half-Adder Sum and Carry Out outputs are defined by the expressions Sum = AB + AB = A B CarryOut = AB Half-Adder Logic Circuit The Half-Adder Logic Circuit can be directly implemented from the Sum and Carry Out Boolean expressions. Figure 14.6 Figure 14.6 Half-Adder Logic Circuit Virtual University of Pakistan Page 146

6 2. Full-Adder A Full-Adder can be fully described in terms of its Function table, its Sum and Carry Out Boolean Expressions and the circuit Implementation. Full-Adder Function Table The Full-Adder has a 3-bit input and a 2-bit output. The function table of the Full- Adder has three input columns representing the two single bit numbers A, B and the Carry In bit. The function table also has two output columns representing the Sum bit and Carry Out bit. Table 14.4 Input Output A B Carry In(C) Sum Carry Out Table 14.4 Full-Adder Function Table Full-Adder Sum & Carry Out Boolean Expressions The Sum and Carry Out expressions of the Full-Adder can be determined from the function table. The Full-Adder Sum and Carry Out outputs are defined by the expressions Sum = ABC + ABC + ABC + ABC Sum = A( BC + BC) + A( BC + BC) Sum = A( B C) + A( B C) Sum = A B C CarryOut = ABC + ABC + ABC + ABC CarryOut = C( AB + AB) C + C) CarryOut = C( A B) + AB Full-Adder Logic Circuit The Full-Adder Logic Circuit can be directly implemented from the Sum and Carry Out Boolean expressions. Figure 14.7 Virtual University of Pakistan Page 147

7 A B C in C out Figure 14.7 Full-Adder Logic Circuit Forming a Full-Adder using Half-Adders A 1-bit Full-Adder cane be implemented by combining together two Half-Adders. Figure 14.8 Figure14.8 Implementing a Full-Adder using two Half-Adders The Sum output of the first Half-Adder is ( A B) The Carry Out of the first Half-Adder is AB The Sum output of the second Half-Adder is ( A B) Cin = ( A B Cin ) The Carry Out of the second Half-Adder is ( A B) Cin The output of the OR gate is AB + ( A B) Cin Parallel Binary Adders Single bit Full or Half Adders do not perform any useful function. To add two 4- bit numbers a 4-bit adder is required. Four single bit Full-Adders are connected together to form a 4-bit Parallel Adder capable of adding two 4-bit binary numbers. Figure Virtual University of Pakistan Page 148

8 The two 4-bit numbers A and B are applied at the circuit inputs A -3 and B -3 respectively. The 4-bit Sum output of the Parallel Adder is available at outputs S -3. The Carry In to the circuit is set to. (C in =). The Carry is available at C out. Figure bit Parallel Binary Adder Carry Propagation Parallel Binary Adders can be implemented by connecting the required number of 1-bit full adders in a configuration represented in figure However, there is a practical limitation to the number of 1-bit Full-Adders that can be connected in parallel. In the 4-bit Parallel Adder, the Most significant bit adder which adds bits A 3, B 3 and the Carry bit C 3, can not proceed until it receives the Carry from the next least significant 1- bit adder which adds bits A 2, B 2. The A 2 B 2 bit adder can not proceed unless it receives the carry input C 2 from the A 1, B 1 adder. The A 1, B 1 adder in tern depends on A, B adder to provide the carry input. Thus the carry has to propagate through each Full-adder before it reaches the last or most significant full adder. Assume that each gate has a propagation delay of 1 nsec. A 1-bit Full Adder generates a Carry out after 3 nsec. For a 4-bit Parallel Adder Full-adder the Carry out from the most significant adder would be after 12 nsec. The delay can increase to prohibitive levels if 8-bit, 16-bit or 64-bit parallel adders are implemented. 64-bit parallel adders are used by computers. Look-Ahead Carry Circuits To overcome the problem of carry propagation or carry ripple, Look-Ahead carry generator circuits are used. These circuits look at the bits to be added and decide if a higher order carry is to be generated. The Look-Ahead Carry Circuits although increase the circuitry but they provide a practical solution to the prohibitive delays that are caused by the ripple carry in parallel adders. Consider the Full-Adder Circuit The output ( A B) at output P of the XOR gate and the output AB at output G of the AND gate is available simultaneously after one gate delay. If the G output of the AND gate is 1, the Carry Out has to be a 1 no matter what is the other input of the Carry Out OR gate. The Sum and Carry Out can be expressed in terms of P and G gate outputs. The P output is called the Carry Propagate. The G output is called the Carry Generate Virtual University of Pakistan Page 149

9 Figure 14.1 Full-Adder with Carry Generate and Carry Propagate Carry Outputs in terms of Carry Propagate and Carry Generate The Sum and Carry Out Boolean expressions can be rewritten in terms of P, Carry Propagate and G, Carry Generate terms. Sum = P C CarryOut = CP + G Writing the expressions for the four Carry Out terms C 1, C 2, C 3 and C 4 in terms of Carry Propagate P and Carry Generate G. C 1 = CP + G C 2 = C1P1 + G1 = P1 ( CP + G ) + G1 = G1 + P1 G + PP1 C C 3 = G2 + P2G1 + P1P 2G + PP1 P2C C 3 = C2P2 + G2 = P2 ( G1 + P1G + PP1 C ) + G2 = G2 + P2G1 + P1P 2G + PP1 P2C C 4 = G3 + P3G 2 + P2P3 G1 + P1P 2P3G + PP1 P2P3 C where Pn = A n Bn and G n = A nbn The Look-Ahead Carry Generator Circuit is shown. Figure The inputs to the Look-Ahead Carry Generator Circuit are the Carry Propagate terms P, P 1, P 2 and P 3 and Carry Generate terms G, G 1, G 2 and G 3. The Carry Propagate P, P 1, P 2 and P 3 and Carry Generate terms G 1, G 2, G 3 and G 4 are generated by the XOR and AND gates after one gate delay. The Outputs of the Look-Ahead Carry Generator Circuit are C 1, C 2, C 3 and C 4. The output C 1 is generated by the circuit represented by the expression C 1 = CP + G which requires an AND gate to generate the product term C P and a second level two input OR gate to sum the terms C P and G. Thus C 1 is available after two gate delays. Virtual University of Pakistan Page 15

10 C A P B P S G C A 1 P 1 B 1 P 1 S 1 G 1 A 2 P 2 Look-Ahead Carry Generator C 1 B 2 P 2 S 2 G 2 C 2 A 3 P 3 B 3 P 3 S 3 G 3 C 3 C4 Figure Look-Ahead Carry Generator Similarly, the output C 2 is generated by the circuit represented by the expression C 2 = G1 + P1G + PP1 C which requires a 2-input and 3-input AND gates to generate the product terms P G and 1 P P1C respectively. A second level three input OR gate is required to sum the three terms. Thus C 2 is also available after two gate delays. The output C 3 is generated by the circuit represented by the expressionc 3 = G2 + P2G1 + P1P 2G + PP1 P2C. The expression is implemented by a combination of three AND gates having 2, 3 and 4 inputs respectively and a single 4- input OR gate. Again two levels of gates is used, C 3 is available after a gate delay of two. Finally, the output C 4 is generated by the circuit represented by the expressionc 4 = G3 + P3G 2 + P2P3 G1 + P1P 2P3G + PP1 P2P3 C. To implement the expression two levels of 2, 3, 4 and 5 input AND gates and a single 5 input OR gate is used. C 4 is available after a gate delay of two. Thus for Carry outputs C 1, C 2, C 3 and C 4 the delay is of the order of two after the Propagate Carry and Generate Carry terms become available. Virtual University of Pakistan Page 151

11 MSI Adders 4-bit parallel Adders are available as Medium Scale Integrated Circuits. These circuits use the Look-Ahead Carry Circuitry to remove the carry ripple. The two ICS are 74LS83A and 74LS283. Both the devices are functionally identical, however they are not pin compatible. These devices are packaged as 16-pin devices. The division of the 16 pins is 4 pins for the 4-bit input A 4 pins for the 4-bit input B 4 pins for the 4-bit output Sum 1 pin for Carry In 1 pin for Carry Out 1 pin for Circuit Power Supply 1 pin for Circuit GND The 74LS83A or the 74LS283 can be cascaded together to form 8-bit, 12-bit or 16-bit Parallel Adders. Figure The Carry Out pin of one IC is connected to the Carry In pin of the other IC. A (8-11) B (8-11) A (4-7) B (4-7) A (-3) B (-3) C12 74LS283 C8 74LS283 C4 74LS283 C= Sum (8-11) Sum (4-7) Sum (-3) Figure bit Parallel Adder using three 74LS283 ICs Virtual University of Pakistan Page 152

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1