International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May-2014 ISSN

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1 645 ANALYSIS AND IMPLEMENTATION OF TRIVIAL DELAY BASED ADDERS G.Priyadarshini,J.Robert Theivadas,Ranganathan Vijayaraghavan ABSTRACT- In present-day, all digital devices are designed to be portable in which IC s are much compressed. When IC s turn into compacted ones, downsides in power and area get increased. Adders are requisite component for every contemporary Digital IC. A non-heuristic method for the analysis and optimization of adders with the intention of reducing delay is proposed here. Implementation with 20 different Boolean Expressions is done, which are constructed using CMOS logic and the performance is analyzed in terms of delay and area. This work is done with the Tanner EDA tool - 250nm technology. From this exploration the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. These adders are incorporated in existing adder based circuits like BCD Adder, Array Multiplier, Booth multiplier, etc., and its performance is evaluated in terms of maximum combinational path delay and power. INDEX TERMS- Boolean Expressions, BCD adder, Delay Calculation, Mux Based adders. 1 INTRODUCTION A n adder plays a vital role in many digital The simplest gate delay model sets a circuit designs including Digital Signal fixed propagation time, or gate delay Td, from a Processors (DSPs) and microprocessors. In gate input to a gate output. Propagation delay is electronics, an adder or summer is a digital a technical term that can have a different circuit that performs addition of numbers. In meaning depending on the context. In modern computers adders reside in the electronics, the propagation delay, or gate delay, arithmetic logic unit (ALU) where other is the length of time which starts when the input operations are performed. Although adders can to a logic gate becomes stable and valid, to the be constructed for many numerical time that the output of that logic gate is stable representations, such as Binary-coded decimal or and valid. Often this refers to the time required excess-3, the most common adders operate on for the output to reach from 10% to 90% of its binary numbers. Most of the VLSI applications final output level when the input changes. like Digital Signal processing, video and image Reducing gate delays in digital circuits allows processing and microprocessors extensively use them to process data at a faster rate and improve arithmetic operation. Thus adders form the basic overall performance. Logic gates that compute part for most of the applications. In all kind of other functions require more transistors, some of digital IC s the transistor sizes are reduced to which are connected in series, making them make the device portable. Making these devices poorer than inverters at driving current. Thus a more and more compact lead to the increase in NAND gate must have more delay than an delay and power. Delay forms the most inverter with similar transistor sizes that drives important part of the device operation. Increased the same load. The method of logical effort delay affects the overall performance. Lesser the quantifies these effects to simplify delay analysis delay, higher is the performance. for individual logic gates and multi-stage logic networks. G.Priyadarshini is currently pursuing masters degree program in VLSI Design in Anand Institute of Higher Technology, under Anna University, India. dharshupri.g@gmail.com J.Robert Theivadas is working as Assistant Professor in ECE Department at Anand Institute of Higher Technology, under Anna University, India. roberttheivadas@gmail.com Various approaches have been made till date to reduce the delay in most of the circuits. Especially the adders with reduced delay will assist more in the performance escalation. Some of the different approaches made till date are discussed in the next section.

2 646 2 EXISTING TECHNIQUE 2.1 GDI TECHNIQUE The circuit operation of GDI Based Full Adders is exactly the same as that of previous SERF module. Sum bit is obtained from the output of the second stage of XOR and XNOR circuit while Carry bit (Cout) is calculated by multiplexing B and Cin controlled by (A XNOR B). The main advantage of this technique is that which is having two extra input pins to use which makes it flexible than usual CMOS design. It is also a genius design which is very power efficient without huge amount of transistor count. The major problem of a GDI cell is that it requires twin-well CMOS or silicon on insulator (SOI) process to realize. Thus, it will be more expensive to realize a GDI chip. Moreover if only standard p-well CMOS process is used, the GDI scheme will face the problem of lacking driving capability which makes it more expensive and difficult to realize as a feasible chip. 2.2 STATIC ENERGY RECOVERY FULL ADDER In this type of adder the energy recovering logic reuses charge and therefore consumes less power than non-energy recovering logic. The circuit consists of two XNORs realized by 4 transistors. Sum is generated from the output of the second stage XNOR circuit. The cout can be calculated by multiplexing a and cin controlled by (a b). Let us consider that there is a capacitor at the output node of the first XNOR module. To illustrate static energy recovery let us consider an example where initially a=b=0 and then a changes to 1. When a and b both equals to zero the capacitor is charged by VDD. In the next stage when b reaches a high voltage level keeping a fixed at a low voltage level, the capacitor discharges through a. Some charge is retained in a. Hence when a reaches a high voltage level we do not have to charge it fully. So the energy consumption is low here. The main drawback is that circuit produces full-swing at the output nodes. But it fails to provide so for the internal nodes. As the power consumption by the circuit reduces the circuit becomes slower. Also it cannot be cascaded at low power supply due to multiple threshold problems. 2.3 MINORITY FULL ADDER MinFA is a Minority based Full Adder which has 34 Transistors. Although this low-power CMOS based design is modular, it has a long critical path and not a high driving capability at Sum output node, which leads to long propagation delay. 2.4 INVERTER BASED FULL ADDER InvFA is an Inverter based Full Adder it has seven capacitors and four inverters. The main advantage of this design is its simplicity, modularity and low number of transistors. Although it has driving capability at the output nodes, its relatively long critical path results in long delay. 2.5 BRIDGE STYLE BCFA which is designed based on the low-power CMOS Bridge style and Capacitors network includes four capacitors and 12 transistors. Besides its low power consumption, low driving power of the bridge circuit to the 2C capacitor and the inverter, which generate Cout, increase the delay of the circuit. Finally, this design produces complementary outputs and needs two additional inverters at the output nodes. In Proposal work,using different Boolean expression for a one-bit full adder gives effective result than these existing one. In Section III, gives the proposed method.simulation and Results in Section IV,Future Work in Section V and Conclusion in Section VI. 3 PROPOSED FULL ADDER DESIGN As very well known,adders form mandatory component of every current Integrated circuits for example consider Ripple carry adder,carry select adder,etc all has the use of full-adder,if any one of the full-adder gets a drawback it affects the whole circuit.so optimization of fulladder is carried out here.it is done by constructing 20 different Boolean expressions that are constructed in cmos logic and performance is analysed

3 647 Digital circuits use ON-OFF devices to implement operations of a system of logic called TWO-VALUED using BOOLEAN EXPRESSION. The statement may take the form of algebraic expressions, logic block diagrams, or truth tables, as well as circuits.boolean expression is composed of variables and terms.the simplification of Boolean expression can lead to more effective computer programs, algorithms and circuits. FORMS OF BOOLEAN EXPRESSIONS can be reduced to a single term and in the reduced term, above variable will be absent (C + C` =1).e.g. ; (A.B C`) + (A. B. C)=A.B(C` + C)=A.B If there are two terms which are identical except that one contains an extra variable, reduce them into a single term by dropping the larger one.e.g: B.C + A`. B. C=B. C(1 + A`)=B. C(1) = B. C With this method, 20 different full adders are designed and their equations are as follows: SUM = A B C 1 SUM OF PRODUCT FORM (SOP) : SUM = A B C W=(X` Y` Z`) + (X` Y Z`) + (X` Y` Z) Maxterm : It is obtained from an OR term of n variables with each variables being unprimed, if corresponding bit is a 0 and primed if it is 1. MINIMIZATION OF BOOLEAN EXPRESSION Convert equation from POS form to SOP form. Remove parenthesis if any in the expression. If there are two or more identical terms,keep only one of them and drop the other. If a variable and its complements are present in a term,reduce it to 0. (A. A`=0). Group two terms of which one contains a variable and other its complement, except for which both are identical. They SUM = AB + BAC + AB + ABC SUM = A B + AB C + (A B + AB) Each term in such an expression is called minterm. CARRY = (A B )C + AB CARRY = (A B) C + AB Minterm : It is obtained from an AND term of n CARRY = (AB + A B variables with C each variable being primed, if corresponding bit of binary number is 0 and CARRY = AB. AC. BC unprimed, if it is 1. CARRY = A B B + A B. C 2 PRODUCT OF SUM (POS): CARRY = (A B). C AB CARRY = C. (A. B) + C. (A + B) S=(P + Q + R) (P+ Q` + R) (P`+ Q + R) CARRY = AB + AC + BC Each term in such an expression is called maxterm. CARRY = (A B)C. AB CARRY = AB + A B. C CARRY = AB. AC. BC CARRY = A. B AC. BC CARRY = AB.. A + B C CARRY = A B. C AB CARRY = A + B + A B + C CARRY = (A B) C AB All these expressions are designed using CMOS in Tanner and delay is measured.result showed that full adder with XOR-MUX had the lowest delay and power.the delay and power results are represented in Table 1.BCD adder is designed in Tanner by replacing the full adder in the original circuit with few of these different adders and delay was measured and

4 648 compared.results show that a BCD adder with XOR-MUX based full adder had lesser delay than the same circuit with other different full adder.an example circuit with XOR-AND-OR(1) based BCD adder and the XOR-MUX based BCD adder is represented in Fig 1& 2.Their delay measurement is also shown in the Table 2 4 SIMULATION AND RESULTS The simulation results are shown in Table 1.The performance of all the full adders has been analyzed in terms of delay and transistor count. TABLE 1 SIMULATION RESULTS OF DIFFERENT ADDERS Fig.1 BCD ADDER USING XOR,AND,OR FULL ADDER USING DELAY (ps) AREA XOR,AND,OR XNOR,AND,OR XNOR,AND,OR,NOT XOR,AND XOR,NAND,NEG OR XNOR,NAND,NOT XNOR,NAND XOR,NAND XOR,MUX XNOR,MUX,NOT XOR,XNOR,MUX XOR,AND,OR,MUX XNOR,AND,OR,MUX NAND NOR XOR,NAND,NOR,NOT XNOR,NAND,NOR,NOT XNOR,NOR,NOT,OR XOR,NOR,NOT,OR XOR,AND,OR(2) The least delay adder with XOR-MUX based is incorporated in BCD adder.thus Fig.1 and Fig.2 Shows BCD adder with higher delay and BCD adder with lesser delay respectively. The adder that has lesser delay shows,the use of XOR-MUX based adder and also the other few adders are also used and compared. Fig.2 BCD ADDER USING XOR-MUX COMPARISON AND RESULT TABLE 2 COMPARISON RESULTS BCD ADDER USING DELAY (ns) XOR,AND,OR(1) n XOR,MUX n XOR,NOR,NOT,OR n XOR,AND n NOR n

5 649 5 FUTURE WORK These different adders is implemented in higher applications like Booth multiplier,array multiplier,etc.to show that adder using XOR- MUX gives the lesser delay,area and power when compared with the other adders. 6 CONCLUSION Delay is the time required for the output to reach from 10% to 90% of its final output level when the input changes. Reducing gate delays in digital circuits allows them to process data at a faster rate and improve overall performance. The proposed 20 different Boolean expression are simulated using Xilinx ISE 9.1 Tool. Delay for all the adders are calculated and the final result shows that MUX based adders have lesser delay.when implementin those different adders in BCD adder shows the result that the adder using XOR-MUX shows the least delay and thus comparison and simulation is presented. REFERENCES [1] R.UMA, Vidya Vijayan, M.Mohanapriya, Sharon Paul, (February 2012) Area, Delay and Power Comparison of Adder Topologies,International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1 [2] Padma Devi, Ashima Girdher, Balwinder Singh, (June 2010) Improved Carry Select Adder with Reduced Area and Low Power Consumption, International Journal of Computer Applications ( )Vol 3 No.4 [3] Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha, (12,2012) A high Speed 8 Transistor Full Adder using Novel 3 Transistor XOR Gates, International Journal of Electrical and computer engineering. [4] Y. Sunil Gavaskar Reddy and V.V.G.S.Rajendra Prasad,(Sep-2011) Power Comparison of CMOS and Adiabatic Full adder, International Journal of VLSI design&communication Systems(VLSICS) Vol.2, No.3 [5] R.Naveen,K.Thanushkodi, C.Saranya, (Aug- 2013) Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders, International Journal of Electronics & Communication Engineering Research. [6] SaradinduPanda,A.Banerjee,B.Maji,Dr.A.Mukh opadhyay,(sep2012) Power and Delay Comparison in between Different types of Full Adder Circuits, International Journal of Advanced Research in Electrical,Electronics and instrumentation Engineering. [7] Balamurugan Dharmaraj, Anbarasu Paulthurai, Design of High Speed Multiplier Using Minority Function Based Full Adder Canadian Journal on Electrical and Electronics Engineering Vol. 4, No. 2, April 2013.