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1 University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year
2 Lecture 7 & 8 NAND and XOR Implementations Combinational Design Procedure
3 NAND-NAND & NOR-NOR Networks DeMorgan s Law: (a + b) = a b (a b) = a + b a + b = (a b ) (a b) = (a + b ) = = = = push bubbles or introduce in pairs or remove pairs.
4 NAND-NAND Networks Mapping from AND/OR to NAND/NAND a b c d a) b) c) d)
5 Implementations of Two-level Logic Sum-of-products AND gates to form product terms (minterms) OR gate to form sum Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product
6 Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate
7 Two-level Logic using NAND Gates (cont d) OR gate with inverted inputs is a NAND gate de Morgan's: A' + B' = (A B)' Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed
8 Conversion Between Forms Convert from networks of ANDs and ORs to networks of NANDs and NORs Introduce appropriate inversions ("bubbles") Each introduced "bubble" must be matched by a corresponding "bubble" Conservation of inversions Do not alter logic function Example: AND/OR to NAND/NAND A B C D Z A B C D NAND NAND NAND Z
9 Conversion Between Forms (cont d) Example: verify equivalence of two forms A B C D Z A B C D NAND NAND NAND Z Z = [ (A B)' (C D)' ]' = [ (A' + B') (C' + D') ]' = [ (A' + B')' + (C' + D')' ] = (A B) + (C D)
10 Exclusive-OR and Exclusive-NOR Circuits Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels.
11 Exclusive-NOR Circuits Exclusive-NOR (XNOR) : Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level.
12 Exclusive-NOR Circuits XNOR gate may be used to simplify circuit implementation.
13 XOR Function XOR function can also be implemented with AND/OR gates (also NANDs).
14 XOR Function Even function even number of inputs are. Odd function odd number of inputs are.
15 Parity Generation and Checking FIGURE 4-25 XOR gates used to implement the parity generator and the parity checker for an even-parity system.
16 Design Procedure (Mano) Design a circuit from a specification.. Determine number of required inputs and outputs. 2. Derive truth table 3. Obtain simplified Boolean functions 4. Draw logic diagram and verify correctness A B C R S S = A + B + C R = ABC
17 Previously, we have learned Boolean algebra can be used to simplify expressions, but not obvious: how to proceed at each step, or if solution reached is minimal. Have seen five ways to represent a function: Boolean expression truth table logic circuit minterms/maxterms Karnaugh map
18 Combinational logic design Use multiple representations of logic functions Use graphical representation to assist in simplification of function. Use concept of don t care conditions. Example - encoding BCD to seven segment display. Similar to approach used by designers in the field.
19 BCD to Seven Segment Display Used to display binary coded decimal (BCD) numbers using seven illuminated segments. BCD uses s and s to represent decimal digits - 9. Need four bits to represent required digits. Binary coded decimal (BCD) represents each decimal digit with four bits a b c g e d f
20 BCD to seven segment display List the segments that should be illuminated for each digit. a,b,c,d,e,f b,c 2 a,b,d,e,g 3 a,b,c,d,g 4 b,c,f,g 5 a,c,d,f,g 6 a,c,d,e,f,g 7 a,b,c 8 a,b,c,d,e,f,g 9 a,b,c,d,f,g f e a g d b c
21 BCD to seven segment display Dec e d c b a z y x w Derive the truth table for the circuit. Each output column in one circuit. Inputs Outputs
22 BCD to seven segment display Find minimal sum-of-products representation for each output For segment a : yz wx Note: Have only filled in ten squares, corresponding to the ten numerical digits we wish to represent.
23 Don t care conditions (BCD display)... Fill in don t cares for undefined outputs. Note that these combinations of inputs should never happen. Leads to a reduced implementation For segment a : yz wx X X X X Put in X (don t care), and interpret as either or as desired. X X
24 Don t care conditions (BCD display)... Circle biggest group of s and Don t Cares. Leads to a reduced implementation For segment a : yz wx X X X X F a = y X X
25 Don t care conditions (BCD display) Circle biggest group of s and Don t Cares. Leads to a reduced implementation For segment a : yz wx X X X X F a2 = w X X
26 Don t care conditions (BCD display)... Circle biggest group of s and Don t Cares. All s should be covered by at least one implicant For segment a : yz yz wx wx X X X X X X X X X X X X F a3 = xz F a4 = xz
27 Don t care conditions (BCD display)... Put all the terms together Generate the circuit For segment a : yz wx X X X X F = y + w + xz + xz X X
28
29 Summary Need to formulate circuits from problem descriptions. Determine number of inputs and outputs 2. Determine truth table format 3. Determine K-map 4. Determine minimal SOP o There may be multiple outputs per design o Solve each output separately
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