TABLE 3-2 Truth Table for Code Converter Example

Size: px
Start display at page:

Download "TABLE 3-2 Truth Table for Code Converter Example"

Transcription

1 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-28 TABLE 3-2 Truth Table for Code Converter Example Decimal Digit Input BCD Output Excess-3 A B C D W Y Z Truth Table for Code Converter Example

2 TABLE 3-3 Truth Table for BCD to Seven-Segment Decoder BCD Input Seven-Segment Decoder A B C D a b c d e f g All other inputs 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458 T-29 Truth Table for BCD to Seven-Segment Decoder

3 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-3 A Inputs A 2 A Outputs D 7 D 6 D 5 D 4 D 3 D 2 D D Truth Table for 3 to 8-Line Decoder

4 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-3 A Inputs A 2 A Outputs D 7 D 6 D 5 D 4 D 3 D 2 D D Truth Table for Octal-to-Binary Encoder

5 T-32 Truth Table of Priority Encoder TABLE 3-6 Truth Table of Priority Encoder Inputs Outputs D 3 D 2 D D A A V 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

6 T-33 Signed Binary Numbers g y Decimal Signed 2 s Complement Signed s Complement Signed Magnitude by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

7 T-34 Example of Design Hierarchy and Reusable Blocks Input dd function Z O (a) Symbol for circuit 2 A A A 2 3-Input odd function B O A A A 2 3-Input odd function B O A A A 2 3-Input odd function B O Z O A A A 2 3-Input odd B function O (d) Exclusive-OR block as interconnect- ed NANDs (b) Circuit as interconnected 3-input odd function blocks A A B O A 2 (c) 3-input odd function circuit as interconnected exclusive-or blocks 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

8 T-35 Diagrams Representing the Hierarchy for Figure input odd function 9-input odd function 3-input odd function 3-input odd function 3-input odd function 3-input odd function 3-input odd function OR OR OR OR OR OR OR OR OR -NAND (a) (b) 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

9 T-36 Logic Diagram for Analysis Example A T 3 B C T F D T 2 T 4 T 5 F by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

10 T-37 Logic Diagram for Binary Adder Y Z T T 2 T 3 S C 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

11 T-38 ViewDraw Schematic for Binary Adder in Figure 3-5 Y S Z C 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

12 T-39 ViewTrace Input and Output Waveforms for the Binary Adder Schematic in Figure 3-6 Y Z S D i g i t a l C T 5 n n 5 n Time(Seconds) 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

13 T-4 Maps for BCD to Excess-3 Code Converter CD AB C CD AB C A B A B D D W = A + BC + BD = BC + BD + BCD CD AB C CD AB C A B A B D D Y = CD + CD Z = D 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

14 T-4 Logic Diagram of BCD to Excess-3 Code Converter A W B C Y D Z 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

15 T-42 Seven-Segment Display a f b e g d c (a) Segment designation (b) Numeric designation for display 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

16 T-43 3 to 8-Line Decoder D = A 2 A A D = A 2 A A A A A 2 D 2 = A 2 A A D 3 = A 2 A A D 4 = A 2 A A D 5 = A 2 A A D 6 = A 2 A A D 7 = A 2 A A 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

17 T-44 A 2 to 4-Line Decoder with Enable Input A D D E A A D D D 2 D 3 D 2 (b) Truth table A E D 3 (a) Logic diagram 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

18 T-45 A 3 to 8 Decoder Constructed with Two 2 to 4 Decoders A A A 2 2 to 4 Decoder Enable D D D 2 D to 4 Decoder Enable D 4 D 5 D 6 D by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

19 T-46 Implementing a Binary Adder Using a Decoder 3 to 8 Decoder Z 2 2 S Y C 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

20 T-47 Logic Diagram of a 4-Input Priority Encoder D 3 D 2 D A A D V 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

21 T-48 4 to -Line Multiplexer S Function table S S Y S D D D D 2 D 3 D Y D 2 D by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

22 T-49 4 to -Line Multiplexer with Transmission Gates S S D D TG (S = ) TG (S = ) TG (S = ) Y D 2 D 3 TG (S = ) TG (S = ) TG (S = ) 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

23 T-5 Quadruple 2 to -Line Multiplexer A Y A Y A 2 Y 2 A 3 Y 3 B B Function table E S Output Y All 's Select A Select B B 2 B 3 S (select) E (enable) 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

24 T-5 Implementing a Boolean Function with a Multiplexer 4 x MU Y S S Y Z F F = Z F = Z F = F = Z Z 2 3 F (a) Truth table (b) Multiplexer implementation 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

25 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-52 A B C D F = D F = F = D F F = F = D F = F = F = D C B A D S F S S 2 8 x MU Implementing a Four-Input Function with a Multiplexer

26 T-53 to 4-Line Demultiplexer E D S S D D 2 D by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

27 T-54 Logic Diagram of Full Adder Y Half adder Half adder S C Z 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

28 T-55 4-Bit Ripple Carry Adder B 3 A 3 B 2 A 2 B A B A FA C 3 C 2 C FA FA FA C C 4 S 3 S 2 S S 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

29 T-56 Development of a Carry Lookahead Adder B A S G P C B 3 A 3 B 2 A 2 B A B A PFA PFA PFA PFA S 3 G 3 P 3 C 3 S 2 G 2 P 2 C 2 S G P C S G P C 4 Ripple Carry C (a) G 3 P 3 C 3 G 2 P 2 C 2 G P C G P C G -3 Carry Lookahead P -3 (b) 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

30 T-57 Block Diagram of Binary Adder-Subtractor A B Binary adder Borrow Binary subtractor Complement Selective 2's complementer Subtract/Add S Quadruple 2-to- multiplexer Result 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

31 T-58 Adder-Subtractor Circuit B 3 A 3 B 2 A 2 B A B A S C 3 C 2 C FA FA FA FA C C 4 S 3 S 2 S S 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

32 T-59 A 2-Bit by 2-Bit Binary Multiplier B B A A A B B A B A B A B A B C 3 C 2 C C A B B HA HA C 3 C 2 C C 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

33 T-6 A 4-Bit by 3-Bit Binary Multiplier A B 3 B 2 B B A B 3 B 2 B B Addend 4-bit adder Augend Sum and output carry A 2 B 3 B 2 B B Addend 4-bit adder Augend Sum and output carry C 6 C 5 C 4 C 3 C 2 C C 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

34 T-6 Block Diagram of BCD Adder Addend Augend K 4-bit binary adder Z 3 Z 2 Z Z Input carry Output carry C 4-bit binary adder S 3 S 2 S S BCD sum 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

35 T-62 Standard Graphics Symbol for a 4-Bit Parallel Adder 3 3 Cl P Q S S 3 CO 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

36 T-63 Standard Graphics Symbols for Decoders /Y /Y 2 4 EN EN 2 3 (a) 3-to-8 line (b) 2-to-4 line EN A A D D D 2 D 3 (c) Truth table for decoder in (b) with EN and outputs negative logic 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

37 T-64 Example of a G-(AND) Dependency Y A B C G G2 2 Y A B C & & & (a) Block with G and G2 (b) Equivalent interpretation 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

38 T-65 Standard Graphics Symbols for Multiplexers E EN MU E S MU EN G S S S 2 D D D 2 D 3 D 4 D 5 D 6 D G 7 Y A B A B A 2 B 2 A 3 B 3 Y Y Y 2 Y 3 (a) 8 to line (b) Quadruple 2 to line 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

39 T-66 Graphics Symbol for an Adder-Subtractor S A A A 2 A 3 B B B 2 B 3 3 4/ 4 4 4/3 P Q S 3 S N4 Cl CO 997 by Prentice-Hall, Inc. MANO & KIME Upper Saddle River, New Jersey 7458

40 T-67 Qualifying Symbols Associated with Inputs and Outputs Symbol Description Active-low input or output Logic negation input or output EN Enable input: enables all outputs when active Dynamic input Three-state output Open-circuit output Output with special amplification 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458

COMBINATIONAL CIRCUIT

COMBINATIONAL CIRCUIT Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits

More information

4:Combinational logic circuits. 3 July

4:Combinational logic circuits. 3 July 4:Combinational logic circuits 3 July 2014 1 overview What is combinational logic circuit? Examples of combinational logic circuits Binary-adder Binary-subtractor Binary-multiplier Decoders Multiplexers

More information

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1 LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design

More information

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation

More information

Unit 3. Logic Design

Unit 3. Logic Design EE 2: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Unit 3 Chapter Combinational 3 Combinational Logic Logic Design - Introduction to Analysis & Design

More information

BCD Adder. Lecture 21 1

BCD Adder. Lecture 21 1 BCD Adder -BCD adder A 4-bit binary adder that is capable of adding two 4-bit words having a BCD (binary-coded decimal) format. The result of the addition is a BCD-format 4-bit output word, representing

More information

UNIT-IV Combinational Logic

UNIT-IV Combinational Logic UNIT-IV Combinational Logic Introduction: The signals are usually represented by discrete bands of analog levels in digital electronic circuits or digital electronics instead of continuous ranges represented

More information

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: ECE QUESTION BANK SUBJECT NAME: DIGITAL SYSTEM DESIGN SEMESTER III SUBJECT CODE: EC UNIT : Design of Combinational Circuits PART -A ( Marks).

More information

CHW 261: Logic Design

CHW 261: Logic Design CHW 6: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Copyright 6 by Pearson Education, Inc. Upper Saddle

More information

Combinational Logic Circuits. Combinational Logic

Combinational Logic Circuits. Combinational Logic Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The

More information

Combinational Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

Combinational Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science Combinational Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design 2 Combinational logic A combinational circuit

More information

Asst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02)

Asst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02) 2145230 Aircraft Electricity and Electronics Asst. Prof. Thavatchai Tayjasanant, PhD Email: taytaycu@gmail.com aycu@g a co Power System Research Lab 12 th Floor, Building 4 Tel: (02) 218-6527 1 Chapter

More information

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay)   CSC S.J. Park. Announcement Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification

More information

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits 1 Module-4 Design and Analysis of Combinational Circuits 4.1 Motivation: This topic develops the fundamental understanding and design of adder, substractor, code converter multiplexer, demultiplexer etc

More information

UNIT III. Designing Combinatorial Circuits. Adders

UNIT III. Designing Combinatorial Circuits. Adders UNIT III Designing Combinatorial Circuits The design of a combinational circuit starts from the verbal outline of the problem and ends with a logic circuit diagram or a set of Boolean functions from which

More information

Combinational Circuits DC-IV (Part I) Notes

Combinational Circuits DC-IV (Part I) Notes Combinational Circuits DC-IV (Part I) Notes Digital Circuits have been classified as: (a) Combinational Circuits: In these circuits output at any instant of time depends on inputs present at that instant

More information

Experiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa

Experiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa Experiment # 4 Binary Addition & Subtraction Eng. Waleed Y. Mousa 1. Objectives: 1. To study adder and subtractor circuits using logic gates. 2. To construct and test various adders and subtractor circuits.

More information

Class Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitII 2. SKILLS ADDRESSED: Learning I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd Chapter 6 组合逻辑电路函数 Floyd, Digital Fundamentals, th ed 29 Pearson Education, Upper 28 Pearson Saddle River, Education NJ 7458. All Rights Reserved Summary Half-Adder

More information

Adder (electronics) - Wikipedia, the free encyclopedia

Adder (electronics) - Wikipedia, the free encyclopedia Page 1 of 7 Adder (electronics) From Wikipedia, the free encyclopedia (Redirected from Full adder) In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers

More information

IES Digital Mock Test

IES Digital Mock Test . The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code

More information

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Digital Applications () Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering systems,

More information

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As

More information

University of Technology

University of Technology University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 7 & 8 NAND and XOR Implementations Combinational Design Procedure NAND-NAND & NOR-NOR Networks DeMorgan

More information

Project Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus.

Project Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus. Project Part 1 A Circuit Description and Diagrams: The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus. Shown below is a jpeg screenshot

More information

Department of Electronics and Communication Engineering

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of

More information

Digital Electronics. Functions of Combinational Logic

Digital Electronics. Functions of Combinational Logic Digital Electronics Functions of Combinational Logic Half-dder Basic rules of binary addition are performed by a half adder, which has two binary inputs ( and B) and two binary outputs (Carry out and Sum).

More information

EXPERIMENT NO 1 TRUTH TABLE (1)

EXPERIMENT NO 1 TRUTH TABLE (1) EPERIMENT NO AIM: To verify the Demorgan s theorems. APPARATUS REQUIRED: THEORY: Digital logic trainer and Patch cords. The digital signals are discrete in nature and can only assume one of the two values

More information

Encoders. Lecture 23 5

Encoders. Lecture 23 5 -A decoder with enable input can function as a demultiplexer a circuit that receives information from a single line and directs it to one of 2 n possible output lines. The selection of a specific output

More information

Digital Electronics 8. Multiplexer & Demultiplexer

Digital Electronics 8. Multiplexer & Demultiplexer 1 Module -8 Multiplexers and Demultiplexers 1 Introduction 2 Principles of Multiplexing and Demultiplexing 3 Multiplexer 3.1 Types of multiplexer 3.2 A 2 to 1 multiplexer 3.3 A 4 to 1 multiplexer 3.4 Multiplex

More information

2 Building Blocks. There is often the need to compare two binary values.

2 Building Blocks. There is often the need to compare two binary values. 2 Building Blocks 2.1 Comparators There is often the need to compare two binary values. This is done using a comparator. A comparator determines whether binary values A and B are: 1. A = B 2. A < B 3.

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page

More information

Function Table of an Odd-Parity Generator Circuit

Function Table of an Odd-Parity Generator Circuit Implementation of an Odd-Parity Generator Circuit The first step in implementing any circuit is to represent its operation in terms of a Truth or Function table. The function table for an 8-bit data as

More information

UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS

UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS STRUCTURE 2. Objectives 2. Introduction 2.2 Simplification of Boolean Expressions 2.2. Sum of Products 2.2.2 Product of Sums 2.2.3 Canonical

More information

Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006

Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 COE/EE2DI4 Midterm Test #1 Fall 2006 Page 1 Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 Instructions: This examination paper includes 10 pages and 20 multiple-choice questions starting

More information

Subtractor Logic Schematic

Subtractor Logic Schematic Function Of Xor Gate In Parallel Adder Subtractor Logic Schematic metic functions, including half adder, half subtractor, full adder, independent logic gates to form desired circuits based on dif- by integrating

More information

Introduction. BME208 Logic Circuits Yalçın İŞLER

Introduction. BME208 Logic Circuits Yalçın İŞLER Introduction BME208 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 1 Lecture Three hours a week (three credits) No other sections, please register this section Tuesday: 09:30 12:15

More information

Digital. Design. R. Ananda Natarajan B C D

Digital. Design. R. Ananda Natarajan B C D Digital E A B C D 0 1 2 3 4 5 6 Design 7 8 9 10 11 12 13 14 15 Y R. Ananda Natarajan Digital Design Digital Design R. ANANDA NATARAJAN Professor Department of Electronics and Instrumentation Engineering

More information

MSI Design Examples. Designing a circuit that adds three 4-bit numbers

MSI Design Examples. Designing a circuit that adds three 4-bit numbers MSI Design Examples In this lesson, you will see some design examples using MSI devices. These examples are: Designing a circuit that adds three 4-bit numbers. Design of a 4-to-16 Decoder using five 2-to-4

More information

Digital Logic and Design (Course Code: EE222) Lecture 14: Combinational Contd.. Decoders/Encoders

Digital Logic and Design (Course Code: EE222) Lecture 14: Combinational Contd.. Decoders/Encoders Indian Institute of Technology Jodhpur, Year 28 29 Digital Logic and Design (Course Code: EE222) Lecture 4: Combinational Contd.. Decoders/Encoders Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in

More information

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two

More information

Logic Design I (17.341) Fall Lecture Outline

Logic Design I (17.341) Fall Lecture Outline Logic Design I (17.341) Fall 2011 Lecture Outline Class # 07 October 31, 2011 / November 07, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative

More information

Laboratory Manual CS (P) Digital Systems Lab

Laboratory Manual CS (P) Digital Systems Lab Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification

More information

COMBINATIONAL LOGIC CIRCUIT First Class. Dr. AMMAR ABDUL-HAMED KHADER

COMBINATIONAL LOGIC CIRCUIT First Class. Dr. AMMAR ABDUL-HAMED KHADER COMBINATIONAL LOGIC CIRCUIT First Class 1 BASIC ADDER Adders are important in computers and also in other types of digital system in which numerical data are processed. An understanding of the basic operation

More information

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering

More information

Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction

Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction Objectives: 1. To study adder and subtractor circuits using logic gates. 2. To construct and test various adders and subtractor

More information

Gates and Circuits 1

Gates and Circuits 1 1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior

More information

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING (Regulation 2013) EE 6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL 1 SYLLABUS OBJECTIVES: Working Practice in simulators / CAD Tools / Experiment

More information

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT HAPTER FUNTION OF OMBINATIONAL LOGI IRUIT OUTLINE HALF-ADDER ANF FULL ADDER IRUIT -BIT PARALLEL BINARY RIPPLE ARRY ADDER -BIT PARALLEL BINARY ARRY LOOK- AHEAD ADDER BD ADDER IRUIT DEODER ENODER MULTIPLEXER

More information

Logic Circuit Design

Logic Circuit Design Logic Circuit Design we have studied Truth Tables Logic gates Logic algebra K-maps 1 All these are tools Tools Truth Tables Logic gates Logic algebra K-maps 2 All these are tools Tools Truth Tables Logic

More information

Practical Workbook Logic Design & Switching Theory

Practical Workbook Logic Design & Switching Theory Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering

More information

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R05310402 Set No. 1 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS

More information

Gates and and Circuits

Gates and and Circuits Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

More information

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e. Name: Multiple Choice 1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.) 8 2.) The output of an OR gate with

More information

DELD UNIT 3. Question Option A Option B Option C Option D Correct Option A B C

DELD UNIT 3. Question Option A Option B Option C Option D Correct Option A B C Class : S.E.Comp Matoshri College of Engineering and Research Center Nasik Department of Computer Engineering Digital Elecronics and Logic Design (DELD) UNIT - III Subject : DELD Sr. No. Question Option

More information

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100 EC 40 MODEL TEST PAPER - 1 ELECTRONIC CIRCUITS Time: Three Hours Maximum Marks: 100 Answer five questions, taking ANY TWO from Group A, any two from Group B and all from Group C. All parts of a question

More information

Chapter 3 Combinational Logic Design

Chapter 3 Combinational Logic Design Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 2 Combinational Logic Overview Part -Implementation Technology and Logic Design Design Concepts Fundamental concepts of

More information

Topic Notes: Digital Logic

Topic Notes: Digital Logic Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 20 Topic Notes: Digital Logic Our goal for the next couple of weeks is to gain a reasonably complete understanding of how

More information

Paper No. Name of the Paper Theory marks Practical marks Periods per week Semester-I I Semiconductor

Paper No. Name of the Paper Theory marks Practical marks Periods per week Semester-I I Semiconductor Swami Ramanand Teerth Marathwada University, Nanded B. Sc. First Year Electronics Syllabus Semester system (To be implemented from Academic Year 2009-10) Name of the Theory marks Practical marks Periods

More information

Gujarat University B. Sc. Electronics Semester I: ELE (Effective from: )

Gujarat University B. Sc. Electronics Semester I: ELE (Effective from: ) Unit - I: Components and Instrumentation: Gujarat University B. Sc. Electronics Semester I: ELE - 101 Passive Circuit devices: Resistors, nonlinear resistors, inductors, types of inductors, capacitors,

More information

This Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.

This Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations. Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 5 Lecture Title:

More information

Digital Electronic Concepts

Digital Electronic Concepts Western Technical College 10662137 Digital Electronic Concepts Course Outcome Summary Course Information Description Career Cluster Instructional Level Total Credits 4.00 Total Hours 108.00 This course

More information

EEE 301 Digital Electronics

EEE 301 Digital Electronics EEE 301 Digital Electronics Lecture 1 Course Contents Introduction to number systems and codes. Analysis and synthesis of digital logic circuits: Basic logic functions, Boolean algebra,combinational logic

More information

Electronics. Digital Electronics

Electronics. Digital Electronics Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital

More information

DELD MODEL ANSWER DEC 2018

DELD MODEL ANSWER DEC 2018 2018 DELD MODEL ANSWER DEC 2018 Q 1. a ) How will you implement Full adder using half-adder? Explain the circuit diagram. [6] An adder is a digital logic circuit in electronics that implements addition

More information

DIGITAL ELECTRONICS QUESTION BANK

DIGITAL ELECTRONICS QUESTION BANK DIGITAL ELECTRONICS QUESTION BANK Section A: 1. Which of the following are analog quantities, and which are digital? (a) Number of atoms in a simple of material (b) Altitude of an aircraft (c) Pressure

More information

16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)

16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154) 16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154) Aim: To design multiplexers and De-multiplexers using gates and ICs. (74150, 74154) Components required: Digital IC Trainer kit,

More information

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS 6 Credit Hours Prepared by: Dennis Eimer Revised Date: August, 2007 By Dennis Eimer Division of Technology Dr. John Keck, Dean

More information

Lab 2: Combinational Circuits Design

Lab 2: Combinational Circuits Design Lab : Combinational Circuits Design PURPOSE: The purpose of this laboratory assignment is to investigate the design of combinational circuits using SSI circuits and basic logic gates such as ANDs, ORs,

More information

Combinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations

Combinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations Combinational Logic Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations Copyright (c) 2012 Sean Key Combinational Logic Design

More information

Electrical, Electronic and Communications Engineering Technology/Technician CIP Task Grid

Electrical, Electronic and Communications Engineering Technology/Technician CIP Task Grid Secondary Task List 100 SAFETY 101 Describe OSHA safety regulations. 102 Identify, select, and demonstrate proper hand tool use for electronics work. 103 Recognize the types and usages of fire extinguishers.

More information

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER CONTENTS 3.1 Introduction to Basic Gates 3.2 Analysing A Combinational Logic Circuit 3.3 Design A Combinational Logic Circuit From Boolean Expression

More information

DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR

DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR e-issn 2455 1392 Volume 4 Issue 9, September 2018 pp. 9 16 Scientific Journal Impact Factor : 4.23 http://www.ijcter.com DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR Hemant Singh Bisht

More information

Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits. Sequence detector

Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits. Sequence detector Lecture 3 Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits Counter Sequence detector TNGE11 Digitalteknik, Lecture 3 1 Adder TNGE11 Digitalteknik,

More information

Syllabus for: Electronics for F Y B Sc (Electronics) Semester- 1 (With effect from June 2014) PAPER I: Basic Electrical Circuits

Syllabus for: Electronics for F Y B Sc (Electronics) Semester- 1 (With effect from June 2014) PAPER I: Basic Electrical Circuits Unit I: Passive Devices Syllabus for: Electronics for F Y B Sc (Electronics) Semester- 1 (With effect from June 2014) PAPER I: Basic Electrical Circuits Resistors, Fixed resistors & variable resistors,

More information

Satish Chandra, Assistant Professor, P P N College, Kanpur 1

Satish Chandra, Assistant Professor, P P N College, Kanpur 1 8/7/4 LOGIC GTES CE NPN Transistor Circuit COMINTIONL LOGIC Satish Chandra ssistant Professor Department of Physics P PN College, Kanpur www.satish4.weebly.com circuit with an output signal that is logical

More information

Digital Logic Design ELCT 201

Digital Logic Design ELCT 201 Faculty of Information Engineering and Technology Dr. Haitham Omran and Dr. Wassim Alexan Digital Logic Design ELCT 201 Winter 2017 Midterm Exam Second Chance Please tick the box of your major: IET MET

More information

VLSI Implementation & Design of Complex Multiplier for T Using ASIC-VLSI

VLSI Implementation & Design of Complex Multiplier for T Using ASIC-VLSI International Journal of Electronics Engineering, 1(1), 2009, pp. 103-112 VLSI Implementation & Design of Complex Multiplier for T Using ASIC-VLSI Amrita Rai 1*, Manjeet Singh 1 & S. V. A. V. Prasad 2

More information

DIGITAL FUNDAMENTALS

DIGITAL FUNDAMENTALS Instructor s Resource Manual to accompany DIGITAL FUNDAMENTALS Ninth Edition Thomas L. Floyd Upper Saddle River, New Jersey Columbus, Ohio Copyright 26 by Pearson Education, Inc., Upper Saddle River, New

More information

Combinational Logic Design CH002

Combinational Logic Design CH002 Combinational Logic Design CH002 Figure 2.1 Circuit as a black box with inputs, outputs, and specifications Figure 2.2 Elements and nodes Figure 2.3 Combinational logic circuit Figure 2.4 Two OR implementations

More information

Positive and Negative Logic

Positive and Negative Logic Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 4 Lecture Title:

More information

2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.

2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. 2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion

More information

Dhanalakshmi College of Engineering

Dhanalakshmi College of Engineering Dhanalakshmi College of Engineering Manimangalam, Tambaram, Chennai 601 301 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY III SEMESTER -

More information

DHANALAKSHMI COLLEGE OF ENGINEERING MANIMANGALAM. TAMBARAM, CHENNAI B.E. ELECTRICAL AND ELECTRONICS ENGINEERING III SEMESTER EE6311 Linear and Digital Integrated Circuits Laboratory LABORATORY MANUAL CLASS:

More information

Veer Narmad South Gujarat University, Surat

Veer Narmad South Gujarat University, Surat Unit I: Passive circuit elements (With effect from June 2017) Syllabus for: F Y B Sc (Electronics) Semester- 1 PAPER I: Basic Electrical Circuits Resistors, resistor types, power ratings, resistor colour

More information

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices Lecture 5 Doru Todinca Textbook This chapter is based on the book [RothKinney]: Charles H. Roth, Larry L. Kinney, Fundamentals

More information

Spec. Instructor: Center

Spec. Instructor: Center PDHonline Course E379 (5 PDH) Digital Logic Circuits Volume III Spec ial Logic Circuits Instructor: Lee Layton, P.E 2012 PDH Online PDH Center 5272 Meadow Estatess Drive Fairfax, VA 22030-6658 Phone &

More information

ELECTRONICS ADVANCED SUPPLEMENTARY LEVEL

ELECTRONICS ADVANCED SUPPLEMENTARY LEVEL ELECTRONICS ADVANCED SUPPLEMENTARY LEVEL AIMS The general aims of the subject are : 1. to foster an interest in and an enjoyment of electronics as a practical and intellectual discipline; 2. to develop

More information

(a) (b) (c) (d) (e) (a) (b) (c) (d) (e)

(a) (b) (c) (d) (e) (a) (b) (c) (d) (e) Exercises 97 Exercises Exercise 2. Write a oolean equation in sum-of-products canonical form for each of the truth tables in Figure 2.8. (d) (e) C C C D Figure 2.8 Truth tables for Exercises 2. and 2.3

More information

Fan in: The number of inputs of a logic gate can handle.

Fan in: The number of inputs of a logic gate can handle. Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

ECE 124 Digital Circuits and Systems Winter 2011 Introduction Calendar Description:

ECE 124 Digital Circuits and Systems Winter 2011 Introduction Calendar Description: ECE 124 Digital Circuits and Systems Winter 2011 Introduction Calendar Description: Number systems. Switching algebra. Hardware description languages. Simplification of Boolean functions. Combinational

More information

GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM. Course Title: Digital Electronics (Code: )

GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM. Course Title: Digital Electronics (Code: ) GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM Course Title: Digital Electronics (Code: 3322402) Diploma Programmes in which this course is offered Semester in which offered Power

More information

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28 Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

Unit 1 Foundations in Electronics - Lesson 1.1 Introduction to Electronics Standards Essential Question Enduring Understandings

Unit 1 Foundations in Electronics - Lesson 1.1 Introduction to Electronics Standards Essential Question Enduring Understandings Course: DIGITAL ELECTRONICS- PROJECT LEAD THE WAY (DE-PLTW) Year: 2017-2018 Teacher: Mr. Christopher Reynolds/ Mr. Kenneth Rice Unit 1 Foundations in Electronics - Lesson 1.1 Introduction to Electronics

More information

Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru

Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru Prerequisites Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru Course Title :Digital Electronics Lab I Course Code : 15EC2P Semester : II Course Group

More information

NORTH MAHARASHTRA UNIVERSITY. F.Y. B. Sc. Electronics. Syllabus. Wieth effect from june2015

NORTH MAHARASHTRA UNIVERSITY. F.Y. B. Sc. Electronics. Syllabus. Wieth effect from june2015 Syllabus Wieth effect from june2015 Paper- I, Semester I ELE-111: Analog Electronics I Unit- I:Introduction to Basic Circuit Components Definition and unit, Circuit Symbol, Working Principle, Classification

More information

R & D Electronics DIGITAL IC TRAINER. Model : DE-150. Feature: Object: Specification:

R & D Electronics DIGITAL IC TRAINER. Model : DE-150. Feature: Object: Specification: DIGITAL IC TRAINER Model : DE-150 Object: To Study the Operation of Digital Logic ICs TTL and CMOS. To Study the All Gates, Flip-Flops, Counters etc. To Study the both the basic and advance digital electronics

More information

NORTH MAHARASHTRA UNIVERSITY, JALGAON

NORTH MAHARASHTRA UNIVERSITY, JALGAON , JALGAON Syllabus for F.Y.B.Sc. Semester I and II ELECTRONICS (w. e. f. June 2012) F.Y. B. Sc. Subject Electronics Syllabus Structure Semester Code Title Number of Lectures ELE-111 Paper I : Analog Electronics

More information