Logic Design I (17.341) Fall Lecture Outline

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1 Logic Design I (17.341) Fall 2011 Lecture Outline Class # 07 October 31, 2011 / November 07, 2011 Dohn Bowden 1

2 Today s Lecture Administrative Main Logic Topic Homework 2

3 Course Admin 3

4 Administrative Admin for tonight Syllabus Review 4

5 Syllabus Syllabus Exam #2 will be a take home exam will be passed out tonight Lab due dates need to be modified 5

6 Syllabus Review Week Date Topics Chapter Lab Report Due 1 09/12/11 Introduction to digital systems and number systems /19/11 Binary Codes and Boolean Algebra /26/11 Boolean Algebra (continued) /03/11 Examination 1 X 10/10/11 No Class - Holiday 5 10/17/11 Application of Boolean Algebra /24/11 Karnaugh Maps and /31/11 Multi-Level Gate Circuits and Lab lecture /07/11 Examination /14/11 Combinational Circuit Design and Simulation Using Gates /23/11 Multiplexers, Decoders. Encoder, and PLD /28/11 Introduction to VHDL /05/11 Examination /12/11 Review /19/11 Final Exam 6

7 Exam #2 Take home exam DUE next week November 14,

8 Questions? 8

9 Chapter 7 MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES 9

10 Objectives 10

11 Objectives Multi-Level Gate Circuits NAND and NOR Gates Design of Two-Level Circuits Using NAND and NOR Gates Design of Multi-Level NAND and NOR Gate Circuits Circuit Conversion Using Alternative Gate Symbols Design of Two-Level, Multiple-Output Circuits Multiple-Output NAND and NOR Circuits 11

12 Multi-Level Gate Circuits 12

13 Terminology 13

14 Terminology AND-OR circuit A two-level circuit composed of a level of AND gates followed by an OR gate at the output OR-AND circuit A two-level circuit composed of a level of OR gates followed by an AND gate at the output OR-AND-OR circuit A three-level circuit composed of a level of OR gates followed by a level of AND gates followed by an OR gate at the output 14

15 Terminology Circuit of AND and OR gates Implies no particular ordering of the gates The output gate may be either AND or OR 15

16 Tree Diagrams 16

17 Tree Diagrams Tree diagram created from a Given expression 17

18 Tree Diagrams Tree diagram created from a Given expression Has 4 Levels 18

19 Tree Diagrams Tree diagram created from a Given expression Has 4 Levels Each node on a tree diagram represents a gate 6 Gates 19

20 Tree Diagrams Tree diagram created from a Given expression Has 4 Levels Each node on a tree diagram represents a gate 6 Gates The number of gate inputs is written beside each node 13 Inputs 20

21 Tree Diagrams Corresponding circuit for the Four-Level Realization of Z 21

22 Tree Diagrams Each node represents a gate 22

23 Tree Diagrams The number of gate inputs is written beside each node 23

24 Changing the Number of Levels 24

25 Partially Multiplying Out We can change the expression for Z to three levels by Partially multiplying out the expression Z = (AB + C)[(D + E) + FG] + H = AB(D + E) + C(D + E) + ABFG + CFG + H 25

26 Partially Multiplying Out Now Three Levels 26

27 Partially Multiplying Out Now Three Levels 6 gates 27

28 Partially Multiplying Out Now Three Levels 6 gates 19 inputs 28

29 Partially Multiplying Out The same gate can be used multiple times when applicable 29

30 Example 30

31 Example Example Find a circuit of AND and OR gates to realize f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14) Consider solutions with Two levels of gates and Three levels of gates Try to minimize the number of gates and the total number of gate inputs Assume that all variables and their complements are available as inputs 31

32 Example First simplify f by using a K-Map f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14) 32

33 Example f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14) 33

34 Example K-Map solution leads directly to a two-level AND-OR gate circuit f = a c d + bc d + bcd +acd 34

35 Example Now Factoring our expression f = a c d + bc d + bcd +acd Yields f = c d(a + b) + cd (a + b) Which is an OR-AND-OR circuit 35

36 Example f = c d(a + b) + cd (a + b) OR-AND-OR 36

37 Example Analysis Both of the previous solutions have an OR gate at the output A solution with an AND gate at the output might have fewer gates or gate inputs A two-level OR-AND circuit corresponds to a product-of-sums expression for the function Product-of-sums expression can be obtained from the 0 s on the K-map 37

38 Example From the 0 s on the K-map we get f = (c + d)(a + b + c)(c + d )(a + b + c ) 38

39 Example The expression below leads directly to a two-level OR-AND circuit f = (c + d)(a + b + c)(c + d )(a + b + c ) OR-AND 39

40 To get a Three-Level Circuit 40

41 Three-level circuit with an AND gate output To get a three-level circuit with an AND gate output We partially multiply out using (X + Y)(X + Z) = X + Y Z f = (c + d)(a + b + c)(c + d )(a + b + c ) To get f = [c + d(a + b)][c + d (a + b)] 41

42 Three-level circuit with an AND gate output The following equation f = [c + d(a + b)][c + d (a + b)] Would require four levels of gates to realize However if we multiply out d (a + b) and d(a + b) we get f = (c + a d + bd)(c + ad + bd ) 42

43 Three-level circuit with an AND gate output f = (c + a d + bd)(c + ad + bd ) Leads directly to a three-level AND-OR-AND circuit 43

44 Minimum Solution 44

45 Minimum Solution Determination For our last example The best two-level solution had An AND gate at the output and The best three-level solution had An OR gate at the output In general to be sure of obtaining a minimum solution One must find both the circuit with the AND-gate output and the one with the OR-gate output 45

46 Minimum Solution Determination Both of the circuits the AND-gate output and the one with the OR-gate output need to be looked at to determine a minimum solution 46

47 NAND and NOR Gates 47

48 NAND Gates 48

49 NAND Gates Below shows a three-input NAND gate The small circle (or bubble ) at the gate output Indicates inversion 49

50 NAND Gates Therefore the NAND gate is equivalent to An AND gate followed by an inverter 50

51 NAND Gates The NAND gate output is F = (ABC) = A + B + C 51

52 NAND Gates An n-input NAND gate is 52

53 NOR Gates 53

54 NOR Gates Below shows a three-input NOR gate The small circle (or bubble ) at the gate output Indicates inversion 54

55 NOR Gates Therefore the NOR gate is equivalent to An OR gate followed by an inverter 55

56 NOR Gates The NOR gate output is F = (A + B + C) = A B C 56

57 NOR Gates An n-input NOR gate is 57

58 Functionally Complete Set of Gates 58

59 Functionally Complete Set of Gates To be a functionally complete set of gates You can get OR AND and NOT with the elements 59

60 Functionally Complete Set of Gates AND and NOT are a functionally complete set of gates because OR can also be realized using AND and NOT 60

61 Functionally Complete Set of Gates Any function can be realized using only NAND gates NOT AND OR 61

62 Design of Two-Level NAND-and NOR-Gate Circuits 62

63 Design of Two-Level NAND- Gate Circuits 63

64 Design of Two-Level NAND-Gate Circuits A two-level circuit composed of AND and OR gates is easily converted to A circuit composed of NAND gates or NOR gates Use F = (F ) and then applying DeMorgan s laws (X 1 + X X n ) = X 1 X 2 X n (X 1 X 2 X n ) = X 1 + X X n 64

65 Design of Two-Level NAND-Gate Circuits For example using F = (F ) the following illustrates conversion of a minimum sum-of-products form to several other two-level forms F = A + BC + B CD = [(A + BC + B CD) ] AND-OR = [A (BC ) (B CD) ] NAND-NAND = [A (B + C) (B + C + D )] OR-NAND = A + (B + C) + (B + C + D ) NOR-OR The next slide shows the above circuits 65

67 Design of Two-Level NOR-Gate Circuits 67

68 Design of Two-Level NOR-Gate Circuits If we want a two-level circuit containing only NOR gates Start with the minimum product-of-sums form for F instead of the minimum sum-of-products 68

69 Design of Two-Level NOR-Gate Circuits After obtaining the minimum product-of-sums from a K-map F can be written in the following two-level forms again using F = (F ) and then applying DeMorgan s laws F = (A + B + C)(A + B + C )(A + C + D) OR-AND = {[(A + B + C)(A + B + C )(A + C + D)] } = [(A + B + C) + (A + B + C ) + (A + C + D) ] NOR-NOR = (A B C + A BC + A CD ) AND-NOR = (A B C ) (A BC) (A CD ) NAND-AND The next slide shows the above circuits 69

71 Design of Two-Level NAND and NOR-Gate Circuits The previous eight possible two-level forms are degenerate In the sense that they cannot realize all switching functions Consider, for example, the following NAND-NOR circuit: 71

72 Design of Two-Level NAND and NOR-Gate Circuits For example the following NAND-NOR circuit From this example it is clear that the NAND-NOR form can realize only a product of literals and not a sum of products!!! 72

73 Design of Minimum Two-Level NAND-NAND Circuits 73

74 Design of Minimum Two-Level NAND-NAND Circuits Procedure for designing a minimum two-level NAND-NAND circuit 1. Find a minimum sum-of-products expression for F 2. Draw the corresponding two-level AND-OR circuit 3. Replace all gates with NAND gates leaving the gate interconnection unchanged If the output gate has any single literals as inputs complement these literals 74

75 Example 75

76 Example First Find a minimum sum-of-products expression for F F = l 1 + l P 1 + P 2 + Then Draw the corresponding two-level AND-OR circuit 76

77 Example Thirdly Replace all gates with NAND gates Leave the gate interconnection unchanged 77

78 Example Finally If the output gate has any single literals as inputs complement these literals F = l 1 + l P 1 + P 2 + F = (l 1 l 2 P 1 P 2 ) AND-OR NAND-NAND 78

79 Design of Multi-Level NAND- and NOR-Gate Circuits 79

80 Design of Multi-Level NAND- and NOR-Gate Circuits The following procedure may be used to design multi-level NANDgate circuits 1. Simplify the switching function to be realized 2. Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as OR-gate inputs 3. Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between gates unchanged, leave the inputs to levels 2,4,6, unchanged. Invert any literals which appear as inputs to levels 1,3,5, 80

81 Design of Multi-Level NAND- and NOR-Gate Circuits 81

82 Design of Multi-Level NAND- and NOR-Gate Circuits The output gate must be OR RECALL AND gate outputs cannot be used as AND-gate inputs OR-gate outputs cannot be used as OR-gate inputs 82

83 Design of Multi-Level NAND- and NOR-Gate Circuits Number the levels starting with the output gate as level 1 Replace all gates with NAND gates 83

84 Design of Multi-Level NAND- and NOR-Gate Circuits Leave all interconnections between gates unchanged Leave the inputs to levels 2,4,6, unchanged 84

85 Design of Multi-Level NAND- and NOR-Gate Circuits Invert any literals which appear as inputs to levels 1,3,5, Leave the inputs to levels 2,4,6, unchanged 85

86 Alternative Gate Symbols 86

87 Alternative Gate Symbols Logic designers who design complex digital systems often find it convenient to use more than one representation for a given type of gate For example an inverter can be represented by Inversion bubbles differ in placement 87

88 Alternative Gate Symbols Equivalent gate symbols based on DeMorgan s Laws 88

89 Using Alternate Symbols 89

90 Alternate Symbols Can use alternate symbols to facilitate analysis and design of NAND and NOR gate circuits 90

91 NAND Gate Conversion 91

92 Replace NAND gates at 1 st and 3 rd levels with alternate symbols This eliminates inversion Bubble at circuit output NAND Gate Circuit Conversion 92

93 Non - Inverting outputs are connected to Inverting inputs Inverting outputs are Connected to inverting inputs Two inversions in a row cancel s each other out. Do not need to use DeMorgan s Law [(A + B)C] is (A + B)C Due to cancellation NAND Gate Circuit Conversion 93

94 Equivalent AND-OR Circuit 94

95 Can convert to an AND-OR by Removing double Inversions and Complement single variables connected to inverted inputs when we remove the inversion from the input AND OR Gate Circuit Conversion 95

96 Conversion to NOR Gates 96

97 Can convert to a NOR Because the output gate is an AND gate and AND and OR gates alternate through the circuit Conversion to NOR Gates 97

98 Replace all OR and AND gates with NOR gates Conversion to NOR Gates 98

99 See notes below Conversion to NOR Gates 99

100 Conversion of AND-OR Circuit to NAND Gates 100

101 If AND and OR gates do not alternate We can still convert to a NAND or OR... By adding extra inverters Conversion of AND-OR Circuit to NAND Gates 101

102 AND gates to NAND gates by adding bubble to output Conversion of AND-OR Circuit to NAND Gates 102

103 OR gates to NAND gates by adding bubble to input Conversion of AND-OR Circuit to NAND Gates 103

104 Two inversions cancel Conversion of AND-OR Circuit to NAND Gates 104

105 When non-inverted drives an inverted or vice versa add an inverter Place bubble thus you get cancellation Conversion of AND-OR Circuit to NAND Gates 105

106 Whenever a variable drives an inverted input Complement the variable Conversion of AND-OR Circuit to NAND Gates 106

107 Conversion of AND-OR Circuit to NAND Gates 107

108 Design of Two-Level, Multiple- Output Circuits 108

109 Design of Two-Level, Multiple-Output Circuits Solution of digital design problems often requires the realization of several functions of the same variables Although each function could be realized separately The use of some gates in common between two or more functions sometimes leads to a more economical realization 109

110 Example 110

111 Design of Two-Level, Multiple-Output Circuits Example Design a circuit with four inputs and three outputs which realizes the functions F 1 (A, B, C, D) = Ʃ m(11, 12, 13, 14, 15) F 2 (A, B, C, D) = Ʃ m(3, 7, 11, 12, 13, 15) F 3 (A, B, C, D) = Ʃ m(3, 7, 12, 13, 14, 15) 111

112 Design of Two-Level, Multiple-Output Circuits Recall Inputs F 1 (A, B, C, D) = Ʃ m(11, 12, 13, 14, 15) F 2 (A, B, C, D) = Ʃ m(3, 7, 11, 12, 13, 15) F 3 (A, B, C, D) = Ʃ m(3, 7, 12, 13, 14, 15) Outputs 112

113 Design of Two-Level, Multiple-Output Circuits K-maps for equations F 1 (A, B, C, D) = Ʃ m(11, 12, 13, 14, 15) F 2 (A, B, C, D) = Ʃ m(3, 7, 11, 12, 13, 15) F 3 (A, B, C, D) = Ʃ m(3, 7, 12, 13, 14, 15) 113

114 Design of Two-Level, Multiple-Output Circuits Realization of functions separately Total of 9 Gates 114

115 Design of Two-Level, Multiple-Output Circuits To simplify 1 Obvious AB to both F 1 and F 3 2 ACD for F 1 A CD for F 3 Replace CD in F 2 by A CD + ACD CD is unnecessary Results in next slide 115

116 Design of Two-Level, Multiple-Output Circuits Realization of functions with shared gates Total of 7 Gates Note F 2 is realized by ABC + A CD + ACD Which is not a minimum Sum-Of-Products (SOP) Thus minimum SOP may not lead to minimal solution 116

117 Design of Two-Level, Multiple-Output Circuits Realization of functions separately Total of 9 Gates Realization of functions with shared gates Total of 7 Gates 117

118 Example 118

119 Design of Two-Level, Multiple-Output Circuits Another example of sharing gates among multiple outputs to reduce cost We have four-input and three-output circuit to be designed to realize f 1 = Ʃ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15) f 2 = Ʃ m(2, 3, 5, 6, 7, 10, 11, 14, 15) f 3 = Ʃ m(6, 7, 8, 9, 13, 14, 15) Look for common terms to save gates 119

120 Design of Two-Level, Multiple-Output Circuits Plot maps for f 1, f 2, and f 3 1 f = Ʃ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15) 2 f = Ʃ m(2, 3, 5, 6, 7, 10, 11, 14, 15) 3 f = Ʃ m(6, 7, 8, 9, 13, 14, 15) 120

121 Each Function Minimized Separately f 1 = bd + b c + ab f 2 = c + a bd f 3 = bc + ab c + (abd or ac d) Ten Gates 25 gate inputs 121

122 Inspection Of Maps f 1 = bd + b c + ab f 2 = c + a bd f 3 = bc + ab c + (abd or ac d) Inspection of maps a bd from f 2 abd from f 3 and ab c from f 3 can be used in f 1 If bd is replaced with a bd + abd then gate needed to realize bd can be eliminated Because m 10 and m 11 in f 1 are already covered by b c ab c (from f 3 ) can be used to cover m 8 and m 9 gate needed for ab can be eliminated 122

123 Minimal Solution f 1 = a bd + abd + ab c + b c f 2 = c + a bd f 3 = bc + ab c + abd 123

124 Example 124

125 In this example The best solution is obtained by not combining the circled 1 with adjacent 1 s 125

126 Example 126

127 The solution with the maximum number of common terms Is not necessarily the best solution as illustrated by this example 127

128 Multiple-Output NAND- and NOR-Gate Circuits 128

129 Multiple-Output NAND- and NOR-Gate Circuits The procedure for single-output multi-level NAND- and NORgate circuits Also applies to multiple-output circuits If all outputs are OR gates Direct conversion to a NAND-gate circuit is possible If all outputs are AND gates Direct conversion to a NOR-gate circuit is possible 129

130 Note that the single inputs to the first and third level inputs are inverted 130

131 Lab 131

132 Lab Lab Booklets will be passed out Use Student Logic Number 301 Lab report criteria is available on the class web page 132

133 Next Week 133

134 Next Week Topics Collect Exam #2 Chapter 8 Combinational Circuit Design and Simulation Using Gates 134

135 Home Work 135

136 Homework 1. Do Exam #2 2. Read Chapter 8 136

137 References 1. None 137

138 138

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1