logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs

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Neil Spencer
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1 Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces a change in the output. End of story! Inputs logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. Inputs logic system Outputs The simplest example must be an invereter. At first glance this seems to be an impossible circuit, if the input to the gate is 0 then the output is 1, but the output is connected to the input so it must have the same value. In actual fact this circuit oscillates. When the input to a gate changes the output doesn t change instantly, it takes a little time. We call this time the propagation delay. The circuit makes sense now; if the input becomes 1, a little while later the output becomes 0 so, the input becomes 0, a little while later the output becomes 1 so, the input becomes 1, a little while later the output becomes 0 and so on... The frequency of oscillation will be f = 1/2Tpd, where Tpd is the propagation delay. A typical value of Tpd might be about 10ns so the circuit would oscillate with a frequency of about 50MHz.

2 Although oscillators are very useful this one isn t! The propagation delay of gates is somewhat unpredictable so the frequency of oscillation would be difficult to guarantee with this arrangement. Now consider a similar arrangement, this time using two inverters: In this example, as long as power is applied to the circuit, the output of the second inverter (1 or 0) will always be identical to the input of the first, even without any inputs to the circuit. This is almost a memory element, it s not a lot of use to us yet as we can t change the value which is stored. We can rectify this deficiency by using NAND gates instead of inverters. The extra inputs can now be used to Set (make the output 1) and Reset the circuit (make the output 0). Normally we would draw this differently. We call this circuit a latch. Sometimes you will see it called a flip-flop but many authors prefer to reserve this title for clocked circuits which we ll see later. We can describe the operation of the circuit with a table (rather like a truth table) called an excitation table. S R Q+ 0 0 U (undefined) (set) (reset) 1 1 Q- (unchanged)

3 The + and suffices denote time; + meaning next and meaning previous. Although we might call this device a SR latch it would probably be more correct to call it a not SR latch as values of zero are used to Set and Reset it. If we build the circuit using NOR gates, or add a pair of inverters we get a true SR latch. S /Q R Q S Q R /Q Synchronous Circuits In general, we prefer to design circuits in which all of the changes are synchronised by a clock signal, meaning that all parts of the circuit change at the same time. It s quite simple to modify our latch to use a clock: S R In the example S and R can only influence the circuit when the clock is high (the value is 1) because of the NAND gates we ve added. This is still not ideal. In complex systems the output of the flip flop may ultimately influence the inputs. It is preferable that this influence is not allowed to have any effect until the next clock pulse arrives, but in the circuit above the inputs are vulnerable throughout the positive clock phase.

4 Two common techniques exist to isolate the outputs from the inputs of the flip flop, the first, known as Master Slave operation actually uses two flip flops. Master Slave In this example the first flip flop (the master) is active when the clock is high. Because of the inverter, the second flip flop (the slave) is active when the clock is low, and the contents of the master are transferred to it. Because the master is no longer active, the output of the slave can not influence the master until the clock goes high again. Another approach to this problem is Edge Triggering in which the flip flop is triggered on the clock edge. Conceptually, an edge triggered device is quite simple. a b c In the diagram, the inverter has a small but finite propagation delay so the clock signal presented to the flip flop is extremely narrow, consequently, by the time the outputs change the clock has long since gone. a b c

5 Other flip flops There are other kinds of flip flop apart from the SR. There is little to be gained from exploring the inner workings of each device, so we ll simply consider their excitation tables. We use the same notation but now the and + suffices mean before and after the clock pulse respectively. The JK flip flop J K Q+ 0 0 Q- (unchanged) (reset) (set) 1 1 /Q- (toggle) The only difference between the JK and the SR is the operation when we attempt to set AND reset it at the same time (J=K=1). Instead of the undefined operation of the SR flip flop, the JK does something useful; it toggles. In other words, if J and K are both 1, then the value of Q after the clock is NOT what it was before the clock. The D (Data or Delay) type flip flop This is a simpler device which we might think of as being a subset of the JK. It has only one input, called D. D Q The D flip flop has an output of 1 after the clock when and only when the input is a one before the clock. The D flip flop can be constructed from a JK flip flop by ensuring that J and K are always different by using an inverter. This corresponds to the middle two rows of the JK excitation table. Ignore the S & R in these diagrams real devices often have these extra inputs.

6 The T (Toggle) type flip flop This is another simple device, once again it is effectively a subset of the JK in which J and K are always the same, it corresponds to the top and bottom rows of the JK excitation table. With an input of 0 the T type does nothing (the output doesn t change), but when the input is 1 the output toggles. Again, ignore S & R in the diagrams. T Q+ 0 Q- 1 /Q- Ad Hoc Circuits We can devise a surprisingly large number of very useful circuits simply by connecting flip flops together, without using any formal design methodology. An eight bit (SISO/SIPO) shift register The diagram illustrates a 8-bit shift register. Data enters at the left hand side (provided by the switch in this example) and the entire contents of the register move one position to the right with each successive clock pulse. Shift registers are useful in many areas, for example shifting a byte one place to the right (or left) is equivalent to dividing (or multiplying) by two. Various

7 configurations of shift register are also used to convert between serial and parallel data formats. In the example above, data enters the register serially, one bit after another, but may be read in parallel, all bits together, from the Q outputs of the flip flops. Five bit ring counter The ring counter is a simple extension to the shift register. The separate Set and Reset inputs available on many flip flops are used to initialise the register and the output is fed back to the input. In this example the 1 held in the first flip flop will move one position to the right with each clock pulse, when it reaches the end it will start again. The pattern of bits on the outputs will look like: etc. Five bit Johnson Counter A slightly different arrangement in which /Q instead of Q is fed back produces a quite different sequence in the Johnson counter:

8 etc. This circuit is sometimes called a twisted ring or switch-tail. Eight bit ripple counter Although we said earlier that, in general we prefer to design circuits in which all of the changes are synchronised by a clock signal, there are one or two exceptions. The diagram above illustrates an asynchronous, or ripple counter. In this circuit, only the first flip flop is controlled by the clock. The output of this flip flop clocks the second. The second clocks the third, and so on. Consequently the clock (and the changes to the flip flops) ripples through the circuit from left to right. As its name suggests, this circuit counts, beginning with , then , up to , then starts again. Because it is so simple, and because counters are used such a lot, we often make allowances for its asynchronous behaviour. Design methods Detailed coverage of sequential logic design is beyond the scope of this module, obviously, design methods do exist so it is possibly useful to look very briefly at a simple design example. We will design a counter which counts in a rather odd sequence:

9 As our counter has 4 bits we ll use 4 D Type flip flops to build it. We begin by drawing a state transition table. On the left hand side we tabulate the counter values before the clock, and on the right hand side, the values after the clock: Present state abcd Next state abcd We ll call the four outputs a,b,c,d (for no particular reason). Looking at the top row of the table, it is telling us that when the outputs are 0010 before the clock, we want an output of 0110 after the clock. Because we are using D Type flip flops this means that the D inputs to the flip flops must be 0110 before the clock. Now let s produce K-maps for each of our flip flops: ab cd a cd ab b

10 c d cd ab cd ab The Karnaugh maps yield the flip flop input equations: Da = ab + b/c/d Dc = c/d + abc Db = b/c + b/d + /ac/d Dd = ab/c + /abc From here we can build a circuit, which would look something like:

11 This isn t quite finished! I ve deliberately left the S and R inputs floating. Imagine what happens when we first apply power to this circuit; the flip flops will probably contain zeroes (we can t guarantee this!). Looking back at our original design, the counter never has 0000 in its sequence, so if it starts in this state we have not designed a way out. There are two possible solutions to the problem: we can use the S and R inputs to the flip flops to ensure that appropriate starting conditions are used... Or we can design in the unused states. Apart from 0000 there are many other possible states which do not occur in the sequence we ve chosen. The counter has 4 bits and could therefore have sixteen different states, the missing ones are: It would make a lot of sense to put these codes in the present state side of our state transition table and on the next state side ensure that they all lead to valid states. We are building an escape route; if our counter ever ends up in a state that it shouldn t be in, it will move to one that it should be in at the next clock pulse. Modifying the design is fairly easy it is left as an exercise for the student!!!! Epilogue Many of the example circuits are available on my web pages in LogicWorks format. Download them and see how they work. If you don t understand the design example don t panic! It s only included for illustration. There are much cleverer (and easier to understand!) techniques for designing sequential logic but you have to wait a year or two for these!

EECS 150 Homework 4 Solutions Fall 2008

EECS 150 Homework 4 Solutions Fall 2008 Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring