Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits. Sequence detector

Size: px
Start display at page:

Download "Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits. Sequence detector"

Transcription

1 Lecture 3 Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits Counter Sequence detector TNGE11 Digitalteknik, Lecture 3 1

2 Adder TNGE11 Digitalteknik, Lecture 3 2

3 An n bit adder built with n Full Adders (FA) TNGE11 Digitalteknik, Lecture 3 3

4 Full adder TNGE11 Digitalteknik, Lecture 3 4

5 FA realized with NAND gates TNGE11 Digitalteknik, Lecture 3 5

6 Carry propagation delay and carry accelerator TNGE11 Digitalteknik, Lecture 3 6

7 Comparator TNGE11 Digitalteknik, Lecture 3 7

8 7 segment display, HDSP 5553 (package drawing N) TNGE11 Digitalteknik, Lecture 3 8

9 HDSP Light Emitting Diodes (LED) with a common cathode TNGE11 Digitalteknik, Lecture 3 9

10 7 segment decoder, DM9368 The DM9368 is a 7 segment decoder driver incorporating input latches and constant current output circuits to drive common cathode type LED displays directly. Pin Name Description A0 A3 A3 Address (Data) Inputs RBO Ripple Blanking Output (Active LOW) RBI Ripple Blanking Input (Active LOW) a g Segment Drivers Outputs LE Latch Enable Input (Active LOW) TNGE11 Digitalteknik, Lecture 3 10

11 DM9368 Truth Table *The RBI will blank the display only if a binary zero is stored in the latches. TNGE11 Digitalteknik, Lecture 3 11

12 Logic diagram of DM9368 TNGE11 Digitalteknik, Lecture 3 12

13 Display values of counters TNGE11 Digitalteknik, Lecture 3 13

14 D flip flopflop TNGE11 Digitalteknik, Lecture 3 14

15 Timing diagram of D flip flop flop Positive edge triggered D flip flop TNGE11 Digitalteknik, Lecture 3 15

16 Negative edge triggered D flip flop TNGE11 Digitalteknik, Lecture 3 16

17 State diagram and state table of D flip flopflop TNGE11 Digitalteknik, Lecture 3 17

18 Register TNGE11 Digitalteknik, Lecture 3 18

19 Shift register TNGE11 Digitalteknik, Lecture 3 19

20 2 bit Counter (Cnt2b) State table State diagram TNGE11 Digitalteknik, Lecture 3 20

21 Time diagram of 2 bit counter TNGE11 Digitalteknik, Lecture 3 21

22 Analysis of sequential circuit Step 1: Write logic expressions q0+ = q0 q1+ = q1*q0 + q1 *q0 Step 2: Draw a state table q1 q0 q1+ q Step 3: Draw a state diagram Schematic diagram of 2 bit Counter TNGE11 Digitalteknik, Lecture 3 22

23 D flip flop with Clear (Cl) and Preset (Pr) signals TNGE11 Digitalteknik, Lecture 3 23

24 Time diagram of D flip flop flop with Cl and Pr signals TNGE11 Digitalteknik, Lecture 3 24

25 2 bit counter with asynchronous reset signal TNGE11 Digitalteknik, Lecture 3 25

26 2 bit counter with synchronous reset signal TNGE11 Digitalteknik, Lecture 3 26

27 2 bit counter with enable signal TNGE11 Digitalteknik, Lecture 3 27

28 Time diagram of 2 bit counter with enable signal TNGE11 Digitalteknik, Lecture 3 28

29 Schematic diagram of 2 bit counter with enable signal TNGE11 Digitalteknik, Lecture 3 29

30 Sequence detector, Sdet1_ mo The type Moore sequence detector detects 3 consecutive 1 s 1s in the input data. TNGE11 Digitalteknik, Lecture 3 30

31 Time diagram of Sdet1_mo TNGE11 Digitalteknik, Lecture 3 31

32 Schematic diagram of Sdet1_mo TNGE11 Digitalteknik, Lecture 3 32

Practical Workbook Logic Design & Switching Theory

Practical Workbook Logic Design & Switching Theory Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R05310402 Set No. 1 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS

More information

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As

More information

Digital Logic Circuits

Digital Logic Circuits Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals

More information

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1 LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design

More information

Page 1. Last time we looked at: latches. flip-flop

Page 1. Last time we looked at: latches. flip-flop Last time we looked at: latches flip flops We saw that these devices hold a value depending on their inputs. A data input value is loaded into the register on the rise of the edge. Some circuits have additional

More information

DM Segment Decoder/Driver/Latch with Constant Current Sink Outputs

DM Segment Decoder/Driver/Latch with Constant Current Sink Outputs DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs General Description The DM74 is a 7-segment decoder driver incorporating input latches and output circuits to directly drive common

More information

IES Digital Mock Test

IES Digital Mock Test . The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. DECADE COUNTER; 4-BIT BINARY COUNTER The SN54/ and SN54/ are high-speed 4-bit ripple type counters partitioned into two sectio. Each counter has a divide-by-two section and either a divide-by-five () or

More information

DIGITAL ELECTRONICS QUESTION BANK

DIGITAL ELECTRONICS QUESTION BANK DIGITAL ELECTRONICS QUESTION BANK Section A: 1. Which of the following are analog quantities, and which are digital? (a) Number of atoms in a simple of material (b) Altitude of an aircraft (c) Pressure

More information

Brought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja.

Brought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja. Brought to you by Priti Srinivas Sajja PS01CMCA02 Course Content Tutorial Practice Material Acknowldgement References Website pritisajja.info Multiplexer Means many into one, also called data selector

More information

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1 Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates

More information

Digital Electronic Concepts

Digital Electronic Concepts Western Technical College 10662137 Digital Electronic Concepts Course Outcome Summary Course Information Description Career Cluster Instructional Level Total Credits 4.00 Total Hours 108.00 This course

More information

Written exam IE1204/5 Digital Design Friday 13/

Written exam IE1204/5 Digital Design Friday 13/ Written exam IE204/5 Digital Design Friday 3/ 207 08.00-2.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani 08-7904469

More information

Spec. Instructor: Center

Spec. Instructor: Center PDHonline Course E379 (5 PDH) Digital Logic Circuits Volume III Spec ial Logic Circuits Instructor: Lee Layton, P.E 2012 PDH Online PDH Center 5272 Meadow Estatess Drive Fairfax, VA 22030-6658 Phone &

More information

ICS 151 Final. (Last Name) (First Name)

ICS 151 Final. (Last Name) (First Name) ICS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 19 pages including this cover and 3 blank pages. 2. Write down your Student-Id

More information

Solutions. ICS 151 Final. Q1 Q2 Q3 Q4 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature

Solutions. ICS 151 Final. Q1 Q2 Q3 Q4 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature ICS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 19 pages including this cover and 3 blank pages. 2. Write down your Student-Id

More information

Java Bread Board Introductory Digital Electronics Exercise 2, Page 1

Java Bread Board Introductory Digital Electronics Exercise 2, Page 1 Java Bread Board Introductory Digital Electronics Exercise 2, Page 1 JBB Excercise 2 The aim of this lab is to demonstrate how basic logic gates can be used to implement simple memory functions, introduce

More information

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation

More information

PHYSICS 536 Experiment 14: Basic Logic Circuits

PHYSICS 536 Experiment 14: Basic Logic Circuits PHYSICS 5 Experiment 4: Basic Logic Circuits Several T 2 L ICs will be used to illustrate basic logic functions. Their pin connections are shown in the following sketch, which is a top view. 4 2 9 8 +5V

More information

Project Board Game Counter: Digital

Project Board Game Counter: Digital Project 1.3.3 Board Game Counter: Digital Introduction Just a few short weeks ago, most of you knew little or nothing about digital electronics. Now you are about to build and simulate a complete design.

More information

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS 6 Credit Hours Prepared by: Dennis Eimer Revised Date: August, 2007 By Dennis Eimer Division of Technology Dr. John Keck, Dean

More information

Digital Electronics Course Objectives

Digital Electronics Course Objectives Digital Electronics Course Objectives In this course, we learning is reported using Standards Referenced Reporting (SRR). SRR seeks to provide students with grades that are consistent, are accurate, and

More information

DM Segment Decoder/Driver/Latch with Constant Current Sink Outputs

DM Segment Decoder/Driver/Latch with Constant Current Sink Outputs DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs General Description The 74 is a 7-segment decoder driver incorporating input latches and output circuits to directly drive common

More information

Lecture 02: Digital Logic Review

Lecture 02: Digital Logic Review CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:

More information

Preface... iii. Chapter 1: Diodes and Circuits... 1

Preface... iii. Chapter 1: Diodes and Circuits... 1 Table of Contents Preface... iii Chapter 1: Diodes and Circuits... 1 1.1 Introduction... 1 1.2 Structure of an Atom... 2 1.3 Classification of Solid Materials on the Basis of Conductivity... 2 1.4 Atomic

More information

Module -18 Flip flops

Module -18 Flip flops 1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip

More information

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF

More information

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted SR Latch S R S R SR LATCH WITH NABL: R R' S R t+ t t+ t t t S S' LATCH WITH NABL: This is

More information

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378:

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-378: Computer Hardware esign Winter 26 SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted

More information

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true

More information

EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics

EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics I. OVERVIEW I.A Combinational vs. Sequential Logic Combinational Logic (everything so far): Outputs depend entirely on

More information

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute.  From state elements ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

More information

Lecture 20: Several Commercial Counters & Shift Register

Lecture 20: Several Commercial Counters & Shift Register EE2: Switching Systems Lecture 2: Several Commercial Counters & Shift Register Prof. YingLi Tian Nov. 27, 27 Department of Electrical Engineering The City College of New York The City University of New

More information

logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs

logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces

More information

Course Outline Cover Page

Course Outline Cover Page College of Micronesia FSM P.O. Box 159 Kolonia, Pohnpei Course Outline Cover Page Digital Electronics I VEE 135 Course Title Department and Number Course Description: This course provides the students

More information

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Winter 28 SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted

More information

Classification of Digital Circuits

Classification of Digital Circuits Classification of Digital Circuits Combinational logic circuits. Output depends only on present input. Sequential circuits. Output depends on present input and present state of the circuit. Combinational

More information

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT HAPTER FUNTION OF OMBINATIONAL LOGI IRUIT OUTLINE HALF-ADDER ANF FULL ADDER IRUIT -BIT PARALLEL BINARY RIPPLE ARRY ADDER -BIT PARALLEL BINARY ARRY LOOK- AHEAD ADDER BD ADDER IRUIT DEODER ENODER MULTIPLEXER

More information

Sequential Logic Circuits

Sequential Logic Circuits LAB EXERCISE - 5 Page 1 of 6 Exercise 5 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

TABLE 3-2 Truth Table for Code Converter Example

TABLE 3-2 Truth Table for Code Converter Example 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-28 TABLE 3-2 Truth Table for Code Converter Example Decimal Digit Input BCD Output Excess-3 A B C D W Y Z 2 3 4 5 6 7 8 9 Truth

More information

Department of Electronics and Communication Engineering

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of

More information

PRACTICAL SUMMER TRAINING Undertaken at

PRACTICAL SUMMER TRAINING Undertaken at PRACTICAL SUMMER TRAINING Undertaken at DEFENCE LABROATORY DEFENCE RESEARCH & DEVELOPMENT ORGANISATION JODHPUR 342 011 Training on Control of 16 devices through a digital keypad ABOUT DEFENCE LABORATORY,

More information

Sequential Logic Circuits

Sequential Logic Circuits Exercise 2 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure the dynamic parameters of

More information

CS302 - Digital Logic Design Glossary By

CS302 - Digital Logic Design Glossary By CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital

More information

E-Tec Module Part No

E-Tec Module Part No E-Tec Module Part No.108227 1. Additional programs for the fischertechnik Electronics Module For fans of digital technology, these additional functions are provided in the "E-Tec module". Four additional

More information

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e. Name: Multiple Choice 1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.) 8 2.) The output of an OR gate with

More information

Computer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Computer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Computer Architecture: Part II First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Combinational Circuits Flips Flops Flops Sequential Circuits 204231: Computer

More information

Figure 1.1 Mechatronic system components (p. 3)

Figure 1.1 Mechatronic system components (p. 3) Figure 1.1 Mechatronic system components (p. 3) Example 1.2 Measurement System Digital Thermometer (p. 5) Figure 2.2 Electric circuit terminology (p. 13) Table 2.2 Resistor color band codes (p. 18) Figure

More information

DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3

DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 DIGITAL ELECTRONICS Marking scheme : Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 Aim: This experiment will investigate the function of the

More information

Fan in: The number of inputs of a logic gate can handle.

Fan in: The number of inputs of a logic gate can handle. Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011 Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7//2 Ver. 72 7//2 Computer Engineering What is a Sequential Circuit? A circuit consists of a combinational logic circuit and internal memory

More information

TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC

TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SOLID-STATE DISPLAYS WITH INTEGRAL TTL MSI CIRCUIT CHIP FOR USE IN ALL SYSTEMS WHERE THE DATA TO BE DISPLAYED IS THE PULSE COUNT 6,9-mm (0.270-Inch) Character Height High Luminous Inteity TIL306 Has Left

More information

DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N

DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical

More information

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28 Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

ELECTRONICS ADVANCED SUPPLEMENTARY LEVEL

ELECTRONICS ADVANCED SUPPLEMENTARY LEVEL ELECTRONICS ADVANCED SUPPLEMENTARY LEVEL AIMS The general aims of the subject are : 1. to foster an interest in and an enjoyment of electronics as a practical and intellectual discipline; 2. to develop

More information

Design and Analysis of Automatic Car Park System with Capacity Control

Design and Analysis of Automatic Car Park System with Capacity Control Design and Analysis of Automatic Car Park System with Capacity Control Musa Mohammed Gujja & Umar Abubakar Wakta Department of Electrical and Electronic Engineering Ramat Polytechnic Maiduguri Abstract:The

More information

! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.

! Review: Sequential MOS Logic.  SR Latch.  D-Latch. ! Timing Hazards. ! Dynamic Logic.  Domino Logic. ! Charge Sharing Setup. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "

More information

10 U.L. 5 (2.5) U.L. LOGIC SYMBOL LS90 LS92 LS VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 GND = PIN 10 NC = PINS 2, 3, 4, 13

10 U.L. 5 (2.5) U.L. LOGIC SYMBOL LS90 LS92 LS VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 GND = PIN 10 NC = PINS 2, 3, 4, 13 DECADE COUNTER; DIVIDE-BY-TWEVE COUNTER; -BIT BINARY COUNTER The SN/S, SN/S and SN/S are high-speed -bit ripple type counters partitioned into two sectio. Each counter has a divide-by-two section and either

More information

R & D Electronics DIGITAL IC TRAINER. Model : DE-150. Feature: Object: Specification:

R & D Electronics DIGITAL IC TRAINER. Model : DE-150. Feature: Object: Specification: DIGITAL IC TRAINER Model : DE-150 Object: To Study the Operation of Digital Logic ICs TTL and CMOS. To Study the All Gates, Flip-Flops, Counters etc. To Study the both the basic and advance digital electronics

More information

Digital Electronics. A. I can list five basic safety rules for electronics. B. I can properly display large and small numbers in proper notation,

Digital Electronics. A. I can list five basic safety rules for electronics. B. I can properly display large and small numbers in proper notation, St. Michael Albertville High School Teacher: Scott Danielson September 2016 Content Skills Learning Targets Standards Assessment Resources & Technology CEQ: WHAT MAKES DIGITAL ELECTRONICS SO IMPORTANT

More information

DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters

DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting desig. The

More information

Introduction. BME208 Logic Circuits Yalçın İŞLER

Introduction. BME208 Logic Circuits Yalçın İŞLER Introduction BME208 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 1 Lecture Three hours a week (three credits) No other sections, please register this section Tuesday: 09:30 12:15

More information

Laboratory Manual CS (P) Digital Systems Lab

Laboratory Manual CS (P) Digital Systems Lab Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification

More information

1 Q' 3. You are given a sequential circuit that has the following circuit to compute the next state:

1 Q' 3. You are given a sequential circuit that has the following circuit to compute the next state: UNIVERSITY OF CALIFORNIA Department of Electrical Engineering and Computer Sciences C50 Fall 2001 Prof. Subramanian Homework #3 Due: Friday, September 28, 2001 1. Show how to implement a T flip-flop starting

More information

DELD MODEL ANSWER DEC 2018

DELD MODEL ANSWER DEC 2018 2018 DELD MODEL ANSWER DEC 2018 Q 1. a ) How will you implement Full adder using half-adder? Explain the circuit diagram. [6] An adder is a digital logic circuit in electronics that implements addition

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page

More information

Logic Families. Describes Process used to implement devices Input and output structure of the device. Four general categories.

Logic Families. Describes Process used to implement devices Input and output structure of the device. Four general categories. Logic Families Characterizing Digital ICs Digital ICs characterized several ways Circuit Complexity Gives measure of number of transistors or gates Within single package Four general categories SSI - Small

More information

Unit level 4 Credit value 15. Introduction. Learning Outcomes

Unit level 4 Credit value 15. Introduction. Learning Outcomes Unit 20: Unit code Digital Principles T/615/1494 Unit level 4 Credit value 15 Introduction While the broad field of electronics covers many aspects, it is digital electronics which now has the greatest

More information

Gates and Circuits 1

Gates and Circuits 1 1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior

More information

MC14513B. BCD To Seven Segment Latch/Decoder/Driver

MC14513B. BCD To Seven Segment Latch/Decoder/Driver BCDToSeven Segment Latch/Decoder/Driver CMOS MSI (LowPower Complementary MOS) The MC453B BCDtoseven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and

More information

CS/EE Homework 9 Solutions

CS/EE Homework 9 Solutions S/EE 260 - Homework 9 Solutions ue 4/6/2000 1. onsider the synchronous ripple carry counter on page 5-8 of the notes. Assume that the flip flops have a setup time requirement of 2 ns and that the gates

More information

74F161A 74F163A Synchronous Presettable Binary Counter

74F161A 74F163A Synchronous Presettable Binary Counter Synchronous Presettable Binary Counter General Description The and are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and

More information

1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as

1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered

More information

Serial Addition. Lecture 29 1

Serial Addition. Lecture 29 1 Serial Addition Operations in digital computers are usually done in parallel because that is a faster mode of operation. Serial operations are slower because a datapath operation takes several clock cycles,

More information

Lecture 3: Logic circuit. Combinational circuit and sequential circuit

Lecture 3: Logic circuit. Combinational circuit and sequential circuit Lecture 3: Logic circuit Combinational circuit and sequential circuit TRAN THI HONG HONG@IS.NAIST.JP Content Lecture : Computer organization and performance evaluation metrics Lecture 2: Processor architecture

More information

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative

More information

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100 EC 40 MODEL TEST PAPER - 1 ELECTRONIC CIRCUITS Time: Three Hours Maximum Marks: 100 Answer five questions, taking ANY TWO from Group A, any two from Group B and all from Group C. All parts of a question

More information

EE 280 Introduction to Digital Logic Design

EE 280 Introduction to Digital Logic Design EE 280 Introduction to Digital Logic Design Lecture 1. Introduction EE280 Lecture 1 1-1 Instructors: EE 280 Introduction to Digital Logic Design Dr. Lukasz Kurgan (section A1) office: ECERF 6 th floor,

More information

Positive and Negative Logic

Positive and Negative Logic Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 4 Lecture Title:

More information

DM74ALS169B Synchronous Four-Bit Up/Down Counters

DM74ALS169B Synchronous Four-Bit Up/Down Counters Synchronous Four-Bit Up/Down Counters General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74ALS169B

More information

B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics

B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics Sr. No. Date TITLE To From Marks Sign 1 To verify the application of op-amp as an Inverting Amplifier 2 To

More information

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

More information

Digital Logic Troubleshooting

Digital Logic Troubleshooting Digital Logic Troubleshooting Troubleshooting Basic Equipment Circuit diagram Data book (for IC pin outs) Logic probe Voltmeter Oscilloscope Advanced Logic analyzer 1 Basic ideas Troubleshooting is systemic

More information

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/30/2008

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/30/2008 Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/3/28 6/3/28 Computer Engineering Basic Element for Sequential CircuitsSR Latch Latch Store one-bit information (two states of and ) Two inputs,

More information

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay)   CSC S.J. Park. Announcement Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification

More information

HCF40161B SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR

HCF40161B SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED

More information

CHW 261: Logic Design

CHW 261: Logic Design CHW 6: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Copyright 6 by Pearson Education, Inc. Upper Saddle

More information

(B) The simplest way to measure the light intensity is using a photodiode in the photoconductive mode:

(B) The simplest way to measure the light intensity is using a photodiode in the photoconductive mode: PHY226 Electronics Final Preparation 1. Optoelectronics: LEDs and photodiodes (A) LEDs and photodiodes are essentially semi conductor diodes which can interact with electromagnetic waves. Explain why in

More information

HCF40103B 8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS

HCF40103B 8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS 8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS SYNCHRONOUS OR ASYNCHRONOUS PRESET MEDIUM -SPEED OPERATION : f CL =3.6MHz (Typ.) at V DD = 10V CASCADABLE QUIESCENT CURRENT SPECIF. UP TO 20V

More information

Types of Control. Programmed Non-programmed. Program Counter Hardwired

Types of Control. Programmed Non-programmed. Program Counter Hardwired Lecture #5 In this lecture we will introduce the sequential circuits. We will overview various Latches and Flip Flops (30 min) Give Sequential Circuits design concept Go over several examples as time permits

More information

74AC161B SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

74AC161B SYNCHRONOUS PRESETTABLE 4-BIT COUNTER SYNCHRONOUS PRESETTABLE 4-BIT COUNTER HIGH SPEED: f MAX = 125MHz (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 8µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) 50Ω TRANSMISSION

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,

More information

COURSE LEARNING OUTCOMES AND OBJECTIVES

COURSE LEARNING OUTCOMES AND OBJECTIVES COURSE LEARNING OUTCOMES AND OBJECTIVES A student who successfully fulfills the course requirements will have demonstrated: 1. an ability to analyze and design CMOS logic gates 1-1. convert numbers from

More information

Data Logger by Carsten Kristiansen Napier University. November 2004

Data Logger by Carsten Kristiansen Napier University. November 2004 Data Logger by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Data Logger. Education: Electronic and Computer Engineering.

More information

CONTENTS Sl. No. Experiment Page No

CONTENTS Sl. No. Experiment Page No CONTENTS Sl. No. Experiment Page No 1a Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. 2a 3a 4a 5a 6a 1b

More information

Electronic Components And Circuit Analysis

Electronic Components And Circuit Analysis Theory /Practical Theory Semester /Annual Semester Semester No. I II Swami Ramanand Teerth Marathwada University, Nanded Syllabus B. Sc. First Year ELECTRONICS Semester System (MCQ Pattern) (To Be Implemented

More information