Lecture 20: Several Commercial Counters & Shift Register

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1 EE2: Switching Systems Lecture 2: Several Commercial Counters & Shift Register Prof. YingLi Tian Nov. 27, 27 Department of Electrical Engineering The City College of New York The City University of New York (CUNY)

2 Counters A counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Synchronous Counters -- all state bits change under control of a single clock. Asynchronous (ripple) Counters -- changing state bits are used as clocks to subsequent state flip-flops (no clock signal). Clocked Clear: With both clear signal and clock triggered edge, the counter is reset. Static Clear: any clear signal appears, the counter is reset. 2

3 746 Counter (4 JK flip flops) Overflow. A 4-bit synchronous counting, 2. An static clear with active low (CLR ); 3. Loading; 4. Two enables (ENT = and ENP =, enable the counter); 5. Leading-edge triggered. 6. Labeling the bits DCBA (D represents the most significant bit) 3

4 746 Counter details for C-bit INc INc. The input for C-bit is A, B. For D-bit is A, B, and C. 2. ENT = and ENP =, enable the counter; 3. Load =, the flip flop is loaded with the value on INc. 4. Load =, y = output of A, B (brown AND gate). Count as normal.. 4

5 7463 Counter (4 JK flip flops) Overflow IN D C B A Clock. A 4-bit synchronous counting, 2. A clocked clear with active low (CLR ); 3. Loading; 4. Two enables (ENT = and ENP =, enable the counter); 5. Leading-edge triggered. 6. Labeling the bits DCBA (D represents the most significant bit) 5

6 A 8-bit Counter from 2 4-bit Counters When low counter reaches, Overflow = to enable the High counter. 6

7 Design a System by using 746 Counters Design a decimal counter that goes through the sequence:,, 2, 3, 9, repeat. How many 4-bit counters are needed? : static clear 2 () 7

8 Design a System by using 7463 Counters Design a decimal counter that goes through the sequence:,, 2, 3, 9, repeat. How many 4-bit counters are needed? : clocked clear 9 () 8

9 Up/Down Counters (749) Adding the Up/Down control signal. D/U count down, count up. 9

10 Up/Down Counters (749) Details of C-bit

11 Asynchronous Counters No clock signal, changing state bits are used as clocks to subsequent state flipflops. Clocked Clear: With both clear signal and clock triggered edge, the counter is reset. Static Clear: any clear signal appears, the counter is reset.

12 Asynchronous Counters asynchronous counter diagram 2

13 Practice Solution: Design a system the output of which is a clock pulse for every ninth input clock pulse by using counters. Solution : use counter 7463 (clocked clear), change states:,, 2, 3, 4, 5, 6, 7, 8, 3

14 Practice Solution 2: Solution 2: using 746 (a static clear) We must count to 9 before clearing it. 4

15 Practice Solution 3: Design a system the output of which is a clock pulse for every ninth input clock pulse. Solution 3: use counter 7463 (clocked clear), change states: 8, 9,,, 2, 3, 4, 5,, 8 5

16 Practice Solution 4: Design a system the output of which is a clock pulse for every ninth input clock pulse. Solution 4: use counter 7463, change states: 7, 8, 9,,, 2, 3, 4, 5, 7 6

17 Shift Registers A Shift register is a set of flip flops such that the data moves once place to the right/left on each clock or shift input. The flip flops can be SR, JK, or D. 7

18 Shift Input of Shift Register Input shift to right 8

19 Shift Register: Adding NOT Gates for Loadreducing Purpose of adding the NOT gate:. Reducing loads of the circuit from 4 to. 2. Changing the trigger edge from Trailing-edge to leading-edge. Loads is not calculated based on the number of flip flops. It is based on the electric current (amperes). For example, loads of a truck are measured by weight, not the number of objects. 9

20 Adding NOT Gates for Load-reducing Purpose of adding NOT gates:. Reducing loads of the circuit. 2. Changing the trigger edge type. 2

21 Serial-in, Serial-out shift register Only bit is loaded into the register at a time. Load =, input (S) = qn, Load =, input (S) = x. 2

22 Shift Register with Clear Input, Serial in, and Parallel Outputs 8-bit 7462 Shift Register with: Clear Active low. D flip flops 2. Clear input to initialize the output of each bit to. 3. Parallel outputs to get the contents of each flip flop. 22

23 Parallel-in Serial-out Shift Register A parallel-in shift register allows the register to be loaded in one step! Need: a) an input line for each flip flop; 2) a control line for load. 23

24 Parallel-in Serial-out Shift Register Load = high (don t load) Enable = low (enable shift) Then, we have: PRE = high CLR = high Shift works. Load = low (load) Then, we have: PRE = IN2 CLR = IN2 IN2 is loaded into the flip flop. Enable = high (clock is disabled, nothing changes) clo 24

25 Parallel-in Serial-out Shift Register Load = high (don t load) Enable = low (enable shift) Then, we have: q is shifted into q2. Shift works. Load = low (load) Enable = low (enable shift) Then, we have: IN2 is loaded into q2. Enable = high (clock is disabled, nothing changes) 25

26 Right/Left Shift Registers Don t load, don t shift Hold Clock signal is disabled. 26

27 Right/Left Shift Registers Don t load, don t shift Shift left S = q3 R = q3 27

28 Right/Left Shift Registers Don t load, don t shift Shift right S = q R = q q 28

29 Right/Left Shift Registers Don t load, don t shift Load S = IN2 R = IN2 IN2 IN2 29

30 Practice: design system using shift register Using the following an 8-bit serial-in, parallel-out shift register to design a system with one output, z, which is if the input, x, has been alternating for seven clock times (including the present). 3

31 Practice: design system using shift register Using the following an 8-bit serial-in, parallel-out shift register to design a system with one output, z, which is if the input, x, has been alternating for seven clock times (including the present). X A B C D E F z X A B C D E F z Case Case 2 3

32 Practice: 32

33 Announcement HW8 is due on /29 Review Chapter 8., 8.4. Next class: Review for Final Exam Final Exam: Time: Wed. (2/2/7) :pm 3:5pm Location: SH 378 Can bring 2-A4-Pages of notes 33

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