The book has excellent descrip/ons of this topic. Please read the book before watching this lecture. The reading assignment is on the website.

Transcription

1 5//22 Digital Logic Design Introduc/on to Computer Architecture David Black- Schaffer Contents 2 Combina3onal logic Gates Logic Truth tables Truth tables Gates (Karnaugh maps) Common components: Mul/plexors, encoders, decoders Sequen3al Elements Building a counter Memories and latches Material that is not in this lecture 3 Readings from the book Finite State Machines (C.) The book has excellent descrip/ons of this topic. Please read the book before watching this lecture. The reading assignment is on the website. (Don t forget: the assigned reading may include details or bits and pieces that I don t cover in the lecture. You re responsible for that as well on the exam.)

2 5//22 Logic gates 4 Basic Opera3ons NOT!A AND A B OR AB NOR!(AB) = NOT (A OR B) NAND!(A B) = NOT (A AND B) XOR A^B = (A!B)(!A B) XNOR!(A^B) = NOT (A XOR B) Logic gate truth tables 5 Truth tables define the behavior of the gate (it s output) for all possible input combina3ons. AND OR XOR NAND NOR XNOR Logic equa3ons and their gate equivalents 6 A = A = A A = A A = A OR A OR A AND A AND 2

3 5//22 Laws of Boolean algebra 7 Iden/ty: A = A A = Zero and One: A = A = Inverse: A!A= A!A= Commuta/ve: AB = BA A B = B A Associa/ve: A(BC) = (AB)C A (B C)=(A B) C Distribu/ve: A (BC) = (A B)(A C) A(B C) = (AB) (AC) See C.2 in the book. De Morgan s Law:!(A B) =!A!B 8!(A B) =!A!B Prove it: A B A B!(A B)!A!B!A!B AND OR De Morgan s Law:!(A B) =!A!B 9!(A B) =!A!B Prove it: A B A B!(A B)!A!B!A!B AND OR 3

4 5//22 Logic gates summary Learn the basic logic gates: NOT, AND, OR, NOR, NAND, XOR, XNOR Each gate is defined by its Truth Table: Defines the output for all combina/ons of inputs De Morgan s law:!(a B) =!A!B 8 4

5 5//22 9 Equa3ons from truth tables Going the other way 2 We just did equa/ons truth tables, but how about truth tables equa/ons? Why would we want to do this? So we can build logic from func/onal defini/ons. Does this func/on look familiar? A B S Sum C Carry This truth table defines the behavior of an adder. Example: Building a half- adder: Sum output 2 What is a half- adder? An adder with no carry in (AB = {Sum, Carry OUT }) Why? Simpler than a full adder. Building it: Start with S What logic func/on is this? (inputs are A and B) Find all the places where S is, then look at the inputs S = A XOR B This paiern is XOR. B S A C XOR 5

6 5//22 Example: Building a half- adder: Carry output 22 Now look at C What logic func/on is this? (inputs are A and B) Find all the places where C is, then look at the inputs C = A AND B Makes sense: we only have a carry out if we are adding (A= AND B=) This paiern is AND. A B S C AND Example: Complete half adder 23 Two gates: S = A XOR B C = A AND B A B S C 24 6

7 5//22 Karnaugh Maps 27 What we just did was ad hoc: We looked at the truth table and guessed the gate How do we do this more systema3cally so we can always find the right gates? In par/cular: find the fewest gates Karnaugh Maps A special way of wri/ng truth tables so we can easily iden/fy logic gates (But really this is all done by computers these days.) Introduc3on to Karnaugh maps 28. Write the inputs across the top and side 2. Circle the largest power- of- 2 blocks of s 3. Write down the equa/on Sum A \B S = A XOR B A Carry B A \B C = A AND B Karnaugh map example 29. Write the inputs across the top and side 2. Circle the largest power- of- 2 blocks of s 3. Write down the equa/on!b B!A A A\ B f = A!B 7

8 5//22 Example: blocks of size 3 By selec3ng small blocks we get many terms, which means results in a complex equa3on.!a A!B B A\ B B!A B A!B A f = (A!B) (A B) (!A B) = (A (B!B))!A B = A!A B = AB Example: blocks of size 2 3 By selec3ng larger blocks we get fewer terms, and a simpler equa3on.!b B A \B!A B A A f = AB Example: selec3ng s instead of s 32 We can select zeros, but then we get the inverse of the desired func3on. (e.g.,!f instead of f)!b B!B!A A\ B!A A!f =!A!B f =!(!A!B) = AB 8

9 5//22 In general: circle the largest blocks 33 Select the largest power- of- two blocks to get the simplest equa3ons.!b B We could also select s, but then we get!f!f =!A!B f =!(!A!B) = AB f = AB!A A If we are more clever, we can select two blocks of 2 s A\ B Largest block of s is size 3, so use 3 size blocks f = (A!B) (A B) (!A B) = (A (B!B))!A B = A!A B = AB 34 More than two variables 37 Order variables such that only changes in each row/column (Grey coding)!c!d!c D C D C!D CD \AB B D!A B!C B B (D!A!C) Overlapping boxes just mean both terms generate a 9

10 5//22 Karnaugh map summary 38 Allows you to truth table gates Important because we describe func/ons in terms of their truth tables Remember to circle the largest groups (power- of- two) Groups may overlap Inputs should only change one bit at a 3me (e.g.,,,,, not,,,) If you have outputs you don t care about (x s) you can circle them too However, computer do this beier than humans All modern tools (including LogicSim) will convert truth tables to logic gates for you Important logic blocks

11 5//22 MUXes and DEMUXes 43 Mul3plexers (MUXes) Choose from mul/ple inputs Essen/al for rou/ng signals Demul3plexers (DEMUXes) Opposite of MUXes Busses (mul/- bit signals) Same symbol for busses E.g., in can be an 8- bit value (8 wires) and each out will also be 8- bit values (8 wires) Encoders and decoders 44 Decoders Convert from binary encoding to - hot Binary == in - hot Encoders Convert form - hot to binary - hot = binary Q: Why is D not connected? - hot =? In binary Images from hip:// tutorials.ws Memories 45 Memories are 2D arrays of cells Each cell stores bit We enable a whole row to read out a chunk (open a word) of data We can only access row at a /me, so the row enables are - hot - hot row enables Array of SRAM Cells (Each box stores bit) 6 bits of data output from memory array

12 5//22 How to build a memory array 46 But we want to use a binary address to access our memory And we want output in bytes! 4- bit binary address bus Binary bits - 2 Bit 3 Decoder - hot row enables Array of SRAM Cells (Each box stores bit) Address bits - 2 select one of 8 rows Address bit 3 selects which half of the output 8- bit data bus MUX 8- bit data output Reading a memory array 47 binary = 4- bit - hot binary address bus Binary bits - 2 Read Address 2 = Bit Bit 3 = Decoder - hot row enables Array of SRAM Cells (Each box stores bit) 8- bit data bus MUX Decoder uses part of the address to select the row. 8- bit data MUX uses part of output the address to select the columns Real SRAM arrays Write drivers charge the wires to or to overwrite the contents of the SRAM cell when the row is ac/vated. Pre- charge drivers charge the wires to.5 so the weak SRAM cells 7 only need to pull up or 6 down a liile. 5 Decoder Pre- charge/write drivers 48 Sense amplifiers Tiny SRAM transistors are weak: need an amplifier to determine if the output is or. MUX 2

13 5//22 SRAM from ARM 49 Pre- charge and write drivers Decoder SRAM Array Sense amplifiers Summary: important building blocks 5 MUXes select an input from many The input may be a bus (mul/ple bits) DEMUXes do the opposite: output to one output DECODERS take a binary valued input and ac/vate one output (- hot) E.g., binary in will ac/vate - hot output #2 ENCODERS take a - hot input and output its binary value E.g., - hot input #3 in will output binary ADDERS take in A and B and output the sum Half- adder: AB = {Sum, Carry OUT } Full- adder: ABCarry IN = {Sum, Carry OUT } We saw how you use a MUX and a DECODER in a memory array 5 3

14 5//22 54 State elements: memories What is state? 55 State is recorded informa/on It can change, but it does so explicitly Memories store state Output changes only when the data is explicitly updated Combina3onal logic is sate- less Output changes instantly when the input changes Think about truth tables: output changes as soon as the input changes You need both to make anything useful Example: building a counter 56 How can we build a counter? Counts,, 2, 3, 4, Increments on every clock signal (explicit state change) Need to do three things: Calculate the next value (e.g.,, 2, etc.) Store the current value Update it to the next value These are: Combina3onal: next_value = current_value Sequen3al (state): No clock: current_value = current_value On clock: current_value = next_value This way the counter only counts on the clock signal 4

15 5//22 Combina3onal logic for coun3ng 57 How do we count?, 2, 2 3 Answer: an adder! We want: next_value = current_value How do we build an adder? SUM = A XOR B CARRY = A AND B That s great for bit, but how about 3? A2 B2 A B SUM2 SUM Input: 3 bits of A (A, A, A2) Input: 3 bits of B (B, B, B2) Output: 4 bits (SUM, SUM, SUM2, ) A B SUM Hooking up a mul3- bit adder (ripple carry add) 58 Need to hook up our adder so the carries propagate Carry out from bit Carry in on bit Need a full adder! { A B} {SUM, } Connect the carries in a chain to produce a mul3- bit adder. Input to first = A2 B2 A B A B SUM2 SUM SUM Tes3ng the adder 59 Try adding: 2 3 = 5 A = 2 = B = 3 = Output 5 = Expect a carry to the 3 rd bit A2 B2 A B A B SUM2 SUM SUM S = = = S = = = S = = = 5

16 5//22 6 Using the adder to build a counter 6 Want next_value = current_value All 3 bit values Wire it up! Connect the carries B = () A = current_value SUM = next value current_value Problem! We have feedback directly from next_value to current_value. (They are the same wire!) A2 B2 A B A B SUM2 SUM SUM next_value Adding state to break the feedback loop 62 next_value = current_value Need to keep the current_value separate from the next_value Latches only move input to output on the clock signal: state element Now we only update current_value to new_value when the clock signal occurs. Latch separates current_value and next_value, upda/ng current_value only on the clock signal A2 B2 A B A B current_value SUM2 next_value SUM SUM in in in Latch Latch Latch Clock out out out 6

17 5//22 What happens on the clock signal? 63 Time 2 CLK c c c2 n n n2 Latch updates when the clock goes from. On clock the latch input is stored and the output is updated with the new input Adder updates current_value as soon as its A2 inputs change B2 A B A B SUM2 next_value SUM SUM in in in Latch Latch Latch Clock out out out Speed of the clock signal Time Clock current_value next_value Q: What limits the speed of the clock? 64 When the clock edge rises ( ) The next_value is stored as the current value The new current_value then goes through the adder to make a new next_value Everything takes some /me A 2 B2 A B A B current_value SUM2 SUM SUM next_value in in in Latch Latch Latch out out out Clock Big picture: sequen3al logic What did we do? We used a state element to store the current state We used combina/onal logic to calculate the next state from the current state We made a feedback loop such that: On every clock signal The current state next state Need inputs and outputs to interact with anything Clock speed determined by how Inputs quickly next state logic can update. 65 Next State Logic Next State (From Truth Table) Current State (Memory) Outputs Clock Current State 7

18 5//22 Summary: state elements 66 State elements (memories) store state Only update at specified /mes (e.g., clock ) Use combina3onal logic (gates) to calculate the next value Use state elements (memories) to store the current value Update current value = next value on the clock Building memories: SRAM and DRAM 8

19 5//22 SRAM: sta3c random access memory 7 Sta3c Random Access Memory (SRAM) Sta/c: it keeps the value by itself (needs power to do it) Inside an SRAM cell Two inverters in a feedback loop Holds the value (as long as the power is turned on) How do we write into the memory? What is the difference between the input and the output? Output is Pass Gates: When turned on they allow the new value to write in. Output Output is is Using clocks to make latches: transparent latch 7 When clock is high () the input goes straight through to the output When clock is low () the last value is latched or held and the input is ignored In Out In (ignored) Out (stays the same) Clock Problem: The output changes with the input when the clock is high. Glitches in combina/onal logic can cause bad things. In Clock = (open) Clock = (closed) Out (changes with input) Edge- triggered (D) FlipFlop Only update the output on of the clock Master- Slave latch: two latches together Input change does not change output In In!Clock 72 Out Clock Clock = Clock = Output changes on clock! Input change does not change output Data moves to first latch when clock is. (Just like a transparent latch.) Clock = Clock = Data moves to second latch when clock is. (So output does not change with input.) 9

20 5//22 Edge- triggered (D) FlipFlop 73 Clock = Value latched into first latch Clock = First latch transferred to second latch and output But input ignored In!Clock = Clock = Out In Out!Clock = Clock = 74 DRAM: dynamic random access memory 75 Dynamic Random Access Memory Uses a capacitor to store charge Charge dissipates over /me Must periodically refresh the data (hence the dynamic part) Reading data uses up charge (must re- write aper reading) But, 6- x smaller than SRAM = infinitely cheaper Access transistor Enable enables read/write. Input/Output GND Capacitor holds the charge: =, = 2

21 5//22 DRAM: dynamic random access memory 76 Capacitor is a deep well. (center to walls form capaci/ve area.) Enable Access transistor enables read/write. Input/Output GND Images from Universitat Politecnica de Catalunya and IHP Microelectronics Capacitor holds the charge: =, = Memory speeds 77 Why are DRAMs slow and SRAMs fast? It s all about the /me it takes to get the output SRAMs have a powered inverter driving the output DRAMs have only the charge on the capacitor driving the output Also explains why DRAMs are cheap (small) and SRAMs are expensive (large) SRAM has a (small) powered inverter to change the value on the wire Output Output Output DRAM has only the 3ny charge on its capacitor to change the value on the wire VERY SLOW small capacitor charging a big wire Memories summary 78 SRAM (sta/c) keeps the value with an ac/ve feedback loop Big (6 transistors) Fast (powered inverters to output value) DRAM (dynamic) keeps the value as charge on a capacitor Small ( capacitor transistor) Slow (only charge in capacitor to output value) Latches can be built from SRAM cells Transparent: let the input pass through Master- Slave (D FlipFlop): only update the output on the rising clock edge 2

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