Exam #2 EE 209: Fall 2017

Transcription

1 29 November 2017 Exam #2 EE 209: Fall 2017 Name: USCid: Session: Time: MW 10:30 11:50 / TH 11:00 12:20 (circle one) 1 hour 50 minutes Possible Score TOTAL 110 PERFECT 100 No calculators are allowed. No outside notes. Show all work to get full credit. Do not guess. You may attach scratch paper as needed but you must make your final answer clear to the grader. Before you start: clearly write your name at the top of each sheet. Graders may separate pages during grading. 1

2 1. [3 points] Complete the following table showing the current voltage relations for each MOS transistor operating mode. Mode Condition(s) vs. Relationship Off Resistive (linear) Saturation a. [8 points] Draw a CMOS circuit (pull up and pull down) for the logic function. Annotate your diagram with transistor widths such that your CMOS circuit is three times as strong as a reference inverter with NMOS / 1 and PMOS / 2. 2

3 b. [4 points] Describe why the following single transistor circuit behaves like an inverter. Be concise but specific. Describe specifically how this circuit produces the usual inverter input output voltage relation (i.e. consider high and low input values). [hint: If is high then because, etc.] 3

4 c. [12 points] Using the single transistor circuit in (b) write an equation if 1. Do not solve the equation. Repeat for 4. Assume 5 and 0.5. [hint: determine the voltage drop across the resistor given. Then use the input output relationship from (b) to infer the operating mode for the transistor. Use Ohms law and the vs equation.] 4

5 2. Consider the following (complete) state diagram for the time keyed encryption circuit shown on the next page. The circuit loads a user defined 8 bit _ during the INIT state. Upon START the circuit transmits a sequence of 16 bytes read and encrypted sequentially from a 16x8 bit ROM. The ROM requires one full clock cycle to read. The circuit sends the XOR encrypted byte to a receiver and sets _ 1. The circuit waits for a reply from the receiver ( 1). If the receiver reports an error ( 1) the circuit retransmits the byte with the same encryption key. After successfully transmitting each byte the circuit increments by 1. After the circuit transmits the entire 16 bit sequence (_ 1) it goes to the DONE state. It waits there for acknowledgement ( 1). Use a 4 bit counter (3: 0) to store the ROM address. START LAST_BYTE RCVD ERR RCVD RESET START INIT READ SEND WAIT ERR RCVD ACK DONE LAST_BYTE RCVD ERR ACK a. [8 points] Complete the next state logic (NSL) and output function logic (OFL) for the state machine using 1 hot design. _ 5

6 b. [2 points] Is this a Mealy or Moore state machine? Justify your answer. c. [10 points] Complete the datapath for the encrypting circuit using the components below. 6

7 d. [8 points] Determine if the following state transitions satisfy mutual exclusivity and all inclusivity. Indicate your answer by circling YES or NO for each case. Mutually exclusive: YES / NO All inclusive: YES / NO Mutually exclusive: YES / NO All inclusive: YES / NO Mutually exclusive: YES / NO All inclusive: YES / NO Mutually exclusive: YES / NO All inclusive: YES / NO 7

8 3. For each of the following statements circle the correct answer. [1 point] You can always assume that the current into a CMOS load is equal to 0. [True / False]. [1 point] The time constant gives a relative measure of the time required to charge or discharge an RC circuit. [True / False]. [1 point] EDO, Fast page, SDRAM, and DDR SDRAM are memory technologies that improve memory throughput. [True / False]. [1 point] Static RAM requires complex circuitry to refresh its state after a read cycle. [True / False]. [1 point] The 4 bit counter output and it is active any time the counter reaches terminal count (i.e. whenever 3: ). [True / False]. [2 points] Karnaugh maps always yield the minimal 2 level product of sum (PoS) and sum of product (SoP) representation for any Boolean logic function. [True / False]. b. Circle the correct answer to make the following statements true. [1 point] A p n junction (a.k.a. diode) in a reverse bias configuration has a [wider / narrower] depletion region than the same device configured in a forward bias configuration. [2 points] Pipelining is a technique to [increase / decrease] the [throughput / latency] in a circuit by [increasing / decreasing] hardware utilization. [2 points] Boron has 3 valence electrons and phosphorous has 5 valence electrons. Boron is an electron [accepter / donor] in semiconductor devices. Phosphorous is an electron [acceptor / donor]. c. Answer the following questions. [3 points] Briefly (about 20 words or less) describe how to check for signed overflow. [2 points] Write logic expressions for the outputs from a 1 bit full adder () with carry in. 8

9 4. [13 points] Complete the following datapath to produce a single bit output from two sequences and. A control unit (CU) inputs two new 4 bit numbers 3: 0 and 3: 0 at each positive clock edge. The CU uses the signal / to specify which type of check to perform: when / 1 output 1 only if the sequences and are equal: when / 0 output 1 only if the sequences A and B are not equal ( different ). Use a D latch to remember. Your design should always reset 0 at the start of each sequence. The CU sets 1 for one clock along with the first numbers in the sequence. The CU sets 1 (end of sequence) with the last numbers in the sequence. Ignore inputs and until before 1 and also after 1.. T should not change. Use an SR bistable as a flag to monitor or ignore the inputs and. Use inverters as needed. Use exactly one logic gate to generate A_EQ_B but no additional gates. A[3] Cin B[3:0] A[0] A + B A_EQ_B B[3] B[0] Cout CLK START 2x1 multiplexer I0 Y I1 S D EN D latch /CLR Q T EOS EQUAL/DIFF S SR bistable Q SEQ_ACTIVE R b. [3 points] Can you replace the D latch in the design above with a D bistable element? Explain. [hint: what is a D bistable element?]. 9

10 5. [10 points] Implement the following arithmetic function using combinational logic. Assume X[3:0] and Y[3:0] are 4 bit unsigned numbers. Ignore overflow and disregard truncation (i.e. ignore carry bits beyond 4 bits) ,. 2 Use only the components provided below and inverters. 1 bit left shift 1 bit left shift Y[3:0] Y[3:0] 4 bit comparator A < B 1 bit left shift Y[3:0] B[3:0] A = B A > B A[3] Cin A[3] Cin A[0] A + B A[0] A + B B[3] B[3] B[0] Cout B[0] Cout 4 bit 2x1 multiplexer Y[3:0] B[3:0] S A[3] A[0] B[3] B[0] Cin Cout A + B 10

11 b. [12 points] Synthesize the Boolean logic function 0,1,2,3,7 for each of the following sets of components. You may use inverters as necessary but no other gates. One 2x4 decoder and 1 OR gate. 2x4 decoder A1 A0 Y0 Y1 Y2 Y3 One 4x1 mux 4x1 multiplexer I0 I1 I2 I3 Y S1 S0 Two 2x1 muxes. 2x1 multiplexer I0 I2 Y S 2x1 multiplexer I0 I2 Y S 11