Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1

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1 Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar ECE495K Lecture Notes: Chapter 3

2 How does a light switch work? I thought that this class was about computers 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 2

3 The light switch: off switch 2 VAC Switch in off position means circuit is open, so electrons can t flow. The bulb stays dim. 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 3

4 The light switch: on switch 2 VAC Switch in on position means circuit is closed, so electrons do flow and light the bulb. 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 4

5 Switches implement bits Switch in on or off position leads to circuit opened or closed, which in turn leads to light on/off Recall that on and off correspond to bits What we want: a switch that is turned on and off by electricity instead of mechanical means 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 5

6 Introducing the transistor 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 6

7 Properties of silicon Silicon is a semiconductor conducts electricity only under certain circumstances Silicon lattice can be doped with other atoms Group V (e.g., phosphorus) gives free electrons (n-type) Group III (e.g., boron) gives free electron holes (p-type) Both enable conduction More detail in later courses (ECE 255, 35) 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 7

8 Transistor basics N-type (sourc e) gate oxide P-type (substrate) N-type (drain) Above is an NMOS (N-channel metal-oxide semiconductor) Field Effect Transistor (FET) Applying positive voltage to gate (with respect to substrate) causes electrons and holes to migrate and forms an N-type channel below oxide, allowing current to flow from drain to source NMOS on 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 8

9 Types of transistors N-channel MOSFET (NMOS) previous slide P-channel MOSFET (PMOS) opposite of NMOS P-type source and drain with N-type substrate Current flows between source and drain when negative voltage at gate (with respect to substrate) (P channel forms below oxide) PMOS on Transistors are electrically-controlled switches! When current flows, source and drain have same voltage Otherwise, source and drain electrically disconnected NO relationship betweens source and drain voltages 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 9

10 Conventions Ground (GND): zero voltage applied to N substrate (in PMOS) Represents voltage of the earth, the ultimate acceptor of electrons Usually logic (exceptions later) V dd : positive voltage applied to P substrate (in NMOS) Has consistently dropped over the years as transistors have gotten smaller 2V, 5V, 3.3V, 2.9V, 2.5V, 2.2V,.8V,.5V,.3V, Usually logic (exceptions later) 29 Vijaykumar ECE495K Lecture Notes: Chapter 3

11 Transistor diagrams NMOS PMOS Treat them as switches between source and drain which turn on when appropriate voltage applied to gate (high voltage for NMOS, low voltage for PMOS) 29 Vijaykumar ECE495K Lecture Notes: Chapter 3

12 Complementary metal oxide semiconductor Neat property of NMOS and PMOS High voltage turns on NMOS, but turns off PMOS Low voltage turns on PMOS, but turns off NMOS PMOS conducts well and not well NMOS conducts well and not well Circuits use both PMOS and NMOS PMOS for cases where output is and NMOS for Complementary behavior leads to CMOS There are others types of logic CMOS is the dominant type of logic in industry today 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 2

13 Using the CMOS property Vdd High input: turns on NMOS, turns off PMOS Output is then connected to??? Vin Vout Low input: turns on PMOS, turns off NMOS Output is then connected to??? What logic operation is this? Complementary behavior: PMOS provides high output (NMOS off) NMOS provides low output (PMOS off) GND 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 3

14 x y NAND in CMOS x NAND y (step ) Use PMOS to output and NMOS to output (step 2) NAND outputs if either input is => PMOS in parallel NAND outputs if both inputs are => NMOS in series 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 4

15 Claim: This implements a NAND (NOT of AND) A B Vdd Vdd Vout Low A: turns on??? Output is then connected to??? Low B: turns on??? Output is then connected to??? High A and B turn on??? Output is then connected to??? Complementary behavior: PMOS output high (NMOS off) NMOS output low (PMOS off) GND 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 5

16 Claim: This implements a AND (invert NAND) Vdd Vdd Vdd A Vout Vin Vout GND B NAND followed by NOT In CMOS, NAND is easier than AND Similarly NOR is easier than OR GND 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 6

17 Must be careful with CMOS A Vdd Vout Output (or any other point in the circuit) can never be simultaneously connected to both Vdd and GND Otherwise, you have a short circuit (huge current until something catches fire & blows up) E.g., if A low and B high to the left Not a problem usually (why?) B GND Sometimes ok to have output disconnected from both Vdd and GND Called tri-state or high-z More in later classes Vijaykumar ECE495K Lecture Notes: Chapter 3 7

18 Exercises How to implement a NOR? How to implement an AND? How to implement a 3-input NAND? Recall from Chapter 2 we said that and are easily available in real designs where are they? Read pages Vijaykumar ECE495K Lecture Notes: Chapter 3 8

19 Techniques for Logic Design 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 9

20 Designing Logic Ultimately, all logic and computation performed with transistors IBM s CELL processor in PS3 has 2 million+ of them Lots of wires too to connect up all those transistors We need some slightly more abstract notation for design Otherwise, we are likely to get lost in sea of transistors Draw diagrams at level of logic functions instead of individual transistors 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 2

21 Logic Diagrams A digital logic primitive is called a gate Not to be confused with gate of transistor AND OR NOT NAND NOR XOR XNOR 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 2

22 What does the bubble mean? AND NAND Bubble means inversion active low or negative logic True is low voltage, False is high voltage (instead of usual) A NAND is shown as an AND with an active low output Bubbles can also be applied to inputs 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 22

23 What does this gate do? OR with both inputs active low So, output is high voltage only if either input is low Which gate has the same behavior? 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 23

24 DeMorgan s Law = = Can be used for logic simplification Connecting a bubble input to a bubble output is equivalent to connecting a regular input to a regular output 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 24

25 Using CMOS gates to implement logic Recall from Chapter 2 OR, AND, & NOT logically complete They are enough to implement any truth table(logic expression) All logic expressions can be expressed as sum-of-products OR of multiple ANDed terms, which may include NOTs E.g, x y f 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 25

26 Using CMOS gates to implement logic How can we express any truth table as sum of products? Step : Pick rows with output Step 2: For each such row, make a term by ANDing inputs together using input if value is and input if value is Step 3 OR the terms for the rows to get the whole logic function In our eg, x y for row 2, xy for row 3 Thus, f = x y + xy sum of products using only AND, OR, NOT We can do this for any function with any number of inputs 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 26

27 Using CMOS gates to implement logic Sum of products is AND, OR, NOT but CMOS can easily implement NOT, NAND, NOR OR, AND are harder (AND = NOT of NAND and OR = NOT of NOR) Question: So how to implement sum of products? 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 27

28 Using CMOS gates to implement logic Answer: Convert AND, OR to NAND why is that always possible? e.g., f = xy + x y X Y Step : Draw out logic for specified function 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 28

29 Using CMOS gates to implement logic e.g., f = xy + x y X Y Step 2: Apply DeMorgan s Law to convert ANDs and ORs 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 29

30 Using CMOS gates to implement logic e.g., f = xy + x y X Y Step 3: Eliminate bubbles between OR outputs and AND inputs 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 3

31 Using CMOS gates to implement logic e.g., f = xy + x y X Y Step 4: Apply DeMorgan s on low-input ORs to form NANDs Result CMOS-friendly circuit using only NAND 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 3

32 Using CMOS gates to implement logic Like the previous transformation, there are ways to transform and optimize circuits E.g., minimize the number of logic gates Such optimizations are covered in later classes (ECE 27) 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 32

33 General Method to get any logic functionality Write out the truth table Specifies what functionality you want Derive sum of products Specifies functionality in logic expression Draw logic circuit with NOT OR and AND Follow previous method using DeMorgan s Law to convert the logic circuit to CMOS-friendly circuit using NAND only Read pages Vijaykumar ECE495K Lecture Notes: Chapter 3 33

34 More Gate Diagrams 3-input AND: output is true only if all three inputs are true (xyz) 4-input NAND: output is false only if all four inputs are true (xyzw) Gates can have an arbitrary number of inputs ( fan-in ) Each output can also connect to an arbitrary number of other gates ( fan-out ) (In reality, both of the above impact design and performance) 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 34

35 Useful logic circuits 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 35

36 Useful Circuit blocks Generic building blocks useful in all kinds of digital circuits Processors have thousands of these Eg : decoder: Given a n-bit value, identifies the corresponding item among 2 n things Eg 2: Multiplexor: Chooses one of many inputs 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 36

37 Decoder Has n inputs (selector) and 2 n outputs Exactly one output is for every possible input pattern A B if A=, B= if A=, B= if A=, B= if A=, B= S2 S S 3-bit decoder D7 D6 D5 D4 D3 D2 D D 2-bit decoder convenient notation 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 37

38 Multiplexer (MUX) Uses n-bit selector to choose one among 2 n inputs S S A B A if S=, S=; otherwise B if S=, S=; otherwise C C if S=, S=; otherwise D if S=, S=; otherwise D Called a 4-to- mux ; can generate any 2-input function 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 38

39 Multiplexer (MUX) cont d Uses n-bit selector to choose one among 2 n inputs IN7 IN6 IN5 S2 S S Convenient shorthand notation IN4 IN3 IN2 IN 8- mux OUT Exercise: Implement a mux using a decoder, AND gates, and OR gates IN 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 39

40 Let s build an adder now Arithmetic is just a type of logic! 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 4

41 -bit Addition Using Digital Logic ( of 3) What are the inputs? X Y Cin Sum Cout Input X Input Y Carry in What are the outputs? Sum Carry out Form a truth table 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 4

42 -bit Addition Using Digital Logic (2 of 3) Make sum-of-products X Y Cin Sum Cout Add one term for each input combo that causes output to be Sum = x y c in + x yc in + xy c in + xyc in C out = x yc in + xy c in + xyc in + xyc in 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 42

43 -bit Addition Using Digital Logic (3 of 3) Sum = x y c in + x yc in + xy c in + xyc in C out = x yc in + xy c in + xyc in + xyc in Cin Y X X Y Co Full Adder Ci Sum Sum Cout Shorthand notation 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 43

44 Multi-bit addition Propagate carries just like doing arithmetic by hand (In reality, more complex and faster schemes exist ) X3 Y3 X2 Y2 X Y X Y X Y X Y X Y X Y Co Full Adder Ci Co Full Adder Ci Co Full Adder Ci Co Full Adder Ci Sum Sum Sum Sum S3 S2 S S Popularly called ripple-carry adder 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 44

45 But how to store information? Everything so far just operates on inputs 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 45

46 Types of Logic Combinational Logic All outputs depend only on current inputs Makes various decisions, but forgets decision as soon as inputs change Type of circuits we ve been seeing so far Sequential Logic Outputs may depend on past inputs as well Remember/encode past inputs/decisions as state Use current input and current state for next decision These systems store state information used to guide the decision-making process 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 46

47 Example: TV tuning Old-style TV used knobs to set channel, volume Akin to combinational logic current inputs guide behavior Modern TVs use channel/volume +/- keys on remote control Sequential logic use inputs along with stored state (current channel or volume) to decide behavior 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 47

48 Forming storage from gates (to remember state) Gates forget if old inputs go away, so keep reminding them Do this through a feedback loop Feed current outputs back into inputs Remembers old output even if input is gone S Q Q = Q + S R Q Q = Q + R Called the S/R latch (set/reset) bar above name indicates active low signal 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 48

49 S Understanding the S/R latch Q Q = Q + S R Q Q = Q + R If only Sbar input low, then Q goes to, then Qbar goes to. S input is used for setting the latch to If only Rbar input low, then Qbar goes to, then Q goes to. R input is used for resetting or clearing the latch to 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 49

50 S Understanding the S/R latch Q Q = Q + S R Q Q = Q + R If only Sbar input low, then Q goes to, then Qbar goes to. If only Rbar input low, then Qbar goes to, then Q goes to. If both inputs high, outputs held (Q/Qbar are opposites) Remembers past state after input is gone! Stores bit If both inputs low, both outputs go high, but Q/Qbar no longer opposite -- unstable. Once outputs go high, bad things happen! You should ensure both inputs are never low 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 5

51 D (Data) latch S/R latches or by using S or R input How to store a bit without knowing it is or? Answer: D latch Inputs are D (data) and WE (write enable) When WE is high, output goes to D (Sbar=D, Rbar=D) When WE is low, output is held Only one output: Q (Qbar is internal, not visible outside) D S Q D Q WE WE R Shorthand notation 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 5

52 Storing multiple bits: the register A register is a multiple-bit storage element Consists of a D latch per bit, with all WE inputs tied together Whole register is written as a single unit WE D3 D2 D D D WE D WE D WE D WE Q Q Q Q Q3 Q2 Q Q 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 52

53 Memory: Higher-level storage elements A memory is a set of storage that can be addressed Each memory location is k bits wide The address is an n bit number, for 2 n possible locations The total storage of (k? 2 n ) bits Operations: read a location, write a location Memory conceptually consists of: D latches (k? 2 n ) total Address decoder determine location being referenced Creates a word select output Write enable (AND with decoder output) and k input bits Logic for k output bits from proper location 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 53

54 Layout of 2 2? 3 memory Inputs Address bits A, A A<:> in figure Data inputs D i <2:> WE Outputs Data outputs D<2:> 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 54

55 Layout of 2 2? 3 memory Reading: WE off Output stored data at given address Writing: WE on Store input data at given address 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 55

56 Realities of memory (some details FYI only) Not really implemented the way we ve shown Each bit uses fewer transistors Less control logic for choosing outputs Data lines shared by inputs and outputs Includes same basic concepts, though Often use multiple chips to implement memory 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 56

57 Types of Memory Static Random Access Memory (SRAM) Fast and expensive Dynamic Random Access Memory (DRAM) Much denser (more storage), slower to access Electrically complex and forgets after a while Data must be refreshed periodically or else it gets lost Lots of other types: read-only memory (ROM), electricallyerasable programmable read-only memory (EEPROM), nonvolatile random-access memory (NVRAM), FLASH (write once, read many, erase in chunks), etc. Read pages 97-3 (chapter 4) 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 57

58 Introducing the state machine Doing useful things with state 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 58

59 Finite State Machines A circuit that goes from one state to another (which next state depends on inputs) and outputs something at every state (outputs depend on inputs) Example: Traffic light: Green state: light up green light;wait for some time; go to Yellow state: light up yellow light; wait for some time; go to Red state: light up red light, wait for some time; go to Green 3 states, at each state light up a specific light And the states go to a specific next state 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 59

60 Finite-State Machines (FSMs) input Combinational Logic Circuit output Storage Element Output is a function of the input and the current state The function is computed by the combinational logic circuit How would you design this circuit? The state is stored in the storage element The next state is also function of the input and the current state 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 6

61 Finite-State Machines (FSMs) Output is a function of the input and the current state The function is computed by the combinational logic circuit How would you go about designing this circuit? The state is stored in the storage element How would you build this element? The next state is also function of the input and the current state The function is computed by the combinational logic circuit How would you go about designing this circuit? In 495K we will not go into FSM design details that is in ECE27. But we will connect FSMs to computer design in the next chapter. Computers are a bunch of FSMs! 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 6

62 Notion of a clock How does state machine know when to change to next state? All state machines have a clock input Alternates between high and low at a fixed frequency (Hz) Typically controlled by some crystal (oscillator) Next state change occurs at clock edge (rising edge or falling edge) clock period (?) Frequency f=/? 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 62

63 Notion of a clock Some state machines need to change only slowly, so have clocks below Hz Pentium IV has a 2.8 Gigahertz clock (giga = 9 )! Stop FSM by stopping clock AND clock with control input (usually ) clock period (?) Frequency f=/? 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 63

64 Where are we going from here? Ch 4 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar ECE495K Lecture Notes: Chapter 3 64