Lecture 18. BUS and MEMORY
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1 Lecture 18 BUS and MEMORY Slides of Adam Postula used 12/8/2002 1
2 SIGNAL PROPAGATION FROM ONE SOURCE TO MANY SINKS A AND XOR Signal le - FANOUT = 3 AND AND B BUS LINE Signal Driver - Sgle Source Many Sks Signal Buffer - Sgle Sk 12/8/2002 2
3 SIGNAL PROPAGATION FROM ONE SOURCE TO MANY SINKS A AND XOR Signal le - FANOUT = 3 AND AND B BUS LINE Signal Driver - Sgle Source Many Sks Signal Buffer - Sgle Sk 12/8/2002 3
4 SIGNAL PROPAGATION FROM MANY SOURCES TO ONE SINK signal 1 signal N MUX Select signal common signal le 12/8/2002 4
5 SIGNAL PROPAGATION FROM MANY SOURCES TO ONE SINK signal 1 signal N MUX Select signal common signal le FROM MANY SOURCES TO MANY SINKS signal 1 signal N MUX common signal le DE MUX signal 1 signal N Select signal Select signal 12/8/2002 5
6 TriState Buffer Concept Switch model of a multiplexer signal 1 signal N select decoder signal le Mutually exclusive select signals Bary select signal 12/8/2002 6
7 TriState Buffer Concept Switch model of a multiplexer signal 1 signal N select decoder signal le Mutually exclusive select signals Bary select signal TRISTATE buffer signal drivers - a DISTRIBUTED MULTIPLEXER signal le sig 1 sel 1 sig 2 sel 2 sig N sel N Mutually exclusive select signals 12/8/2002 7
8 TriState Buffer SYMBOLS OE OE OE OE SWITCH MODEL OE - put enable OE 0 0 Z 0 1 Z Z = High Impedance put not connected to put 12/8/2002 8
9 TriState Buffer SYMBOLS OE OE OE OE SWITCH MODEL OE - put enable 12/8/2002 9
10 TriState Buffer SYMBOLS OE OE OE OE SWITCH MODEL OE - put enable CMOS IMPLEMTATION Vdd OE 12/8/
11 UNIDIRECTIONAL BUS LINE Propagation from many sources to many sks signal 1 signal N BUS le Mutually exclusive select signals signal 1 signal N 12/8/
12 UNIDIRECTIONAL BUS LINE Propagation from many sources to many sks signal 1 signal N BUS le Mutually exclusive select signals signal 1 signal N UNIDIRECTIONAL BUS LINE TriState Signal Drivers TriState Signal Buffers signal 1 signal 2 signal 1 signal 2 12/8/
13 BIDIRECTIONAL BUS LINE Mutually exclusive select signals OE 1 = 1 source 1 OE n = 0 sk n 12/8/
14 BIDIRECTIONAL BUS LINE OE 1 = 0 sk 1 Mutually exclusive select signals OE n = 1 source n 12/8/
15 WIRED LOGIC +5V +5V A B NAND AND F1 A B OR NOR F1 TRANSISTORS WORK AS INVERTERS OP COLLECTORS NEED PULL_UP RESISTORS 12/8/
16 WIRED LOGIC +5V +5V A B NAND AND F1 A B OR NOR F1 F1 AND F2 F1 AND F2 Y Z NAND AND F2 Y Z OR NOR F2 12/8/
17 WIRED LOGIC BUS +5V signal 1 select 1 NAND AND F1 sk F1 AND F2 sel1 sig1 F1 signal N select N NAND AND F2 F1 selected /8/
18 REGISTER FILE Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 word 0 12/8/
19 REGISTER FILE word 0 word 1 12/8/
20 REGISTER FILE Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 word 0 Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 word 1 12/8/
21 REGISTER FILE word select MUX MUX MUX MUX Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 word 0 Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 word 1 12/8/
22 REGISTER FILE word select MUX MUX MUX MUX Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 word 0 word select decoder word 1 Di0 Do0 Di1 Do1 Di2 Do2 Di3 Do3 12/8/
23 MEMORY ELEMTS word select D0!D0 STATIC MEMORY CELL THE BASIC ELEMT IS A STATIC LATCH THAT HOLDS THE STORED VALUE AS LONG THE POWER IS ON. 12/8/
24 MEMORY ELEMTS word select D0!D0 STATIC MEMORY CELL READ WRITE CIRCUITRY (conceptual view) + - Do0 Di0 Column select 12/8/
25 MEMORY ARRAY word select D0!D0 D1!D1 D2!D3 word select Do0 Di0 Column select Do1 Di1 Column select Do2 Di2 Column select 12/8/
26 RAM - Random Access Memory Each word the RAM memory can be read by givg its address and observg the data les after some time. Each word can be re-written by givg its address, presentg the new data and keepg it stable for some time. Addressg can be random ( there are no requirements for any sequence addresses ) - hence Random Access Memory. Storage matrix is usually very large and organized as a square matrix of word cells. 12/8/
27 What have we learnt? TriState buffers allow to connect many signal sources to the same signal le. Wired logic can provide the same functionality although is less popular. Flip-flops can be organized registers, registers register files. RAM - Random Access Memory allows to read/write data at a randomly chosen address. 12/8/
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