WEEK 4.1. ECE124 Digital Circuits and Systems Page 1

Transcription

1 WEEK 4.1 ECE124 Digital Circuits and Systems Page 1

2 Combina=onal circuits A combinatorial circuit is one that consists of logic gates with outputs that are determined en=rely by the present value of the inputs. Combinatorial circuits might be 2 level logic (SOP,POS) or mul= level. Black bo illustra=on (there is no storage elements inside the bo): i1 i2 i3? o1 o2 in om Two opera=ons we might want to perform: Analysis given what is in the bo, what func:on(s) does it perform? Design given func:ons to perform, what do we need in the bo? ECE124 Digital Circuits and Systems Page 2

3 Analysis (for combina=onal circuits) Determines the func=on performed by a circuit. Starts with a circuit, and the result of analysis are the logic func=ons. Steps (assuming we have inputs, outputs and gates iden=fied): Label intermediate logic gate outputs star:ng from the inputs with arbitrary signal names. Determine the Boolean func=ons for each gate output star:ng from the inputs. Con=nue, moving towards the outputs un=l we have epressions for the outputs in terms of the inputs. We introduce etra signals and work our way through the circuit from inputs to the outputs. ECE124 Digital Circuits and Systems Page 3

4 Analysis eample (1) Intermediate signals introduced as required (T1, T2, T3) a b c a b c a b a c b c T2 T1 T3 f1 f2 This bunch of logic equa=ons does the trick, but we can subs=tute out the temporary signals to get an input output rela=onship. ECE124 Digital Circuits and Systems Page 4

5 Analysis eample (2) The input output rela=onship (removing temporary signals): ECE124 Digital Circuits and Systems Page 5

6 Design (for combina=onal circuits) Opposite of analysis Given func=ons to be performed, implement a combinatorial circuit that performs the func=ons. Steps: From specifica=ons, determine number of inputs and outputs. Derive the func=ons, or truth tables, that define input output rela=onship. Derive simplified Boolean func=ons. Draw the circuit diagram and verify correctness. Note: We might end up with a 2 level circuit (SOP,POS) or possibly a mul= level circuit implementa=on. ECE124 Digital Circuits and Systems Page 6

7 Design eample (1) Consider the following 4 input (a,b,c,d), 4 output (w,,y,z) circuit specified via K Maps. ab cd ab cd z y ab cd ab cd w ECE124 Digital Circuits and Systems Page 7

8 Design eample (2) We could just implement the SOP for each function individually. Could also (maybe) try and see if some product terms can be shared. Could also try to factor/decompose functions to find shared equations ECE124 Digital Circuits and Systems Page 8

9 Design eample (3) Mul=level factored circuit requires 9 gates and 17 gate inputs (inverters connected directly at inputs are free). 2 level implementa=on requires 10 gates and 23 gate inputs. c d b a c+d cd (c+d)' b(c+d) z y w ECE124 Digital Circuits and Systems Page 9

10 Combinatorial circuits (arithme=c) Some combina=onal circuits are very common and it is worth looking at them in more detail. One par=cular class of very useful circuits are arithme:c circuits; i.e., those circuits used for performing opera=ons such as: addi:on, subtrac:on, mul:plica:on, etc. of binary numbers. ECE124 Digital Circuits and Systems Page 10

11 Binary half adder circuit Basic definition of addition is to take two bits, and add them, producing a sum and a carry out. The circuit that produces these two outputs is called a binary half-adder. ECE124 Digital Circuits and Systems Page 11

12 Binary half adder implementa=on We can draw different implementations of a binary half-adder (depends on availability of XOR gates):! y!y sum y sum y cout cout ECE124 Digital Circuits and Systems Page 12

13 Binary full adders Most commonly, we are interested in adding n bit numbers. Therefore, we need to be able to also handle a carry in signal. The circuit implemen=ng these two func=ons is known as a binary full adder. Sum: odd #1 s EXOR ECE124 Digital Circuits and Systems Page 13

14 Binary full adder implementa=on We can draw different implementations of binary full adders. y cin sum y sum y cin ycin cout cin cout Note that the 2-nd implementation uses 2 half-adders to implement the full-adder. ECE124 Digital Circuits and Systems Page 14

15 Ripple adders for n bit addi=on Can build n-bit adders to add A = (a n-1 a n-2 a 1 a 0 ) and B = (b n-1 b n-2 b 1 b 0 ) simply by linking 1-bit full adders together. FA FA FA FA We might want to think about the performance (delay) of this adder circuit ECE124 Digital Circuits and Systems Page 15

16 Ripple adder performance (1) Recall that we spoke about combinational logic gates having some delay (i.e., a change in an input does not cause the output to change immediately) Assume that a logic gate has delay of 1 unit. Assume that each of our full-adders is built from half-adders. We can therefore trace/identify the longest combinatorial path in the circuit. This is the path that determines the performance of the circuit; The delay of the longest path tells us the minimum amount of time that we need to wait for the output to be correct. y sum FA FA FA FA cout cin ECE124 Digital Circuits and Systems Page 16

17 Issue of Ripple Adder Carry propaga=on is the main issue in an N bit ripple adder A faster adder needs to address the serial propaga=on of the carry bit Lets re eamine the equa=on for full adders

18 Ripple adder performance (2) For the ripple adder, it is possible that a change in the LSB of A or B (i.e., a 0 or b 0 ) will cause a change in the carry out of the MSB (i.e., c n ) We can identify the longest path: Delay is f(,y) only; performed at the same time for all stages. y sum FA FA FA FA cout cin We can compute the longest path for an n-bit ripple adder as follows: For Stages FA 1 FA 2, For Stage FA 0 ECE124 Digital Circuits and Systems Page 18

19 4 bit Ripple Adder using Full Adder A3 B3 A2 B2 A1 B1 A0 B0 A B A B A B A B Carry Full Cout Adder Cin Full Cout Adder Cin Full Cout Adder Cin Full Cout Adder Cin S S S S S3 S2 S1 S0

20 Full Adder Propaga=on Delay A0 B0 Carry Cin S0 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR

21 Full Adder Propaga=on Delay A1 B1 A0 B0 Cin S1 2 nd Stage Critical Path = 2 gate delays = D AND +D OR (Since 1 st Critical path > D XOR ) S0 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR

22 Issue of 4 bit Ripple Adder A3 B3 A2 B2 A1 B1 A0 B0 Carry Cin S3 S2 S1 S0 Critical Path = D XOR +4*(D AND +D OR ) for 4-bit ripple adder (9 gate levels) For an N-bit ripple adder Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays

23 Carry look ahead adders Ripple adders can be very slow for large numbers of bits. If we can calculate the carry ins faster, then we can build a faster adder. Consider the i-th bit of the adder, and identify two signals, namely the propagate p i and generate g i : (i) y(i) p(i) s(i) c(i) g(i) c(i+1) Write the carry out c i+1 in terms of the p i and g i signals instead. ECE124 Digital Circuits and Systems Page 23

24 Carries wri`en as func=ons of the propagates and generates We can consider writing all the carry outs in terms of the p i and g i signals, but substitute previously calculated carries as we go (i) y(i) p(i) s(i) This should be g 2 c(i) g(i) c(i+1) We have written the carries in terms of values all computed when the inputs are applied to the circuit: All p i and g i are computed after 1 gate delay. All c i are then computed after 2 more gate delays, since the are 2-level SOP in terms of p i and g i. ECE124 Digital Circuits and Systems Page 24

25 Carry look ahead performance If we use carry lookahead to generate all of the carries, then our adder will have a delay of 3 units of gate delay to get c n. What is the penalty to be paid? The carry lookahead circuit is 2 level logic (SOP) and we should see that higher numbered carries require more AND gates as well as AND/OR gates with a large number of inputs. It becomes imprac=cal (cant get AND/OR gates with large numbers of inputs). It becomes epensive in terms of the number of logic gates required. So, we get be`er performance, but we pay for it in terms of area and cost of the circuit implementa=on. ECE124 Digital Circuits and Systems Page 25

26 Combina=ons of ripple and carry look ahead circuits We can get something better than a ripple adder, but not as good as full carry lookahead by cascading smaller carry lookahead adders E.g., consider a 16-bit adder composed of 4, 4-bit carry lookahead adders. 4-CLA 4-CLA 4-CLA 4-CLA Performance will be = 9 units of gate delay to get c 16 (notice a ripple adder would have required 2(16)+1 = 33 units of delay. ECE124 Digital Circuits and Systems Page 26

27 Trade off area vs. delay Demonstration of Area vs. Delay for different ways of making an 8-bit adder. Note: delay is assumed to be time to generate c 8 Note: cost is calculated as #gates+#gate inputs. Note: ma gate means #inputs to the largest gate required 8-bit adder design type delay cost ma gate 250 ripple (8, 1-bit FA) 17 gates Delay Area 4, 2-bit CLA 7 gates , 4-bit CLA 5 gates , 8-bit CLA 3 gates ripple (8, 1-bit FA) 4, 2-bit CLA 2, 4-bit CLA 1, 8-bit CLA ECE124 Digital Circuits and Systems Page 27