Group 10 Group 9 Group 8 Group 7 Group 6 Group 5 Group 4 Group 3 Group 2 Group 1 Group 0 GG5 PG5 GG4 PG4. Block 3 Block 2 Block 1 Block 0

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1 CLA and Ling Adders Introduction One of the most popular designs for fast integer adders are Carry-Look-Ahead adders. Rather than waiting for carry signals to ripple from the least signicant bit to the most signicant bit, CLA adders divided the inputs into groups of r bits and implement the logic equations to determine if each group will generate or propagate a carry. By combining the generate and propagate signals of r groups at with each successive stage of logic, a CLA adder can derive the carrys into each bitin order log r n gates instead of order n for a ripple carry adder. This paper discusses the design of a very simple 3 bit CLA adder, some improvements that can be made to that adder, and a variation of CLA adders known as Ling adders. A Simple CLA Adder An overview of the adder's 4 stages is shown in gure with stage and the top and stage 4 at the bottom. In stage the local generate and propagate signals for each bit are created. In stage these signals are combined to create generate and propagate signals out of each group of 3 bits. In stage 3 the group signals are combined into 9 bit block signals. In stage 4 the carry into each block is calculated and these signals begin traveling back up the adder tree. In stage 3 the carry into each group is created, and in stage the carry into each bit is created. Finally, stage uses the local carry signals to calculate the nal sum bits CIN Group 0 Group 9 Group 8 Group 7 Group 6 Group 5 Group 4 Group 3 Group Group Group 0 GG0 PG0 GB3 PB3 CG0 GG9 PG9 CG9 GG8 PG8 GG7 PG7 GG6 PG6 CG8 CG7 CG6 GG5 PG5 Block 3 Block Block Block 0 GG4 PG4 GG3 PG3 CG5 CG4 CG3 GB PB GB PB GB0 GG PG CG GG PG CG GG0 CB CB Cout CB3 Figure : CLA Adder

2 . Generate and Propagate Signals In the rst stage of logic the adder must calculate the local generate and propagate signals (g i and p i ) which tellifeach bit will generate a carry into the next bit or propagate a carry from the previous bit. g i = a i b i () p i = a i + b i () In stage these signals are then combined into group generates and propagates (GG i and PG i ) for each of the ten groups as follows: GG 0 = g + p (g 0 + p 0 c IN ) (3) GG. = g 4 + p (g 3 + p 3 g ) (4) GG 0 = g 3 + p 3 (g 30 + p 30 g 9 ) (5) PG = p 4 p 3 p (6) PG. = p 7 p 6 p 5 (7) PG 0 = p 3 p 30 p 9 (8) where c IN is the carry in signal to the least signicant bit. Since c IN is included in GG 0,nogroup propagate signal from group 0 is needed. The group propagate signals are formed with a simple 3 input AND gate. The group generate signals are formed with the fanin-3 generate gate shown in gure. In stage 3 these signals are used to create the block generate and propagate signals (GB i and PB i ). GB 0 = GG + PG (GG + PG GG 0 ) (9) GB = GG 5 + PG 5 (GG 4 + PG 4 GG 3 ) (0) GB = GG 8 + PG 8 (GG 7 + PG 7 GG 6 ) () GB 3 = GG 0 + PG 0 GG 9 () PB = PG 5 PG 4 PG 3 (3) PB = PG 8 PG 7 PG 6 (4) PB 3 = PG 0 PG 9 (5) All the blocks can use the same fanin-3 generate gate and 3 input AND gate used in the previous stage except for block 3 which contains only two groups. Its propagate signal requires only a input OR, and its generate is create using a fanin- generate gate shown in gure 3. Having created the block generate and propagate signals, the adder begins to nally create the true carry signals.

3 p3 g g3 p4 g4 GG g4 p4 g3 p3 g Figure : FanIn-3 Generate Gate p g0 g GG0 g p g0 Figure 3: FanIn- Generate Gate 3

4 . Carry Signals In stage 4 the block generate and propagate signals are used to create the carry signals into each block (CB i ). CB = GB 0 (6) CB = GB + PB GB 0 (7) CB 3 = GB + PB (GB + PB GB 0 ) (8) C OU T = GB 3 + PB 3 CB 3 (9) where C OU T is the overow carry out of the entire adder. These signals then begin to travel back up the adder stages, rst forming the carry into each group (CG i ) in stage 3. For block these equations are as follows: CG 6 = CB (0) CG 7 = GG 6 + PG 6 CB () CG 8 = GG 7 + PG 7 (GG 6 + PG 6 CB ) () In stage these group carry signals are used to form the local carry into each bit(c i ). For group 8 these equations are as follows: c 3 = CG 8 (3) c 4 = g 3 + p 3 CG 8 (4) c 5 = g 4 + p 4 (g 3 + p 3 CG 8 ) (5) All of these signals can be created using the fanin-3 and fanin- generate gates shown in gures and 3. This means each center group and block will use one fanin-3 gate and one OR gate to create generate and propagate signals for the stage below, and one fanin-3 gate and one fanin- gate to create carry signals for the stage above. The wiring of these groups and blocks is shown in gure 4 for group. hen the local carry signals reach stage, they are used to create the nal sum bits (s i ) according to the equations: t i = a i b i (6) s i = t i c i (7).3 Critical Path The worst case inputs for this adder are when a i b i = for all the input bits and then c IN is toggled. The local generate signals require 3 series transistors to form. For an N bit CLA adder combining r groups at each level, the generate signals must travel up dlog r N e; levels of r + series transistors each. Then the signal travels down dlog r N e;levels of no more than r + 4

5 g4 p4 c4 g3 p3 c3 g p c Gate II Gate II Gate I CG GG PG Figure 4: Group series transistors. Final, the XOR to form the local sums takes series transistors. Therefore, the maximum number of series transistors in the critical path can be written as: T d = 3+(dlog r N e;)(r +)+(dlog r N e;)(r +)+ (8) T d = ( dlog r N e;3)(r +)+5 (9) For a 3 bit adder with r = 3 as described in this paper this equation gives a maximum of 5 transistors. The true critical path is 4 transistors since block 3 contains only groups instead of 3. The critical path is shown in table. Although faster designs are possible, this adder has the Operation Signal Delay Total Local Generate g i 3 3 Group Generate GG i 4 7 Block Generate GB i 4 Block Carry CB Group Carry GG Local Carry c 3 4 Local Sum s 3 4 Table : Simple CLA Critical Path advantage of a relatively simple layout and wiring. The next section discusses changes which can 5

6 be made in this design to improve performance. 3 An Improved CLA Adder The critical path delay of the simple CLA adder design presented in the previous section can be reduced signicantly at the price of making the layout and wiring more complex. 3. Single Stage Group Generate The rst improvement to be made is using a single complex gate to create the group generate and propagate signals in a single stage directly from the adder inputs. In the simple design the expression used for the group generate signal was as follows: Expanding this in terms of the adder inputs gives: GG = g 4 + p 4 (g 3 + p 3 g ) (30) GG = a 4 b 4 +(a 4 + b 4 )[a 3 b 3 +(a 3 + b 3 )a b ] (3) This equation can be implemented by annmosnetwork containing 4 series transistors followed by an inverter. The PMOS network must implement the complement of this function, which normally would also require 4 series transistors. However, the relation g i p i = p i can be used to simply the expression for GG as follows: GG = g 4 [p 4 + g 3 (p 3 + g )] (3) GG = p 4 + g 4 (p 3 + g 3 g )] (33) GG = a 4 b 4 +(a 4 + b 4 )[a 3 b 3 +(a 3 + b 3 )(a + b )] (34) This simplied expression can be implemented by a PMOS network with 3 series transistors followed by an inverter. The gate implementing the group generate for group is shown in gure 5. The gate implementing the group propagate is shown in gure 6. This change reduces the total number of series transistors used in forming the group generate signals from 7 to Carry Select Mux The second improvement eliminates the need to travel back up the adder tree after the block carrys have been formed. This is done by generating two sets of sum bits. One set assumes the carry into each block will be 0, and the other set assumes it will be. This can occur in parallel with the generation of the block carrys which are then used to control a mux which selects the proper set of sum bits. This is the same method used in carry select adders. 6

7 a b GG a b Figure 5: CLA Group Generate b a PG a b Figure 6: CLA Group Propagate 7

8 In the simple CLA adder the equations implemented by group carry, local carry, and nal sum stages for bit 3 are as follows: s 3 = t 3 c 3 (35) s 3 = t 3 CG 8 (36) s 3 = t 3 [GG 7 + PG 7 (GG 6 + PG 6 CB )] (37) This expression is converted to a mux controlled by CB by dening the signals CGF 8 and CGT 8 : CGF 8 = GG 7 + PG 7 GG 6 (38) CGT 8 = GG 7 + PG 7 (GG 6 + PG 6 ) (39) The signal CGF 8 is the carry into group 8 assuming the block carry is zero, and CGT 8 assumes the block carry is one. The nal sum bit is then written as: s 3 = CB [CGF 8 t 3 ]+CB [CGT 8 t 3 ] (40) Using these signals, the other sum bits of the group are written in similar fashion. s 4 = CB [(g 3 + p 3 CGF 8 ) t 4 ]+CB [(g 3 + p 3 CGT 8 ) t 4 ] (4) s 5 = CB [(g 4 + p 4 (g 3 + p 3 CGF 8 )) t 4 ]+CB [(g 4 + p 4 (g 3 + p 3 CGT 8 )) t 4 ] (4) Because the signals CGF 8 and CGT 8 will appear after the local generate and propagate signals, the critical path delay can be further reduced by applying the same principal to make the inputs to the mux controlled by the block carry muxes controlled by CGF 8 and CGT 8. This also allows the simplication of g i + p i = p i to be applied. s 3 = CB [CGF 8 t 3 + CGF 8 t 3 ]+ CB [CGT 8 t 3 + CGT 8 t 3 ] (43) s 4 = CB [CGF 8 (g 3 t 4 )+CGF 8 (p 3 t 4 )] + CB [CGT 8 (g 3 t 4 )+CGT 8 (p 3 t 4 )] (44) s 5 = CB fcgf 8 [(g 4 + p 4 g 3 ) t 5 ]+CGF 8 [(g 4 + p 4 p 3 ) t 5 ]g + CB fcgt 8 [(g 4 + p 4 g 3 ) t 5 ]+CGT 8 [(g 4 + p 4 p 3 t 5 ]g (45) The 3 bit slice which implements these functions is shown for group 8 in gure 7. sing the bit slice eliminates the need to go back up the adder tree after forming the block carrys, and reduces the critical path after the block carrys to a single mux delay. Because of the reduced delay from the formation of the block carrys to the nal sum output, C OU T can no longer be implemented as a function of CB as shown in equation 9 without becoming the critical path. To avoid this a fanin-4 generate gate is used to form C OU T directly from the block generates and propagates. C OU T = GB 3 + PB 3 [GB + PB (GB + PB GB 0 )] (46) This gate is shown in gure 8 and removes C OU T from the critical path. 8

9 t5 g4 p4 t4 g3 p3 t3 CGT8 CGF8 CB S5 S4 S3 Figure 7: Sum Selection Slice GB0 PB PB GB PB3 GB GB3 Cout GB3 PB3 GB PB GB PB GB0 Figure 8: FanIn-4 Generate Gate 9

10 3.3 Critical Path With a single stage group generate the critical path must still pass up dlog r N e; levels. Of these the rst level will contain r + series transistors and the others r +. The carry select mux eliminates the need to travel back up the levels of the adder to form the local carries. The mux delay from the arrival of the control signal is counted as one series transistor to form the complement of the control signal and one transistor to pass the input to the output. The number of series transistors in the critical path is therefore: T d =(dlog r N e;)(r +)+3 (47) For the 3 bit adder shown here with r = 3 this gives 5 series transistors. Using the single stage group generate eliminates series transistors, and the carry select mux reduces the delay from the formation of the block carries from 9 series transistors to. The total critical path is reduced by 9 series transistors from a total of 4 to 5. The new critical path is shown in table. Operation Signal Delay Total Group Generate GG i 5 5 Block Generate GB 4 9 Block Carry CB Result Mux s 3 5 Table : Improved CLA Critical Path 4 A Ling Adder One nal improvement that can be made to CLA design is the use of a pseudo-carry as proposed by Ling[, ]. This method allows a single local propagate signal to be removed from the critical path. To show how this is done the group generate signal for group is shown below: GG = g 4 + p 4 g 3 + p 4 p 3 g (48) Ling observed that each term in GG contains p 4 except for the very rst term which is simply g 4. However, p 4 can still be factored out of this expression by noting that g i = p i g i. GG = p 4 GG (49) GG = g 4 + g 3 + p 3 p (50) The Ling group generate signal (GG ) is simpler and can be calculated more quickly than the CLA group generate signal. When expanded out the CLA and Ling group generates are as follows: GG = a 4 b 4 +(a 4 + b 4 )[a 3 b 3 +(a 3 + b 3 )a b ] (5) GG = a 4 b 4 + a 3 b 3 +(a 3 + b 3 )a b (5) 0

11 The gate used to implement the group generate signal is shown in gure 9 and has one less series transistor than the equivalent CLA gate shown in gure 5. he Ling group propagate signals (PG i ) a b GG a b Figure 9: Ling Group Generate are formed using the same gates as in the CLA design, but they are shifted one bit to the right. The CLA and Ling group propagate signals for group one are shown below. PG = p 4 p 3 p (53) PG = p 3 p p (54) These Ling group generate and propagate signals are then combined in the same manner as before to create block carry signals. CB = GB 0 (55) CB = GB + PB GB 0 (56) CB 3 = GB + PB (GB + PB GB 0) (57) C OU T = GB 3 + PB 3[GB + PB (GB + PB GB 0)] (58) The true C OU T is simply p 3 C which could be formed with a simple AND gate, but this would OU T make it the critical path. Instead, the nal group generate signal (GG 0 ) is formed using the CLA expression rather than the Ling group generate. Also the nal group propagate (PG 0 ) is formed withinputandinsteadofinput AND to include p 3. These changes allow the true C OU T to be formed from the block generate and propagate signals as shown above without making it the critical path.

12 The nal change that must be implemented to complete the Ling adder is to insert into the sum logic the local propagate signal which was factored out of each group generate. This is done simply by ANDing the CGF and CGT signals formed from the Ling group generate and propagates i i with the local propagate signal of the most signicant bit of the previous group. This change is shown in gure 0 which depicts the sum selection logic for group 8 of the Ling adder. 4. Critical Path The only dierence in the critical path of the improved CLA and the Ling adder is the use of the Ling group generate is the rst stage as shown in table 3. This allows the group generate signals to be formed in r + series transistors instead of r +. Thechanges in the sum selection logic are o the critical path and have no eect on the total delay. Therefore, the series transistors in the critical path can be written as: T d =(dlog r N e;)(r +)+ (59) For a 3 bit adder with r = 3 the net improvement of a Ling adder over the improved CLA adder is a total delay of 4 series transistors instead of 5. Operation Signal Delay Total Group Generate GG i 4 4 Block Generate GB 4 8 Block Carry CB 3 4 Result Mux s 3 4 Table 3: Ling Critical Path

13 t5 g4 p4 t4 g3 p3 t3 p CGT*8 CGF*8 CB* S5 S4 S3 Figure 0: Ling Sum Selection Slice 3

14 References [] H. Ling. High speed binary parallel adder. IEEE Transactions on Computers, EC-5(5):799{ 80, October 966. [] H. Ling. High speed binary adder. IBM Journal of Research and Developement, 5(3):56{66, May 98. [3] R. Brent and H. Kung. A regular layout for parallel adders. IEEE Transactions on Computers, C-3(3):60{64, March 98. [4] G. Bewick, P. Song, G. DeMicheli, and M. Flynn. Approaching a nanosecond: A 3-bit adder. In Proceedings of the International Conference on Computer Design, pages {4, 988. [5] I. Hwang and A. Fisher. A 3.ns 3b CMOS adder in multiple output domino logic. In International Solid State Circuits Conference, pages 40{4, 988. [6] A. Omondi. Computer Arithmetic Systems: Algorithms, Architecture and Implementations. Prentice Hall, 994. [7] N. Quach and M. Flynn. High-speed addition in CMOS. Technical Report CSL-TR-90-45, Stanford University, February 990. [8] S. Waser and M. Flynn. Introduction to Arithmetic for Digital Systems Designers. Holts, Rinehart and Winston, 98. 4