A CASE STUDY OF CARRY SKIP ADDER AND DESIGN OF FEED-FORWARD MECHANISM TO IMPROVE THE SPEED OF CARRY CHAIN

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1 Volume 117 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu A CASE STUDY OF CARRY SKIP ADDER AND DESIGN OF FEED-FORWARD MECHANISM TO IMPROVE THE SPEED OF CARRY CHAIN 1 Premson Y, 2 Sakthivel.R, 3 Vivek.T, 4 Vanitha M 1 Govt. Engineering College, Mananthawady, India 2,3 School of Electronics Engineering, VIT University, Vellore, India 4 School of Information Technology and Engineering, VIT University, Vellore, India 1 ypremson@gmail.com, 2 rsakthivel@vit.ac.in Abstract: Basic operation in every digital computers is addition and subtraction, multiplication is implemented using repeated adding and division by repeated subtraction which can be programmed. Adders are not only used in ALUs(arithmetic logic units), but also in many circuits used in of the processors including digital signal processors and general purpose processors. So improving speed, area and energy parameters of adders will improve the performance of whole ALU. Different types of adders are available in the market such as ripple carry adder, carry look ahead adder, carry select adder, carry skip adder etc. In this paper, two different Carry skip adders are compared and slightly modified version of both architecture is proposed that can increase the speed. It incorporates a carry feed forward block to the existing structures so that the delay can be reduced. The proposed architecture can be used for high speed application by the cost of area. The adders compared in this paper are CSKA (conventional carry skip adder) and CI-CSKA (Concatenation Incrementation Carry skip adder), and the proposed models are CFF-CSKA (Carry Feed Forward CSKA) and CFF-CI-CSKA. Index terms: (Ripple Carry Adder) RCA, (Carry Skip Adder) CSKA,AOI and OAI logic, CI- CSKA.(Concatenation Incrementation CSKA), CFF Mechanism(Carry Feed Forward Mechanism) 1. Introduction The adders are not only used in ALUs(arithmetic logic units), but also in many circuits used in of the processors including digital signal processors, for calculating addresses, increment and decrement operators, and similar operations. So improving speed, area and energy parameters of adders will improve the performance of whole ALU [1]. So many works are performed in the area of improving area and delay parameters [2][3]. Many adder architectures are proposed the decrease delay and area and power. The basic structure is RCA (Ripple carry adder) [4] whose area is less but the delay is high. For the carry propagation condition the carry have to propagate through every full adders. This carry propagation path of carry represents the critical path of the adder. As the number of bits increases the delay for generating the output increases which makes RCA not ideal for adding large numbers. One other architecture is CLA (Carry Look Ahead adder) or parallel prefix adders [5] in which the carry for each stage is generated by separate AND- OR logic so that the delay for carry propagation from one stage to other stage can be avoided, but as the number of bits increases the area and complexity of the circuit. The other one is carry skip adder (CSKA) in which the carry is skipped using a multiplexer [6]. When every inputs are in propagation condition, the mux selects the carry for next state as previous state without waiting for addition of last bit. A much more developed architecture of CSKA was developed in [7] that have very less delay when compared to conventional CSKA. The model is CI- CSKA (Concatenation Incrementation CSKA) which combines the concatenation and incrementation schemes to conventional CSKA and carry is skipped by using AOI and OAI logic[8]. This structure focus on increasing speed of operation and decreasing the area. The use of AND OR invert logic as carry skip will also help to decrease area as it has less number of transistors when compared to multiplexer. In this paper, two different adders, conventional CSKA and CI-CSKA are compared for area, power and speed and two modified architecture is proposed, modified CSKA with Carry feed forward mechanism 91

2 (CFF-CSKA) and CI-CSKA with Carry feed forward mechanism (CFF-CI-CSKA) which can improve the speed in cost of area and power. The paper is organised as follows, Section II explains about the previous works on CSKA and C.I.CSKA, Section III explains the proposed modified architecture with carry feed forward mechanism, Section IV gives the simulation results for all adders, Section V gives the results and discussion and Section VI gives the conclusion. 2. Previous Works 2.1 Conventional Carry Skip Adder In conventional Carry skip adder [9] addition is performed in multiple stages. Each stage consists of a RCA block, a multiplexer and a carry prediction unit. RCA is used to find the sum of each stage. It takes the input bits of two numbers A and B, and generates the sum. The designed model uses a 4-bit RCA block. When all bits of corresponding stage is in propagation condition (Eq.1) the carry prediction unit will generate one as output. Eq.(1) T MAX = T XOR +T AND +T MUX T MAX =T RCA +T MUX Eq.(2) Eq.(3) A 2 to 1 multiplexer is used as the carry skip logic. The output of carry prediction unit is fed to the mux. If the output of carry prediction unit is high the mux selects the previous carry Cp without waiting for the carry generated from the RCA block. When two numbers A and B are added the worst case delay happens when both numbers are in carry propagation condition. In this case the carry will propagate from one stage to the input of next stage without waiting for the carry generation by RCA. The maximum time taken for carry generation (Eq.2) is the propagation time of multiplexer and the time for carry prediction. If any of the input to RCA is not in propagation condition the multiplexer will select the first input that is the carry from the RCA block. In this case the next stage has to wait until the carry is generated by the RCA block of previous stage. The maximum time taken for carry generation of if the input bits are not in propagation condition (Eq.3) is the sum of time for carry propagation through RCA block and multiplexer. The propagation time through RCA TRCA depends on from where the carry is generated. If the carry is generated in the first input bit, then it have to propagate through four full adders that is eight XOR gates which makes the time for addition very high. The disadvantage of this adder is that it can skip carry only when all bits are in propagation condition. It is not sure that always every input bits are in carry propagation condition. 2.2 Concatenation Incrementation Carry Skip Adder The CI CSKA (Fig.1) [10] is much more optimized version of CSKA which have an improved speed. It incorporates the concatenation and incrementation schemes to the conventional adder and hence C.I.CSKA (Concatenation Incrementation CSKA). The C.I.CSKA consists of RCA block Incrementation block and a skip logic. The two key ideas of C.I.CSKA is that it substitutes multiplexer carry skip logic with AND-OR Invert and OR-AND Invert logic and the sum will be generated in two stages. The advantage of using AOI- OAI skip logic is that it have less number of transistors, smaller delay and less fabrication cost when compared to multiplexer. The disadvantage is that as the skip logic is invert logic the carry get inverted as it propagates. So an additional NOT gate is required to invert the Figure 1. C.I.Carry Skip Adder 92

3 carry before feeding that to the incrementation block to compensate the inversion provided by AOI-OAI compound gates. The sum is found in two stages. The RCA block finds intermediate results that are the first stage and the final result is the result from the incrementation block (Fig 2). The incrementation block is a chain of half adders in which one input is carry of previous stage and other input is intermediate result. Since the carry input is given to incrementation block, there is no carry input for RCA block and hence all the 1 st Full adders of RCA block in all stages except the 1 st stage can be replaced by half adder. In the first stage sum is calculated by RCA and the carry is propagated to AOI block. The propagated carry is given to both AOI skip logic and also to the incrementation block. Since the RCA blocks of every stage does not requires carry of previous stages all RCA block find the intermediate results simultaneously. The operation of AOI and OAI stages can be explained by two cases, first case is that if carry is propagated from previous state and second is when carry is not propagated. Consider the case in which carry is propagated from previous stage and all input bits are in carry propagation condition, then all intermediate bits will be 1, hence the output of AND gate will be 1. This one will be propagated to AOI logic. The first gate of AOI compound gate is AND gate. This AND gate will generate 1 only if there is a carry from previous stage is 1. The second gate of AOI compound gate is NOR. So the input to this NOR will be one so it will generate output 0, which is the inverted carry from previous stage. This is again inverted by a NOT gate and given to incrementation block. So the time of propagation of carry in this case (eq.4) will be the sum of time taken by and gate TAND and time taken by skip logics which can be TOAI or TAOI logic. T=T AND +T SKIP Eq.(4) T=T RCA +T SKIP Eq. (5) If all input bits are in propagation condition and carry from previous stage is zero the output of AND gate in AOI will be zero and hence it have to wait to receive the third input which is from RCA. Same condition exists if the input bits are not in propagation condition. Similar case occurs for OAI block also. The time required for carry propagation if all the intermediate results are not one (Eq.5) will be the sum of time taken for carry propagation through the RCA chain TRCA and the time taken for carry to propagate through the skip logic. Figure 2. Incrementation block Figure 3. Carry feedforward block Advantage of this model is that for finding carry output of next stage the carry from incrementation block is not required. So the delay for generation of final result does not depends on the delay for carry propagation from one block to other. Also all the intermediate results can be calculated simultaneously by RCA without waiting for the carry from previous block. The carry is calculated based on intermediate results and carry from previous block. The disadvantage of this model is that if all inputs are not in propagation condition then all the intermediate results will not be one, in such cases the skip logic have to wait for the carry from RCA block. 93

4 Figure 4. Proposed Carry Feed Forward CSKA 3. Proposed Architectures 3.1 Proposed CSKA with CFF-Mechanism In conventional carry skip adder the carry is skipped only when all input bits are in propagation mode. Only in this case the carry prediction unit will generate an output of one, which is given to multiplexer as select line. Based on this input the multiplexer is selecting any one of the input that is the carry of previous state or the carry of the RCA. If the input bits are not in propagation mode the adder will have to wait until the carry of RCA block is generated. The probability of all bits in propagation mode is very less. The idea of proposed model is that to generate the carry from of the input bits, if input bits are not in propagation condition. The input bits are first fed to a XOR gate. In this step we can reuse the XOR gate which is used by the carry prediction unit. The carry is generated from this XOR outputs by using simple AND- OR logic which is a modified version used in Look ahead carry adder. The block which is used to generate carry is carry feed forward block (Fig.3) and the complete architecture is shown in Fig.4. The carry generated by this carry feed forward block is fed to the input of multiplexer. The multiplexer will select the carry generated from carry feed forward block if the input bits are not in propagation mode. So the delay when input bits are not in propagation condition (eq.6) is the sum of time for propagation through XOR gate and time for propagation through AND-OR logic and time for propagation through the skip logic. T=T XOR +T AND +T OR +T MUX ---- Eq.(6) Delay in conventional adder was the delay of RCA chain that is reduced to delay of AND and OR logic. The proposed model can generate the carry without much delay when the input bits are not in propagation condition. A conventional carry skip adder skip carry only if the bits are in propagation condition, and in other cases the delay will be proportional to number of XOR gate the carry propagates. Since the carry is generated by the carry feed forward mechanism we does not require carry from the RCA chain. So the last full adder in this RCA chain is replaced by two XOR gates. The two AND gates in the last full adder of each RCA block can be removed, which helps to reduce the area. For generating the carry the carry feed forward block requires 4-AND gates and 1-OR gate. Out of this 4-AND gates two will be compensated by removal of two AND gate from last full adder of RCA chain. So only two AND gates and one OR gate will be more in the proposed architecture. The proposed model is more optimized version of CSKA for high speed applications. 94

5 Figure 5. Proposed C.I.CSKA with carry feed forward mechanism 3.2 Proposed C.I. CSKA with Carry Feed Forward Mechanism In C.I.CSKA carry skip adder the carry is skipped only when all the intermediate inputs are one. This happens only when all input bits are in propagation mode. If this case is not happed the second gate in OAI-AOI compound gate will wait for the carry generated by the RCA block. If the carry starts propagating from the first adder then the carry have to propagate through all eight XOR gates and the delay in this case will the very high. The proposed CFF-C.I.CSKA uses the same CFF mechanism which is used by CFF-CSKA. That is to generate the carry from of the input bits. The input bits are first fed to a XOR gate. The output of this XOR gate is fed to AND-OR logic to generate the carry of each RCA block. The block which is used to generate carry is carry feed forward block (Fig.3) and the complete proposed architecture is shown in Fig.5. The carry generated by this carry feed forward block is fed to the second gate of AOI-OAI skip logic. In cases where the input bits are not in propagation mode the CFF block will generate the carry output using AND- OR logic, from the XOR ed input bits. The CFF block requires two three input AND gate and one OR gate. Since the carry provided to each RCA block is zero, the number of AND gates in carry feedforward block can be limited to three. Since the last full adder is modified with out AND gates, the newly added block requires only one AND and one OR gate. By adding 4-XOR gates, one AND and one OR gate per block it is possible to make the C.I.CSKA to skip carry in all conditions. Since the carry input to each RCA block is zero, the first full adder in each RCA block can be replaced by half adders. Also the carry generated by RCA block is not required because the carry feedforward block generates the carry. Hence the last full adder of RCA chain is modified in such a way that the two AND gates required for the generation of output carry is removed. The carry generated by CFF block helps the second gate in the AOI-OAI logic to decide the carry of next block. The advantage is that if the bits are not in propagation mode the adder will have to wait until the carry of RCA block is generated. This architecture has so many advantages. In CI-CSKA finding carry output of each stage the carry from incrementation block is not required. In CFF CI-CSKA the carry for next block does not requires the carry from incrementation block as well as from RCA block. The carry from RCA block is generated by CFF block which can reduce the delay (E.7). T MAX =T XOR +T AND +T OR +T AOI (or)t OAI (7) Thus the carry is calculated based on intermediate results and carry from previous block if all intermediate bits are in propagation condition. If not the carry to next state is find from CFF mechanism. The disadvantage of this model is that for carry calculation we requires 4- XOR gates, three AND gates and one OR gate per block. Since the first full adder in each RCA block is replaced by half adder and the last full adder of RCA chain is modified in such a way that the two AND gates required for the generation of output carry is removed the increase in area due to feed forward block can be compensated to a greater extend. This proposed CFF-CI-CSKA is an area efficient model which compensates for two XOR gates and two AND gates. CFF-CI-CSKA can be used for high speed applications. 95

6 4. Simulation Results The proposed circuit is modeled using the Verilog and simulated using Modelsim. Six set of test vectors are used for functional verification of both proposed models.fig.6 represents the simulation results for 64-bit CFF- CSKA and Fig.7 gives the simulation results for 64 bit CFF CI-CSKA. Table 1. Comparison of area of conventional models and proposed models 32-bit Adder 64-bit Adder CSKA CFF- CSKA CI-CSKA CFF-CI-CSKA Table 2. Comparison of power of conventional models and proposed models Figure 6. Simulation Results for proposed 64-bit Carry feed-forward CSKA The power of CSKA, CFF-CSKA, CI-CSKA and CFF- CI-CSKA is compared in Table.2. The proposed models CFF-CSKA and CFF-CI-CSKA dissipates more power when compared to the existing models because the increase in the number of logic elements. Graph 1. Graph showing area of existing and proposed architectures. Figure 7. Simulation Results for proposed 64-bit Carry feed-forward CI-CSKA 5. Results and Discussions The tool used for analyzing area, power and data arrival time is design compiler. The library used is saed 90nm technology library. The area of CSKA, CFF-CSKA, CI- CSKA and CFF-CI-CSKA is compared in Table.1. The proposed models CFF-CSKA and CFF-CI-CSKA consumes more area when compared to the existing models. By the cost of small area we can increase the speed to a greater extend. The area comparison of the existing and proposed adders is given in Graph.1. The increase in area can be clearly obtained from the graph. The increase in area is due to extra circuitry we add for carry generation CSKA&CFF- Existing Models CSKA Proposed CI-CSKA&CFF- CI-CSKA 96

7 Graph 2. Bar Graph showing power of existing and proposed architectures CSKA&CFF-CSKA CI-CSKA&CFF-CI- CSKA Existing Models Proposed The power comparison of the existing and proposed adders is given in Graph.1. The power increases a little, which is obtained from the graph. The increase in power is due to extra logic elements we add for carry generation. Since the design is a purely combinational circuit the data arrival time is considered for timing analysis.table.3 shows the comparison of data arrival time of different adders. Table 3. Comparison of data arrival time of conventional models and proposed models 32-bit Adder CSKA CFF- CSKA CI-CSKA CFF-CI-CSKA bit Adder Graph 3. Graph showing timing parameter for existing and proposed architectures CSKA&CFF-CSKA Existing Models Proposed CI-CSKA&CFF-CI-CSKA The time taken for data arrival of CSKA, CFF- CSKA, CI-CSKA and CFF-CI-CSKA is compared in Table.3. The proposed models CFF-CSKA and CFF-CI- CSKA takes less time for data arrival when compared to the existing models. Graph.3 gives the comparison of data arrival time of existing and a proposed adder clearly shows that the proposed models performs well in timing. The proposed CFF model can improve the timing. 6. Conclusion The conventional carry skip adder can be used to skip carry only if the input bits are in carry propagation condition. In CI-CSKA also the carry can be skipped only if the intermediate results are one. But the proposed structure can skip the carry if the input bits are in carry propagation or carry generation condition. The proposed CFF-CSKA architecture requires only 2-AND gates and one OR gate in addition to skip carry. CFF-CSKA is a speed optimized version of conventional CSKA. The second proposed model was CFF-CI-CSKA. This model incorporates many advantages and can be used for very high speed applications. But the extra circuit added with this architecture consumes large area.analysis shows that the proposed models consumes more area and power but it has an improved timing.so it can be concluded that the proposed models can be used for high speed applications by the cost of area and power. References [1] S. K. Mathew, M. A. Anders, B. Bloechel, T. Nguyen, R. K. Krishnamurthy, and S. Borkar, A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 1, pp , Jan [2] V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, and R. Krishnamurthy, Comparison of highperformance VLSI adders in the energy-delay space, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp , Jun [3] Kerur, S.S., Saktivel, R., Kittur, H., Girish, V.A. Low power high performance carry select adder (2014) International Journal of Applied Engineering Research, 9 (2), pp [4] R. Zlatanovici, S. Kao, and B. Nikolic, Energy delay optimization of 64-bit carry-lookahead adders with 97

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