Implementation Of Radix-10 Matrix Code Using High Speed Adder For Error Correction

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1 Implementation Of Radix-10 Matrix Code Using High Speed For Error Correction Grace Abraham 1, Nimmy M Philip 2, Deepa N R 3 1 M.Tech Student (VLSI & ES), Dept. Of ECE, FISAT, MG University, Kerala, India 2 Assistant Professor, Dept. Of ECE, FISAT, MG University, Kerala, India 3 Assistant Professor, Dept. Of ECE, FISAT, MG University, Kerala, India gracemampilly@gmail.com, nimmyphilip@fisat.ac.in, deepanr@fisat.ac.in Abstract Memories are most widely used component in electronic systems. As CMOS technology scales down, multiple cell upsets (MCUs) are causing series issues in memory reliability. In order to protect data in memory, error detection and correction codes are used. The problem with existing error correction codes is that they are either single or double error correction codes. To overcome this issue, a radix-10 based matrix code can be used for multiple error detection to protect memory. This system uses an encoder and decoder section. In this paper, this approach further optimizes the delay with the use of fast adders like parallel prefix carry look ahead adder. A Comparison of radix-10 matrix code using different types of adders was made in order to reduce the delay. The design was modeled using verilog, simulated and synthesized using Xilinx ISE 14.7 and Cadence. Index Terms Multiple cell upsets (MCUs), error correction codes (ECCs), reliability, SRAM I. INTRODUCTION Memories are one of the most widely used elements in electronic systems. As technology scales down, the occurrence of the multiple bit upsets becomes an increasingly important factor in the reliability of memories. Soft errors caused by radiation are a major issue for memory reliability. To prevent soft errors from causing data corruption we use error correction codes (ECCs). As technology scales, a single particle hit upsets multiple memory cells. This phenomenon is known as multiple cell upset (MCU). For example, radiation induced MCUs on memory ICs such as SRAMs are upsets in which a single radiation event causes several bits to flip. Soft errors are also a major concern in space applications. They cause serious consequences for the spacecraft, including loss of information, functional failure or loss of control. Major causes of MCUs are alpha particles from package decay, cosmic rays, thermal neutrons, random noise. It occurs mainly in space environments due to ionizing effects [2]. MCUs are becoming important problems in designing memories because of the following reasons: 1) Increase in probability of MCUs due to technology shrinkage. 2) Probability of having multiple errors is increased when size of memory is increased. Unfortunately, packaging and shielding cannot effectively be used to shield against single event upsets and multiple cell upsets. This is because these upsets are caused by neutrons which can penetrate through packages. To prevent MCUs, memories are protected with error correction codes (ECCs). When an ECC is used, the data are encoded and they are written in memory and are decoded when they are read from memory. For example, Hamming codes [3], Matrix codes [4] and Punctured difference set (PDS) codes have been used as ECC. But these codes require more area, delay overhead and are capable of correcting only up to two errors. Another method to protect memories is the use of built-in current sensors (BICS). BICS [5] can detect errors by detecting changes in the current. The sensors are placed in the columns of the memory. Unexpected current variations are detected by the sensors and thereby detecting the error bit positions. Integer addition is one of the most basic operations of this system. An effective functioning of adders plays a major role in the architecture. Use of fast adder design in the circuit may decrease the delay of the circuit. The high speed, small area and low cost are the main considerations of VLSI circuits. In this paper, a novel radix-10 based matrix code on divide symbol is proposed. This is used to provide enhanced memory reliability. This method uses radix-10 based algorithm to detect errors, which are mainly the integer addition and subtraction. The encoder is reused in decoder section in order to reduce the area-overhead. The error detection capability is maximized using this technique. The paper is divided in to the following sections. In section II, the proposed radix-10 matrix code is explained along with its encoder and decoder circuits. In next section, different types of adders which can be implemented in this design are discussed. The implementation of radix-10 matrix code using a high speed adder and the results are discussed in section IV. Finally, conclusion and future scope of this paper are discussed in section V

2 II. RADIX - 10 MATRIX CODE The block diagram of radix-10 based matrix code is shown in Figure 1. It includes an encoder, SRAM and a decoder. The information bits I, are fed to the encoder. During the encoding process, the values of horizontal redundant bits H and vertical redundant bits V are obtained. After the encoding process, the information bits I, are stored in the memory (SRAM). If MCUs occur in memory, some values of memory cells may get flipped. These errors in memory can be corrected using a decoder. Encoder Memory Decoder Fig. 2. Encoder section of radix-10 matrix code The algorithm of the encoding process is shown in Figure 3. To explain the encoding scheme, 32-bit information is taken as an example. The values from I 31 -I 0 are information bits. H 19 -H 0 are horizontal redundant bits, V 15 V 0 are vertical redundant bits and C 31 -C 0 are information bits which are copied directly from I 31 -I 0. Start Get the 32-bit information bit I 31-I 0 I xor gate SRAM (Information) SRAM (Redundancy) Encoder reused Syndrome Calculator Error locator Error Corrector I correct Compute H (horizontal bits),v(vertical bits) and C(copy of data bits) Fig.1. Block diagram of radix-10 matrix code III. RADIX-10 MATRIX CODE ENCODER In Encoder, N-bit information is divided in to k symbols of m bits (N=k x m). Arrange k symbols in a k 1 x k 2 2D-matrix where k 1 and k 2 represents the row and column numbers of the matrix. In next step, the horizontal redundant bits (H) are produced by decimal integer addition among the selected symbols in the row and similarly for the horizontal redundant bits H 14 H 13 H 12 H 11 H 10 and H 19 H 18 H 17 H 16 H 15. H 4 H 3 H 2 H 1 H 0 = I 3 I 2 I 1 I 0 + I 11 I 10 I 9 I 8 (1) H 9 H 8 H 7 H 6 H 5 = I 7 I 6 I 5 I 4 + I 15 I 14 I 13 I 12 (2) The vertical redundant bits (V) are obtained by xor operation among bits per columns and similarly for the rest vertical redundant bits. V 0 = I 0 I 16 (3) V 1 = I 1 I 17 (4) A 32-bit radix-10 matrix code encoder structure using multibit adders and xor gates is shown in Figure 2. Store information bits in Memory (SRAM) Stop Fig. 3. Algorithm of encoding process STEP 1: Divide N-bit word into k symbols of m bits. Arrange them in a k1 x k2, 2D matrix form. e.g.: A 32-bit information is divided into 8 symbols of 4 bits as shown in Figure 4. Symbol 3 Symbol 2 Symbol 1 Symbol 0 Symbol 7 Symbol 6 Symbol 5 Symbol 4 Fig. 4. A 32-bit word is divided into 8 symbols of 4 bits. Symbol 0= I 3 I 2 I 1 I 0 = 1100 Symbol 4= I 19 I 18 I 17 I 16 = 1111 Symbol 1= I 7 I 6 I 5 I 4 = 1010 Symbol 5= I 23 I 22 I 21 I 20 = 1010 Symbol 2= I 11 I 10 I 9 I 8 = 0110 Symbol 6= I 27 I 26 I 25 I 24 = 0101 Symbol 3= I 15 I 14 I 13 I 12 =1111 Symbol 7= I 31 I 30 I 29 I 28 = 1111 I 31 I 0 En I 3-I 0 I 11-I 8 I 23-I 20 I 31-I 28 I 16 I 0 I 31 I 15 I 31-I 0 H 4-H 0 H 19-H 15 V 0 V 15 C 31-C 0 H V C STEP 2: Calculate the horizontal redundant bits (H) by the decimal integer addition, among symbols in the row

3 Fig. 5. Horizontal bits are represented along with the 32 bit information bit. H 4 H 3 H 2 H 1 H 0 = Symbol 0+Symbol 2 = =10010 H 9 H 8 H 7 H 6 H 5 = Symbol 1+Symbol 3 = =11001 H 14 H 13 H 12 H 11 H 10 = Symbol 4+Symbol 6 = =10100 H 19 H 18 H 17 H 16 H 15 = Symbol 5+Symbol 7 = =11001 STEP 3: Calculate the vertical redundant bits (V) by binary operation among the bits per column. V 0 = I 0 I 16 = 0 1 = 1 V 8 = I 8 I 24 = 0 1 = 1 V 1 = I 1 I 17 = 0 1 = 1 V 9 = I 9 I 25 = 1 0 = 1 V 2 = I 2 I 18 = 1 1 = 0 V 10 = I 10 I 26 = 1 1 = 0 V 3 = I 3 I 19 = 1 1 = 0 V 11 = I 11 I 27 = 0 0 = 0 V 4 = I 4 I 20 = 0 0 = 0 V 12 = I 12 I 28 = 1 1 = 0 V 5 = I 5 I 21 = 1 1 = 0 V 13 = I 13 I 29 = 1 1 = 0 V 6 = I 6 I 22 = 0 0 = 0 V 14 = I 14 I 30 = 1 1 = 0 V 7 = I 7 I 23 = 1 1 = 0 V 15 = I 15 I 31 = 1 1 = 0 are original information bits. By this process we can detect the errors. With the help of vertical syndrome bit S, the correct position of the error can be located. The error corrector will correct errors by inverting the values of error bits. I 0correct = I 0 S 0 (7) H V I 31 -I 0 En I 3-I 0 I 11-I 8 I 23-I 20 I 31-I 28 I 16 I 0 I 31 I 15 I 31-I 0 H 4-H 0 H 19-H 15 V 0 V 15 Subtrator.. Subtrator.. Encoder Syndrome Calculator Error locator Fig. 6. Vertical bits are represented along with the 32 bit information bit. STEP 4: The information bits are stored in memory. The information bits are stored in the memory. If the memory is exposed to radiation, multiple cell upsets may occur. These errors are detected and corrected by the decoding process. IV. RADIX-10 MATRIX CODE DECODER Decoding process is used to detect and correct the errors caused by the radiation. The block diagram of the radix-10 matrix code decoder is shown in Figure 7. Decoder consists of encoder which is reused, syndrome calculator, error locator and error corrector. From the information bit we calculate the horizontal (H ) and vertical (V ) redundant bits. Then find out the horizontal syndrome bits ΔH and vertical syndrome bits S using syndrome calculator. Compare the horizontal redundant bits with the one obtained in encoder section by using a subtractor to obtain ΔH. ΔH 4 H 3 H 2 H 1 H 0 = H 4 H 3 H 2 H 1 H 0 H 4 H 3 H 2 H 1 H 0 (5) Similarly calculate vertical syndrome bit by doing xor operation of vertical redundant bits with one obtained in encoder section. S 0 = V 0 V 0 (6) When ΔH and S are equal to non zero, this indicates the presence of error otherwise the information bits Error corrector I correct En signal Extra Circuit Read Write Signal Signal Encoder Fig bit matrix code decoder structure. Function 0 1 Encoding Decoder 1 0 Compute syndrome bits In this scheme, the area of radix-10 matrix code is minimized by reusing its encoder in decoder section to find horizontal and vertical redundant bits. The enable signal En is used for distinguishing the encoder from decoder, and it is under the control of the write and read signals in memory. In encoding process (write), the radix- 10 matrix code encoder is only an encoder to execute the encoding process. However, in the decoding (read) process, this encoder is used for computing the syndrome bits in the decoder. The algorithm of the decoding process is shown in Figure 8. The different steps of decoding process are explained

4 Start Get information bit I 31 -I 0 from memory Compute H (horizontal bits) and V (Vertical bits) Compute ΔH and S Fig. 9. Multiple cell upsets occurred in a 32 bit data due to radiation particles. Step 2: Calculate the horizontal and vertical redundant bits for the received information bits. Horizontal redundant bits are Yes If ΔH, S=0 No H 4 H 3 H 2 H 1 H 0 =Symbol 0+Symbol 2= =10110 H 9 H 8 H 7 H 6 H 5 =Symbol 1+Symbol 3= =11001 H 14 H 13 H 12 H 11 H 10 =Symbol 4+Symbol6= =10100 H 19 H 18 H 17 H 16 H 15 =Symbol 5+Symbol7= =11001 No error Original Information bit Correct the error bit using I correct= I i S i Vertical redundant bits are V 0 =I 0 I 16 =1 1=0 V 1 =I 1 I 17 =1 1=0 V 2 =I 2 I 18 =1 1=0 V 3 =I 3 I 19 =1 1=0 V 4 =I 4 I 20 =0 0=0 V 5 =I 5 I 21 =1 1=0 V 6 =I 6 I 22 =0 0=0 V 7 =I 7 I 23 =1 1=0 V 8 =I 8 I 24 =1 1=0 V 9 =I 9 I 25 =1 0=1 V 10 =I 10 I 26 =1 1=0 V 11 =I 11 I 27 =0 0=0 V 12 =I 12 I 28 =1 1=0 V 13 =I 13 I 29 =1 1=0 V 14 =I 14 I 30 =1 1=0 V 15 =I 15 I 31 =1 1=0 Stop Fig. 8. Algorithm of decoding process STEP 1: Receive the radiation affected information bits from memory. If the radiation affects the memory, the MCU will occur. Due to radiation, some of the information bits are flipped. One bit in symbol 2 and two bits in symbol 0 are flipped. Symbol 0=I 3 I 2 I 1 I 0 =1111 Symbol 4=I 19 I 18 I 17 I 16 =1111 Symbol 1=I 7 I 6 I 5 I 4 =1010 Symbol 5=I 23 I 22 I 21 I 20 =1010 Symbol 2=I 11 I 10 I 9 I 8 =0111 Symbol 6=I 27 I 26 I 25 I 24 =0101 Symbol 3=I 15 I 14 I 13 I 12 =1111 Symbol 7=I 31 I 30 I 29 I 28 =1111 Fig. 10. Horizontal and vertical bits of received information bits are represented along with received information bit. Step 3: Calculate the horizontal syndrome bits by decimal integer subtraction. ΔH 4 H 3 H 2 H 1 H 0 =H 4 H 3 H 2 H 1 H 0 -H 4 H 3 H 2 H 1 H 0 =00100 Similarly, ΔH 9 H 8 H 7 H 6 H 5 =00000, ΔH 14 H 13 H 12 H 11 H 10 =00000, ΔH 19 H 18 H 17 H 16 H 15 = When the decimal value of ΔH 4 H 3 H 2 H 1 H 0 is not 0, which represents that errors are detected and located in 252

5 symbol 0 or symbol 2. Subsequently, the precise location of the bits that were flipped can be located by using the vertical syndrome bits. S 0 =V 0 V 0 = 0 1 = 1 S 8 =V 8 V 8 = 0 1 = 1 S 1 =V 1 V 1 = 0 1 = 1 S 9 = V 9 V 9 = 1 1 = 0 S 2 =V 2 V 2 = 0 0 = 0 S 10 =V 10 V 10 = 0 0 = 0 S 3 =V 3 V 3 = 0 0 = 0 S 11 =V 11 V 11 = 0 0 = 0 S 4 =V 4 V 4 = 0 0 = 0 S 12 =V 12 V 12 = 0 0 = 0 S 5 =V 5 V 5 = 0 0 = 0 S 13 =V 13 V 13 = 0 0 = 0 S 6 =V 6 V 6 = 0 0 = 0 S 14 =V 14 V 14 = 0 0 = 0 S 7 =V 7 V 7 = 0 0 = 0 S 15 = V 15 V 15 = 0 0 = 0 This indicates that there is error in 0 th,1 st and 8 th bit. Step 5: Errors are corrected and original information bits are obtained. I 0correct = I 0 S 0 = 1 1 = 0 I 1correct = I 1 S 1 = 1 1 = 0 I 8correct = I 8 S 8 = 1 1 = 0 Fig. 11.The corrected 32 bit information bits. V. TYPES OF ADDERSDERS To increase the performance of radix-10 matrix code different types of adders are used. s like ripple carry adder, carry look ahead adder, carry-skip adder, carryselect adder, parallel prefix carry look ahead adders like kogge-stone adder [6] and brent-kung adder [7] are placed in encoder and decoder section and their performance was compared. A. Ripple Carry (RCA) To add an N bit number, multiple full adder circuits can be cascaded in parallel. In a Ripple Carry (RCA), the carry out of one full adder is given as the carry in of the succeeding next most significant full adder. It s called a ripple carry adder because the carry bits are rippled to the next stage. B. Carry Look Ahead Carry look ahead adders are used to reduce the computation time of two binary number addition. The two signals P and G known as carry propagator and carry generator are produced. The carry propagator is propagated to the next level whereas the carry generator is used to generate the output carry, regardless of input carry. The block diagram of a 4-bit carry look ahead adder is shown in Figure 13.The corresponding boolean expressions are given here to construct a carry look ahead adder. P i = A i B i (8) G i = A i B i (9) The output sum and carry can be expressed as Sum i = P i C i (10) C i+1 = G i + ( P i C i ) (11) The Boolean function for the carry output of each stage are shown below and substitute for each C i, its value from the previous equations C 1 =G 0 + P 0 C 0 (12) C 2 =G 1 +P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 (13) C 3 =G 2 +P 2 C 2 = G 2 P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 C 0 (14) C 4 =G 3 + P 3 C 3 = G 3 P 3 G 2 P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 (15) Fig. 13. Carry look ahead adder C. Carry Skip A carry-skip adder consists of a ripple carry-adder with a special speed up carry chain known as a skip chain. This chain includes ripple carry blocks, which consists of a skip adder. A multiplexer is used for selecting a generated carry or a propagated carry with its selection line being the output of the comparison circuit. Fig. 12. Ripple carry adder 253

6 D. Carry Select Fig. 14. Carry skip adder Fig. 15. Carry select adder The carry-select adder consists of two ripple carry adders and a multiplexer. Two ripple carry adders are used for adding two n-bit numbers with a carry-select adder in order to perform the calculation twice, one time with the assumption of the carry being zero and the other assuming one. After the calculation of two results, the sum and the carry is then selected with the multiplexer. E. Kogge Stone It is a parallel prefix form of CLA. It is considered as the fastest adder among other ones. It is the common design for high-performance adders in industry. The time required to generate carry signals in this prefix adder is O(log n). Figure 16 shows the design of 4-bit Kogge Stone. CP 0 = P i and P j (16) CG 0 = ( P i and G j ) or G i (17) Fig. 17. Brent kung adder The cost and wiring complexity are greatly reduced by using this adder. But the logic depth of Brent-Kung adder increases to 2log (2n-1), hence the speed is lower. VI. RESULTS The proposed design was coded in verilog, simulated and synthesized using Xilinx ISE design suite 14.7 and Cadence. The radix-10 matrix code was implemented in FPGA Spartan 3E. Comparison of radix-10 matrix code using various types of adders was done. A. Simulation Results The simulated results of radix-10 matrix code is shown in figure 18. Inputs applied are I in [31:0] = C in [31:0] = Output obtained is I correct [31:0] = I in is the original information bit, C in is the information bit with errors, I correct is the corrected information bit. Fig. 16. Kogge stone adder and the carry operator F. Brent Kung The Brent-Kung adder is a type of parallel prefix adder. Parallel prefix adders are based on the use of generate and propagate signals. Fig. 18. Output waveform of radix-10 matrix code B. Synthesis Results The synthesis results of radix-10 matrix code includes the delay analysis of the circuit (gate delay and logic delay), the memory usage and the device utilization summary which includes the area in terms of gate count, number of LUTs used. The RTL schematic of the circuit was also obtained

7 Grace Abraham et al, IJRCCT, Vol 5, Issue- 5, May ISSN (Online) Fig. 19. Device utilization summary The device utilization summary is shown in Figure 19 and the timing analysis is shown in Figure 20. The RTL schematic obtained in Xilinx and Cadence are shown in Figure 21 and Figure 22 respectively. Figure 23 shows the floorplan of the proposed design using cadence. Fig. 20. Timing analysis Fig. 23. Floorplan of radix-10 matrix code using kogge stone adder in cadence tool. C. Comparison Results Different types of adders were implemented in radix- 10 matrix code to increase the performance. The comparison of these designs were made on the basis of area in terms of gate count, delay, number of LUTs and memory usage. The comparison is shown in Table 1. The results shows that radix-10 matrix code using kogge stone adder has the lowest delay compared to the others. Radix-10 matrix code with ripple carry adder shows highest delay. So kogge stone adder, a parallel prefix adder is the fastest adder with least delay. Hence we can optimize the design by using a kogge stone adder in place of adders. Thus the delay is reduced. TABLE 1. Comparison Of Area, Delay, Memory Usage Of Radix-10 Matrix Code With Different Types Of s Fig. 21. RTL Schematic using Xilinx ISE 14.7 Fig. 22. RTL Schematic of radix-10 matrix code using kogge stone adder in cadence tool. Types of adders used in radix-10 matrix code Gate count (Area) Gate delay Delay (in ns) Route delay Total delay Ripple carry adder ,10,545 Carry skip adder ,33,920 Carry select adder ,10,545 Carry look ahead adder ,01,322 Brent-kung adder ,01,335 Kogge stone adder ,01,328 VII. CONCLUSION Levels Of Logic No. of LUTs used Memory usage (in kb) A novel radix-10 matrix code was designed and synthesized. This protection code is used for multiple error detection and correction. This code uses a decoder and encoder units with fast adder. The proposed system gives maximum error correction capability. Performance comparison was made using different adders. Kogge stone adder which is a parallel prefix adder is the high speed 255

8 adder that can improve the performance of this radix-10 matrix code. Future work can be done for reducing the redundant bits and increase the reliability of the memory. VIII. REFERENCES [1] Jing Guo, Liyi Xiao, Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code, IEEE Trans. VLSI Systems., vol.22,no.1, Jan [2] D. Radaelli, H. Puchner, S. Wong, and S. Daniel, Investigation multi-bit upsets in a 150 nm technology SRAM device, IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp , Dec DEEPA N R received the Bachelor s degree in Electronics and communication engineering in 2005, and MTech in VLSI &Embedded system from M.G.University, Kerala, India, in 2012.She has been working as Assistant professor at FISAT, Angamaly, Mookkannoor, Ernakulam, and Kerala, India. [3] R.W. Hamming, Error correcting and error detecting codes,in Bell Sys. Tech. Journal, vol 29, pp , April [4] C. Argyrides, D. K. Pradhan, and T. Kocak, Matrix codes for reliable and cost efficient memory chips, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 3, pp , Mar [5] P. Reviriego and J. A. Maestro, Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS, ACM Trans. Design Autom. Electron. Syst., vol. 14, no. 1, pp. 18:1 18:10, Jan [6] Sudheer Kumar Yezerla, B Rajendra Naik, Design and Estimation of delay, power and area for Parallel prefix adders, Proceedings of 2014 RAECS UIET Panjab University Chandigarh. [7] Adilakshmi Siliveru, M.Bharathi, Design of Kogge-Stone and Brent-Kung adders using Degenerate Pass Transistor Logic, International Journal of Emerging Science and Engineering (IJESE), Volume-1, Issue-4, February About Authors: GRACE ABRAHAM received the B.Tech degree in Electronics and Communication Engineering in 2014, from M.G University, Sree Narayana Mangalam Institute Of Management And Technology, Ernakulam and currently pursuing M.Tech in VLSI & Embedded system from M.G.University, Kerala, FISAT, Mookkannoor, Angamaly Ernakulam, and Kerala, India. NIMMY M PHILIP received the Bachelor s degree in Electronics and communication engineering in 1999, from Calicut University, Kerala, India and MTech in VLSI &Embedded system from M.G.University, Kerala, India, in She has been working as Assistant professor at FISAT, Angamaly, Mookkannoor, Ernakulam, and Kerala, India

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