Lab 2: Combinational Circuits Design

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1 Lab : Combinational Circuits Design PURPOSE: The purpose of this laboratory assignment is to investigate the design of combinational circuits using SSI circuits and basic logic gates such as ANDs, ORs, NOTs, NANDs, and EXORs. The combinational circuits being implemented in this lab are a BCD-to- segment decoder, a Binaryto-BCD converter, and a -bit Binary Adder. Upon completion of this lab you should be able to: Understand the use of Boolean laws in implementing real circuits. Understand the behavior of a display decoder. Understand the behavior of a combinational code converter Understand the behavior of a binary adder. Understand the concept of time multiplexing. Appreciate the concept of design decomposition and integration. MATERIALS: ICs: (3-input AND), 3 (-input OR), 0 (-input NOT), 00 (-input NAND), 83 (-bit Adder with fast Carry), 5 (quad -to- Multiplexer ), and (BCD-to- Segment Decoder). DC Power Supply DVM (Digital Volt Meter or Multimeter) Function Generator Oscilloscope

2 PRELAB P. BCD-to- Segment Decoder A BCD to seven-segment decoder is to be designed to create the numeric digit display patterns shown in Figure. 0 8 g f a b common e d common 3 c dp 5 Figure. Pin diagram of the -segment display. The display element is of the common anode variety. The decoder receives its BCD input on lines D 3 D D D 0, D 3 being the MSB a) Complete the following truth table of the decoder.

3 D3 D D D0 Seg_a Seg_b Seg_c Seg_d Seg_e Seg_f Seg_g Binary code of any number > (Display OFF) b) Use Boolean laws to find the minimum expressions of all the outputs. P. Binary-to-BCD Decoder A Binary-to-BCD code converter is a combinational circuit that takes a binary code of n bits and convert it into a BCD code of m digits. We want to design a -bit Binary-to-BCD code converter. The block diagram of the circuit is given as follows (Figure ): 3

4 BCD_3 A (MSB) BCD_ BCD_ B BCD_0 C -bit Binary-to BCD Code Converter BCD0_3 D (LSB) BCD0- BCD0_ BCD0_ (Always 0, not to be considered for a -bit input code converter) Figure. Logic block diagram of a Binary-to-BCD Code Converter.

5 a) Complete the following truth table of the code converter INPUTS OUTPUTS # Binary Code BCD BCD0 Numb. A B C D BCD_ 3 BCD_ BCD_ BCD_ 0 BCD0_ 3 BCD0_ BCD0_ BCD0_ b) Because BCD_3 = BCD_ = BCD_ = 0, we consider them as non existing (for the time being), therefore the number of outputs is reduced to 5. Use Boolean laws to find the minimum expressions of BCD0_3, BCD0_, BCD0_, and BCD0_. The following example shows how to derive the expression of BCD_0. i.e. BCD_0 = m0 + m + m + m3 + m + m5 = AB CD + AB CD + ABC D + ABC D + ABCD + ABCD = AB C(D + D ) + ABC (D + D ) + ABC(D + D ) = AB C + ABC + ABC = AB C + ABC + ABC + ABC (because ABC = ABC + ABC) = AC(B + B) + AB(C + C ) = AC + AB = A (B + C) The circuit implementation of BCD_0 using available logic gates is given below. 5

6 B UA C 3 3 UA A 3 BCD_0 R.K (optional) +5V Figure 3. Logic circuit of one of the output of the BCD-to- Segment Code Converter. Experiment EXPERIMENTS The LS is an IC that does the BCD-to- segment conversion. The connection diagram for the LS is shown in Figure, and the connection diagram for the -segment display is shown in Figure. Because of the way the -segment display is designed, a current-limiting resistor must be inserted between each output from the LS and the corresponding input of the display. Since handling so many individual resistors is unwieldy, you will use a R resistor network device. This device consists simply of eight resistors in a single package, as shown in Figure 5. Figure. Pin diagram of the LS BCD to -segment decoder integrated circuit.

7 Figure 5. Pin diagram of the R resistor network (the value of each resistor is 0 Ohms). Completely build, test, and demonstrate the operation of the decoder to the lab instructor (figure ) 0 8, 3 Figure. Decoder and display circuit. Experiment We want to implement the -bit binary to BCD code converter. For this purpose you have to use the results of your Prelab P. a) Implement the logic circuits of outputs BCD_0 BCD0_3, BCD0_, BCD0_, and BCD0_ using logic basic gates (0, 3,, 00, etc.). Organize them in a manner that takes less space on the proto board. b) For testing purposes the output of the code converter is to be connected to the circuit of experiment (figure ). Completely build, test, and demonstrate the operation of this circuit to the lab instructor.

8 B A BCD_0 0 8, 3 -bit Binary-to-BCD Code Converter C 8, 3 D BCD0_3 BCD0_ BCD0_ BCD0_0 0 Figure. Binary-to-BCD Coder Test Circuit. Experiment 3 One of the limitation of the circuit of figure is the fact that two separate modules for BCD display are needed. A correct design will consist in reducing the number of BCD display module. Seven-segment displays are now widely used in almost all microprocessor-based instruments. A single seven-segment display can display the digits from 0 to and the hex digits A to F. Each display is composed of seven LEDs that are arranged in a way to allow the display of different digits using different combinations of LEDs (figure ). Since the display is composed of LEDs, which need high current to drive them, power consumption is very critical. Consider a panel with displays and the number to be displayed is 88. Each LED needs 0 ma. So we need a current of 0xx = 80 ma. That s a lot of current compared to the current consumed by the microprocessor. Another problem is the number of components and output bits that are needed to connect the displays to the processor. We need at least x = 8 resistors and output bits for the displays. Is there a solution for these problems? Yes, there is, it s called MULTIPLEXING! This connection scheme creates a multiplexed display, where driving the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession can create the appearance of a fourdigit display. Each of the four digits will appear bright and continuously illuminated if the digit enable signals are driven low once every to ms (for a refresh frequency of KHz to 0Hz). For example, in a 8

9 0Hz refresh scheme, each digit would be illuminated for one quarter of the refresh cycle, or ms. The controller must assure that the correct cathode pattern is present when the corresponding anode signal is driven (figure 8). Refresh Period = ms to ms Cathodes BCD0 BCD Fig. 8. Time Multiplexing of the display.

10 a 8, Multiplexer 5 5V 8, 3 a BCD0_3 BCD0_ BCD0_ BCD0_0 BCD_0 0 From the Binary-to-BCD Code Converter (Fig. ) 0 o a Square-Wave Signal Generator a Figure. Time-multiplexing circuit of the -bit Binary-to-BCD a) Completely build, test, and demonstrate the operation of this circuit to the lab instructor. The frequency of the square must be set to 800 Hz. b) What happens on the display when the frequency of the square wave signal is in the range of 0 to 0 Hz or.5 khz to 00 khz? Experiment We want evaluate the behavior of a -bit Adder IC (83). The circuit to be implemented combines the circuit of figures 0 and. 0

11 A, B, C,and D are the inputs of the Binary -to-bcd Code converter Carry Out A B C D 5V 0 Ohms LED 5 5 C Sum Sum3 Sum Sum Vcc GND 3 C0 A A3 A A B B3 B B bit input A -bit input B Figure 0. -bit Adder to be connected to the circuit diagram of figure. a) Implement the circuit on your proto board. Complete the following table by changing the values of A and B. Value of A Value of B Display Display Led status b) What are the status of the display and the LED when the numbers present at A and B have their sum greater than 5 (for instance A = 0 and B = 0)? c) In order to have a correct representation of the addition of -bit numbers we have to consider C as an output (MSB of the Adder) with the other outputs A, B, C, and D (LSB). Show how the circuit of figure can be modified to accommodate this new configuration. LAB REPORT Use the template lab report of Lab.

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two