Lab 2 Revisited Exercise

Transcription

1 Lab 2 Revisited Exercise +15V 100k 1K 2N2222 Wire up led display Note the ground leads LED orientation IAP 2008 Lecture 3 1

2 Comparator, Oscillator k 2 V- 7 6 Vin 3 V+ 4 V o Notice that power connections are shown; bypass capacitors included for power supply filtering. All voltage measurements are referenced to ground IAP 2008 Lecture 3 2

3 Op-Amps Inverting Amplifier Null Adjustment Integrator R2 10k C R1 V- Vin 1k V- R1 V- Vin V+ V o V+ 1 5 V o Vin V+ V o 10k v R2 vin = vo = dt R1 RC o v in -15V For clarity, power connections and bypass capacitors not shown IAP 2008 Lecture 3 3

4 Lab Exercise - Schmitt Trigger Vin V- V o Schmitt trigger have different triggers points for rising edge and falling edge. V+ R2 R1 Can be used to reduce false triggering This is NOT a negative feedback circuit IAP 2008 Lecture 3 4

5 Notes IC power supply connections generally not drawn. All integrated circuits need power! Use standard color coded wires to avoid confusion. Potentiometer internals IAP 2008 Lecture 3 5

6 Power Supplies, Voltage Regulators 3 terminal regulator Conventional Power Supply rectify (convert AC to DC) filter out the ripple regulate the voltage. 3 terminal IC regulator IAP 2008 Lecture 3 6

7 Wire Gauge Wire gauge: diameter is inversely proportional to the wire gauge number. Diameter increases as the wire gauge decreases. 2, 1, 0, 00, 000(3/0) up to 7/0. Resistance 22 gauge.0254 in 16 ohm/1000 feet 12 gauge.08 in 1.5 ohm/1000 feet High voltage AC used to reduce loss IAP 2008 Lecture 3 7

8 78XX Voltage Regulator +5V, +12V, +15V -5V, -12V, -15V Reprinted with permission of National Semiconductor Corporation IAP 2008 Lecture 3 8

9 7805 Circuit Reprinted with permission of National Semiconductor Corporation IAP 2008 Lecture 3 9

10 Zener Diode 4.7k Zener diodes will maintain a fixed voltage by breaking down at a predefined voltage (zener voltage). Lab exercise Wire up the above circuit with a 1N752A (5.6V) zener. Set the FG for a 0-10V ramp. Display the output of the FG and the voltage across the zener on the oscilloscope. Describe what is happening IAP 2008 Lecture 3 10

11 Adjustable Voltage Source +15V 270Ω 0.1uf 1N758 10v 10K V+ V- V o IAP 2008 Lecture 3 11

12 Adjustable Voltage Power Supply +15V 270Ω 1N uf 10K V+ V o 1uf 10v V IAP 2008 Lecture 3 12

13 LM317 Three Terminator Adjustable Voltage Regulator Reprinted with permission of National Semiconductor Corporation. First 3 terminal adjustable voltage regulator Voltage output range Short circuit protected Thermal shutdown IAP 2008 Lecture 3 13

14 LM317 Reprinted with permission of National Semiconductor Corporation IAP 2008 Lecture 3 14

15 Buck Converters Linear power supplies are very inefficient Power dissipated by regulating element Buck converters operating in switching mode (on/off) IAP 2008 Lecture 3 15

16 555 Timers Simple, versatile, low cost IC for timing applications: oscillators, one-shot pulse generator, pulse width modulator, missing pulse detector Circuit: two comparators, flip flop, resistor divider and a discharge transistor. Threshold Control Voltage Trigger V CC 8 5k 5k 5k 1 Gnd + Comp _ A + Comp _ B R S Flip Flop Q Inhibit/ Reset 4 Reset 7 3 Discharge Output Figure by MIT OpenCourseWare IAP 2008 Lecture 3 16

17 555 Block Diagram V CC 8 Threshold Control Voltage Trigger k 5k 5k + Comp _ A + Comp _ B R S Flip Flop Q Inhibit/ Reset 7 3 Discharge Output 1 Gnd 4 Reset Figure by MIT OpenCourseWare. S R Reset Output last state low high high NA NA 0 low IAP 2008 Lecture 3 17

18 RC Equation V s = 5 V V s = 5 V Switch is closed t<0 R Switch opens t>0 V s = V R + V C C Vc V s = i R R+ V c i R = V s = dv dt c RC + V c C dv dt c V c 5 1 e t = RC V c Vs 1 e t = RC IAP 2008 Lecture 3 18

19 Monostable Circuit V CC R a 555 or 1/2 556 Discharge Control voltage Threshold R Comp C R Flip flop Output Output Trigger Comp R Reset Figure by MIT OpenCourseWare, based on Philips Semiconductors datasheet. Reprinted with permission of National Semiconductor Corporation IAP 2008 Lecture 3 19

20 Oscillator (Astable) V CC R b RA Discharge Control voltage Threshold R Comp R Flip flop Output 3 Trigger 2 Comp R C 1 4 Reset Figure by MIT OpenCourseWare, based on Philips Semiconductors datasheet. Reprinted with permission of National Semiconductor Corporation IAP 2008 Lecture 3 20

21 Closet Light Timer Lab Exercise k reset 10k 555 output R trigger threshold discharge 1k 0.1uf control C uf Switch closed = door closed t on = 1.1RC IAP 2008 Lecture 3 21

22 Lab Exercise Wire up zener diode circuit Build variable voltage power supply Build variable current source Build 555 oscillator Build closet light timer IAP 2008 Lecture 3 22

23 Analog Circuit Summary 3 Terminal Regulators Zener Diodes Power Supplies 555 Timers & circuits IAP 2008 Lecture 3 23

24 Important Missing Links The real world is an analog world. However, computing is best performed via digital systems (i.e. the processing of data with 0 s and 1 s). Digital-Analog Conversion Analog-Digital Conversion IAP 2008 Lecture 3 24

25 Analog vs Digital Analog systems/devices work with information in a continuous stream: clock with hands, mercury thermometer, vinyl records, analog meters, calipers. Digital systems/devices work with information in a discontinuous stream (0,1): digital thermometer, digital meters, computers IAP 2008 Lecture 3 25

26 Music An Example CD s are digital systems that sample and stores audio data sampling rate: 44.1 khz data stored in 16 bit format; implies 2 16 = 65,536 possible output levels DVD Audio samples at kHz/24 bits Analog records have an infinite number of output levels IAP 2008 Lecture 3 26

27 D-A Conversion (DAC) Problem: take a digital signal and convert to an analog voltage: R-2R ladder > 1/16 * 5 volt > 2/16 * 5 volt > 3/16 * 5 volt > 14/16 * 5 volt > 15/16 * 5 volt Note that the outputs are at discrete levels not continuous! R R R R B3 + B2 + B1 + B V o R 2R 2R 2R 2R B o B 1 B 2 B IAP 2008 Lecture 3 27

28 Digital Circuits Real world analog signals have noise unavoidable. Digital circuits offers better noise immunity. Use voltage to represent 0 and 1 Avoid forbidden voltage zone. Make standards tighter for output than for inputs. Data (HCMOS family): 0 (low), 1 (high) Input voltage low: v Input voltage high: >2.0V Output low: <0.4v Output high: >3.98v IAP 2008 Lecture 3 28

29 Digital Circuits +5V HCMOS 1 (high) Output high: >3.98v output high range +3.98V Input voltage high: >2.0V input high range noise margin +2.0V Forbidden Zone HCMOS 0 (low) 0.7V Output low: <0.4v Input voltage low: v noise margin output low range 0.4V input low rage IAP 2008 Lecture 3 29

30 Power Requirements The following power supplies are common for analog and digital circuits: +5v for digital circuits, +15v, -15v for analog, -5v, +12v, -12v also used Other voltages generally derived IAP 2008 Lecture 3 30

31 Boolean Algebra A B = A & B A = Inverse of A A B = Inverse of [A&B] DeMorgan's Law A B = A + B A + B = A & B IAP 2008 Lecture 3 31

32 Digital System Implementation Start with AND, OR, NOR, NAND gates and add more complex building blocks: registers, counters, shift registers, multiplexers. Wire up design. High manufacturing cost, low fix costs. Examples 74LS, 74HC series IC For volume production, move to PALs, FPGAs, ASICs. Low manufacturing cost, high fix costs IAP 2008 Lecture 3 32

33 Basic Gates Circle indicates inversion IAP 2008 Lecture 3 33

34 74LS00 NAND Gate Dual-In-Line Package V CC B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 GND This device contains four independent gates each of which performs the logic NAND function. Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS00 datasheet IAP 2008 Lecture 3 34

35 74LS02 NOR Gate Dual-In-Line Package V CC Y4 B4 A4 Y3 B3 A Y1 A1 B1 Y2 A2 B2 GND This device contains four independent gates each of which performs the logic NOR function. Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS02 datasheet IAP 2008 Lecture 3 35

36 74LS08 AND Gate Dual-In-Line Package VCC B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 GND This device contains four independent gates each of which performs the logic AND function. Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS08 datasheet IAP 2008 Lecture 3 36

37 Building Logic From basic gates, we can build other functions: Exclusive OR Gate X Y Z X Y Z X Y Z IAP 2008 Lecture 3 37

38 74LS86 Exclusive OR V CC Truth Table GND In Out A L L H H B L H L H Z L H H L Figure by MIT OpenCourseWare, based on Motorola datasheet IAP 2008 Lecture 3 38