Datapath Components. Control vs. Datapath, Registers, Adders (Binary Addition) Copyright (c) 2012 Sean Key

Transcription

1 atapath Components Control vs. atapath, Registers, Adders (Binary Addition) Copyright (c) 2012 ean Key

2 ata vs. Control Most digital circuits can be divided into two parts Control Circuitry to control the overall operation of the circuit atapath The circuit components through which the real data of the circuit passes I.E. In a digital TV signal decoder, the input signal would pass from the antenna through the data path to the display. We will build a library of components to use in the datapath

3 chematics vs. Block iagrams A schematic is a drawing of a circuit that shows a high level of detail in describing the low-level operations of a circuit The circuits we ve seen to far would be described as schematics A block diagram is a different graphical method of describing a circuit, but it omits many of the low-level details to make the design easier to understand from a more abstract viewpoint. Many more complex systems are documented using block diagrams As we study data path components, we will see many standard block symbols that are used in block diagrams.

4 ata Bus ata generally consists of multiple bits. Requires large numbers of lines to connect components. Buses are groupings of related wires, used to simplify wiring diagrams Buses have width, often referred to as N. i.e. if N = 4, the bus is 4 bits wide. Buses can be drawn many different ways. The two most common are shown to the right. single bit single bit bus N N bus[n:0]

5 Block iagram Example FTI FT245R UB to parallel interface chip block diagram obtained from the chip's datasheet

6 Registers Registers can be much more complex than what we ve studied so far. We will study three useful types of registers: Parallel Load Register hift Register Rotate Register Multifunction Register

7 Parallel-Load Register The basic register that we studied previously loaded a new value on each clock tick. Parallel-Load Registers add a load signal New values are only loaded on a clock tick when load is asserted. Load clk I3 I2 Q _FF Q _FF Q _FF Q _FF Q3 Q2 Q1 Q0 [3:0] Q[3:0] Load [7:0] 4-bit parallel load register

8 hift Register hift registers are designed to allow the bit contents of the register to be shifted to the left or the right hifting means that a bit is moved by one bit position. Bits can be shifted to the left, right, or both -- depending on the implementation We will see how to shift both left and right in a later example shr_in shr Q _FF Q clk Q3 4-bit shift right register _FF Q _FF Q2 Q1 Q _FF Q0

9 Rotate Register Rotate registers are special cases of shift registers The bit that is being shifted out of the register is fed back into the other end of the register. shr clk Q _FF Q3 Q _FF Q2 Q _FF Q1 Q _FF Q0 4-bit rotate right register

10 Multifunction Register ifferent register functions can be merged into a single register I3 I2 shl_out shr_in shr_out shl_in s1 s0 I2 1 mux_4_1 0 I3 I2 1 mux_4_1 0 I3 I2 1 mux_4_1 0 I3 I2 1 mux_4_1 0 I3 Q _FF Q _FF Q _FF Q _FF clk Q3 Q2 Q1 Q0 How do the select inputs (s0, s1) change the functionality of the register? How can we make this into a rotate register?

11 Adders An adder adds two binary numbers together. Adders have a width, N, that defines how many bits they operate on. An adder cannot operate correctly on a number that required more bits that the width of the adder Before seeing how to design an adder, lets examine how to add binary numbers!

12 Binary Addition Binary addition is just like decimal addition, except a carry happens when the result of adding two bits is two (10 2 ) or greater. Binary addition is restricted to the number of bits available to the adder (the adder width, N) The carry from the result of the addition of the two most significant bits is called the carry-out bit

13 Binary Addition Examples Using a 4-bit adder, add 7 and 2 Using a 8-bit adder, add 17 and

14 Overflow Overflow occurs when the result of a mathematical operation exceeds the range of the available number of bits. For simple unsigned binary arithmetic, overflow can be detected by watching the carry-out bit. 1 Overflow 0 No overflow

15 Overflow Examples Indicate whether the following mathematical operations will cause overflow:

16 Adder Circuit Adders aren t generally designed using two level logic from a truth table Truth tables are too large i.e., a 16-bit adder would have over 4 billion rows! Too many gates/transistors are required to be efficient Adders are designed as iterative circuits Many small identical components are connected together to form a larger circuit This is known as a ripple-carry adder because carry bits ripple from one component to the next.

17 Half Adder Adds two bits (a & b) Generates a sum (s) and a carry out (co) a +b co s a b co s co = a b s = a b a b a b co HA s AN XOR co s Note: Half adders aren t very useful on their own because they cannot work on multi-bit values. They can be used as components in larger circuits that do work on multi-bit values.

18 Full Adder Adds two bits (a & b) with a carry-in (ci) Generates a sum (s) and a carry out (co) ci a +b co s a b ci co s co = a b + b ci + a ci s = a b ci a b ci AN AN AN XOR a b co FA ci s OR co s

19 4-bit Carry-Ripple Adder 4 Full Adders can be connected together to create a 4-bit adder. Multiple 4-bit carry-ripple adders can be connected together to create larger adders. a3 b3 a2 b2 a1 b1 a0 b0 co a b co FA ci s a b co FA ci s a b co FA ci s a b co FA ci s ci s3 s2 s1 s0 This is a slow circuit because we must wait for the carries to ripple from one FA to the next. Question: What should the value of ci be for the ripple-carry adder that contains the LB?

20 Ripple-Carry Timing Issues Ripple-carry circuits have to major timing issues: 1. They are slow because we have to wait until the carries to propagate through each FA before the output is valid. 2. purious output values are generated while the carries propagate, which can cause glitches. Example: how how the addition of 0111 and 0001 propagate through a ripple-carry adder. If all gates have 2ns delays, how long does it take for the output to be valid?