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1 SKP Engineering College Tiruvannamalai A Course Material on Digital Logic Circuits By A.Vigneswaran Assistant Professor Electronics and Communication Engineering Department Electronics and Communication Engineering Department 1 Digital Logic Circuits

2 Quality Certificate This is to Certify that the Electronic Study Material Subject Code: EE6301 Subject Name: Digital Logic Circuits Year/Sem: II /III Being prepared by me and it meets the knowledge requirement of the University curriculum. Signature of the Author Name: A.Vigneswaran Designation: Assistant Professor This is to certify that the course material being prepared by Mr.A.Vigneswaran is of the adequate quality. He has referred more than five books and one among them is from abroad author. Signature of HD Name: Seal: Signature of the Principal Name: Dr.V.Subramania Bharathi Seal: Electronics and Communication Engineering Department 2 Digital Logic Circuits

3 EE6301 DIGITAL LOGIC CIRCUITS OBJECTIVES: LT P C To study various number systems, simplify the logical expressions using Boolean functions To study implementation of combinational circuits To design various synchronous and asynchronous circuits. To introduce asynchronous sequential circuits and PLCs To introduce digital simulation for development of application oriented logic circuits. UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 9 Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code0- Digital Logic Families,comparison of RTL, DTL, TTL, ECL and MOS families -operation,characteristics of digital logic family. UNIT II COMBINATIONAL CIRCUITS 9 Combinational logic - representation of logic functions-sop and POS forms, K-map representationsminimization using K maps - simplification and implementation of combinational logic multiplexers and demultiplexers - code converters, adders, subtractors. UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 9 Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters -asynchronous and synchronous type - Modulo counters - Shift registers - design of synchronous sequential circuits Moore and Melay models- Counters, state diagram; state reduction; state assignment. UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES 9 Asynchronous sequential logic circuits-transition table, flow table-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuitsintroduction to Programmable Logic Devices: PROM PLA PAL. Electronics and Communication Engineering Department 3 Digital Logic Circuits

4 UNIT V VHDL 9 RTL Design combinational logic Sequential circuit Operators Introduction to Packages Subprograms Test bench. (Simulation /Tutorial Examples: adders, counters, flipflops, FSM,Multiplexers /Demultiplexers). TOTAL (L:45+T:15): 60 PERIODS OUTCOMES: Ability to understand and analyse, linear and digital electronic circuits. TEXT BOOKS: 1. Raj Kamal, Digital systems-principles and Design, Pearson Education 2nd edition, M. Morris Mano, Digital Design with an introduction to the VHDL, Pearson Education, Comer Digital Logic & State Machine Design, Oxford, REFERENCES: 1. Mandal Digital Electronics Principles & Application, McGraw Hill Edu, William Keitz, Digital Electronics-A Practical Approach with VHDL,Pearson, Floyd and Jain, Digital Fundamentals, 8th edition, Pearson Education, Anand Kumar, Fundamentals of Digital Circuits,PHI, Charles H.Roth,Jr,Lizy Lizy Kurian John, Digital System Design using VHDL, 6. John M.Yarbrough, Digital Logic, Application & Design, Thomson, Gaganpreet Kaur, VHDL Basics to Programming, Pearson, Botros, HDL Programming Fundamental, VHDL& Verilog, Cengage, Electronics and Communication Engineering Department 4 Digital Logic Circuits

5 CONTENTS S.No Particulars Page 1 Unit I 6 2 Unit II 26 3 Unit III 59 4 Unit IV 69 5 Unit V 75 Electronics and Communication Engineering Department 5 Digital Logic Circuits

6 Unit I Number Systems and Digital Logic Families Part A 1. Determine (377) 10 in Octal and Hexadecimal equivalent. [CO1-L2] (377) 10 = (571) 10 (377) 10 = (179) Convert : (a) (475.25) 8 to its decimal equivalent (b) (549.B4) 16 to its binary equivalent (a) (475.25) 8 = ( ) 10 (b) (549.B4) 16 = ( ) 2 3. What is the need of number conversions in digital system? [CO1-L1] The need of number conversions in digital system is essential to perform basic mathematical calculations. It finds more importance in digital computers and microprocessor based control systems. 4. Classify the binary codes. [CO1-L2] Weighted codes Non-weighted codes Alphanumeric codes Cyclic codes Error detection and correction codes. Electronics and Communication Engineering Department 6 Digital Logic Circuits

7 5. What are weighted binary codes? [CO1-L1] A code which consists of bit weightage for each digit present in the binary code is called weighted binary code. Example : 8421 code and 2421 code. 6. What are non-weighted binary codes? [CO1-L1] Non-weighted binary codes are not having any weightage for the digits present in binary code. Example: Gray code and Excess-3 code. 7. What is gray code? Why it is called as reflective code? [CO1-L1] A gray code is an un-weighted binary code. The four bit gray code can be used to represent the decimal number from 0 to 15. In this representation the last and first entry of gray code consequently differs only in one bit position (MSB bit). So this is also called reflective code. 8. List the most widely used alphanumeric codes? [CO1-L1] ASCII - American Standard Code for Information Interchange EBCDIC -Extended Binary Coded Decimal Interchange Code 9. What is BCD code? [CO1-L1] BCD stands for Binary Coded Decimal. The BCD code represents the number 0 to 9 with the binary representation 0000 to The decimal numbers are directly represented with the weightages of 8421 in BCD code. 10. What is an unit distance code? Give an example. [CO1-L1] An unweighted code that changes at only one digit position when going from one number to the next in a consecutive sequence of numbers. Example: Gray code. Electronics and Communication Engineering Department 7 Digital Logic Circuits

8 11. Express a 15 bit Hamming code in general. [CO1-L3] To transmit eleven data bits, four parity bits located at positions and 2 3 from left are added to make a 15 bit code word which is then transmitted. The word format would be as shown below: P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12 D13 D14 D15 where the D bits are the data bits and the P bits are the parity bits. 12. Define parity bit. [CO1-L1] A parity bit is a single bit added to a binary data transmission used to indicate if whether the 0's and 1's within that data transmission is an even or odd number. The parity bit is used in parity error checking to find errors that may occur during data transmission 13. What is error detection and error correction code? [CO1-L1] Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. To avoid this, we use error-detecting codes which are additional data added to a given digital message to help us detect if an error occurred during transmission of the message. A simple example of error-detecting code is parity check. Along with error-detecting code, we can also pass some data to figure out the original message from the corrupt message that we received. This type of code is called an error-correcting code. Error-correcting codes also deploy the same strategy as error-detecting codes but additionally, such codes also detect the exact location of the corrupt bit. Electronics and Communication Engineering Department 8 Digital Logic Circuits

9 14. What is hamming code? State its uses. [CO1-L1] Hamming code is an error-detecting and error-correcting binary code, used in data transmission, that can detect all single- and double-bit errors and correct all single-bit errors. A Hamming code satisfies the relation 2 m n +1, where n is the total number of bits in the block, k is the number of information bits in the block, and m is the number of check bits in the block, where m = n- k. 15. Define fan-in and fan-out. [CO1-L1] Fan In: The fan-in defined as the maximum number of inputs that a logic gate can accept. If number of input exceeds, the output will be undefined or incorrect. Fan Out: The fan-out is defined as the maximum number of inputs (load) that can be connected to the output of a gate without degrading the normal operation. Fan Out is calculated from the amount of current available in the output of a gate and the amount of current needed in each input of the connecting gate 16. Define propagation delay. [CO1-L1] The average transition time delay taken by the device to change the binary signal of output for the response of change in input is called propagation delay. 17. Define rise time and fall time. [CO1-L1] Rise time is the time required to switch from 10% of voltage level to 90% of voltage level. Fall time is the time required to switch from 90% of voltage level to 10% of voltage level. 18. What are the types of TTL logic? [CO1-L1] (i) Open collector output (ii) Totem-pole output and (iii) Tri-state output Electronics and Communication Engineering Department 9 Digital Logic Circuits

10 19.What is the significance of high impedance state in tri-state gates? The third state in a tri-state gate is a high impedance state. The high impedance state behaves like an open circuit, which means that the output appears to be disconnected and the circuit has no logic significance. 20. What is totem output? [CO1-L1] In TTL gate, the transistor Q4 sits upon Q3. Such a configuration is called totem pole and it has low output impedance. Hence output voltage can change quickly from one state ot the other due to rapidly charging of stray capacitance. So propogation delay is low in totem-output. Electronics and Communication Engineering Department 10 Digital Logic Circuits

11 Part B 1. List the different types of number system and write its radix. [CO1-H1] A number system allows for collection of digits to have an integer and a fractional part separated by a radix point. N= [ Integer part. Fractional part] The radix or base of a number system specifies the actual number of digits included in the particular system. Types of Number systems Types of Number systems : 1. Decimal number system 2. Binary number system 3. Octal number system 4. Hexadecimal number system Radix size Allowable number set (Digits) 2 (Binary) 0,1 8 (Octal) 0,1,2,3,4,5,6,7 10 (Decimal) 0,1,2,3,4,5,6,7,8,9 16 (Hexadecimal) 0,1,2,3,4,5,6,7,8,9, A,B,C,D,E,F Representation of various number systems with example Binary : (101010) 2, ( ) 2 Octal : (435) 7, (67.456) 8 Decimal : (67.789) 10 Hexadecimal : (A4.F3) Explain the classification of binary codes with examples. [CO1-L3] Electronics and Communication Engineering Department 11 Digital Logic Circuits

12 In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said that the number, letter or word is being encoded. The group of symbols is called as a code. The digital data is represented, stored and transmitted as group of binary bits. This group is also called as binary code. The binary code is represented by the number as well as alphanumeric letter. Advantages of Binary Code Following is the list of advantages that binary code offers. Binary codes are suitable for the computer applications. Binary codes are suitable for the digital communications. Binary codes make the analysis and designing of digital circuits if we use the binary codes. Since only 0 & 1 are being used, implementation becomes easy. Classification of binary codes The codes are broadly categorized into following four categories. a) Weighted Codes b) Non-Weighted Codes c) Binary Coded Decimal Code d) Alphanumeric Codes e) Error Detecting Codes f) Error Correcting Codes (a) Weighted Codes Weighted binary codes are those binary codes which obey the positional weight principle. Each position of the number represents a specific weight. Several systems of the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits. (b) Non-Weighted Codes Electronics and Communication Engineering Department 12 Digital Logic Circuits

13 In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes are Excess-3 code and Gray code. Excess-3 code The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or (3)10 to each code word in The excess-3 codes are obtained as follows Gray Code It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that, only one bit will change each time the decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation. Electronics and Communication Engineering Department 13 Digital Logic Circuits

14 Application of Gray code Gray code is popularly used in the shaft position encoders. A shaft position encoder produces a code word which represents the angular position of the shaft. (c) Binary Coded Decimal (BCD) code In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express each of the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e to 1111 are invalid in BCD. Advantages of BCD Codes It is very similar to decimal system. We need to remember binary equivalent of decimal numbers 0 to 9 only. Disadvantages of BCD Codes The addition and subtraction of BCD have different rules. The BCD arithmetic is little more complicated. BCD needs more number of bits than binary to represent the decimal number. So BCD is less efficient than binary. (d) Alphanumeric codes A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But this is not enough for communication between two computers because there we need many more symbols for communication. These symbols are required to represent 26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols. The alphanumeric codes are the codes that represent numbers and alphabetic characters. Mostly such codes also represent other characters such as symbol and various instructions necessary for conveying information. An alphanumeric code should Electronics and Communication Engineering Department 14 Digital Logic Circuits

15 at least represent 10 digits and 26 letters of alphabet i.e. total 36 items. The following three alphanumeric codes are very commonly used for the data representation. American Standard Code for Information Interchange (ASCII). Extended Binary Coded Decimal Interchange Code (EBCDIC). Five bit Baudot Code. ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. ASCII code is more commonly used worldwide while EBCDIC is used primarily in large IBM computers. 3. Explain error detection and correction codes. [CO1-H1] (i) Error Detecting Codes Error is a condition when the output information does not match with the input information. During transmission, digital signals suffer from noise that can introduce errors in the binary bits travelling from one system to other. That means a 0 bit may change to 1 or a 1 bit may change to 0. Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. To avoid this, we use error-detecting codes which are additional data added to a given digital message to help us detect if an error occurred during transmission of the message. A simple example of error-detecting code is parity check. (ii) Error-Correcting codes Along with error-detecting code, we can also pass some data to figure out the original message from the corrupt message that we received. This type of code is called an error-correcting code. Error-correcting codes also deploy the same strategy as errordetecting codes but additionally, such codes also detect the exact location of the corrupt bit. In error-correcting codes, parity check has a simple way to detect errors along with a sophisticated mechanism to determine the corrupt bit location. Once the corrupt bit is located, its value is reverted (from 0 to 1 or 1 to 0) to get the original message. Electronics and Communication Engineering Department 15 Digital Logic Circuits

16 4. How to Detect and Correct Errors? [CO1-H1] To detect and correct the errors, additional bits are added to the data bits at the time of transmission. The additional bits are called parity bits. They allow detection or correction of the errors. The data bits along with the parity bits form a code word. Parity Checking of Error Detection It is the simplest technique for detecting and correcting errors. The MSB of an 8-bits word is used as the parity bit and the remaining 7 bits are used as data or message bits. The parity of 8-bits transmitted word can be either even parity or odd parity. Even parity -- Even parity means the number of 1's in the given word including the parity bit should be even (2,4,6,...). Odd parity -- Odd parity means the number of 1's in the given word including the parity bit should be odd (1,3,5,...). Use of Parity Bit The parity bit can be set to 0 and 1 depending on the type of the parity required. For even parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is even. Shown in fig. (a). For odd parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is odd. Shown in fig. (b). Electronics and Communication Engineering Department 16 Digital Logic Circuits

17 5. How Does Error Detection Take Place? [CO1-H1] Parity checking at the receiver can detect the presence of an error if the parity of the receiver signal is different from the expected parity. That means, if it is known that the parity of the transmitted signal is always going to be "even" and if the received signal has an odd parity, then the receiver can conclude that the received signal is not correct. If an error is detected, then the receiver will ignore the received byte and request for retransmission of the same byte to the transmitter. Electronics and Communication Engineering Department 17 Digital Logic Circuits

18 6. Explain the characteristics of CMOS logic. [CO1-H1] i. Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pf load, the power dissipation is typically 10 nw per gate. ii. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 ns to 50 ns. iii. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20-40% longer than the propagation delays. iv. Noise immunity approaches 50% or 45% of the full logic swing. v. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high. vi. Voltage levels range from 0 to VDD where VDD is the supply voltage. A low level is anywhere between 0 and 1/3 VDD while a high level is between 2/3 VDD and VDD. Characteristics of TTL logic: Power dissipation is usually 10 mw per gate. Propagation delays are 10 ns when driving a 15 pf/400 ohm load. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1 CMOS compared to TTL: CMOS components are typically more expensive than TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design. Electronics and Communication Engineering Department 18 Digital Logic Circuits

19 Due to longer rise and fall times, the transmission of digital signals becomes simpler and less expensive with CMOS chips. CMOS components are more susceptible to damage from electrostatic discharge than TTL components. 7. Explain the characteristics of digital logic families. [CO1-H1] Fan-in The fan-in of a gate is the number of inputs connected to the gate without any degradation in the voltage levels. For example, an eight-input gate requires one Unit Load(UL) per input. Its fan-in is 8. This parameter determines the functional capabilities of a logic circuit. Fan-out : Fan-out is the maximum number of similar logic gates that a gate can drive without any degradation in voltage levels. The fan-out of a gate specifies the number of standard loads that can be connected to the output of the gate without degrading its normal operation. A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. Fan-out is calculated from the amount of current available in the output of a gate and the amount of current needed in each input of a gate. Totem output In TTL gate, the transistor Q4 sits upon Q3. Such a configuration is called totem pole and it has low output impedance. Hence output voltage can change quickly from one state ot the other due to rapidly charging of stray capacitance. So propogation delay is low in totem-output. Noise Margin: Noise is a term used to denote an undesirable signal that is superimposed upon the normal operating signal. The noise margin is the maximum noise voltage added to Electronics and Communication Engineering Department 19 Digital Logic Circuits

20 an input signal of a digital circuit that does not cause an undesirable change in the circuit s output. Noise margin is expressed in volts and represents the maximum noise signal that can be tolerated by the gate. 8. Explain TTL logic circuit and its Input & Output Voltage Levels. [CO1-H1] In standard TTL (transistor-transistor logic) IC's there is a pre-defined voltage range for the input and output voltage levels which define exactly what is a logic "1" level and what is a logic "0" level and these are shown below. There are a large variety of logic gate types in both the bipolar 7400 and the CMOS 4000 families of digital logic gates such as 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx, 74ACTxx etc, with each one having its own distinct advantages and disadvantages compared to the other. The exact switching voltage required to produce either a logic "0" or a logic "1" depends upon the specific logic group or family. However, when using a standard +5 volt supply any TTL voltage input between 2.0v and 5v is considered to be a logic "1" or "HIGH" while any voltage input below 0.8v is Electronics and Communication Engineering Department 20 Digital Logic Circuits

21 recognised as a logic "0" or "LOW". The voltage region in between these two voltage levels either as an input or as an output is called the Indeterminate Region and operating within this region may cause the logic gate to produce a false output. The CMOS 4000 logic family uses different levels of voltages compared to the TTL types as they are designed using field effect transistors, or FET's. In CMOS technology a logic "1" level operates between 3.0 and 18 volts and a logic "0" level is below 1.5 volts. Then from the above observations, we can define the ideal Digital Logic Gate as one that has a "LOW" level logic "0" of 0 volts (ground) and a "HIGH" level logic "1" of +5 volts and this can be demonstrated as: Ideal Digital Logic Voltage Levels Where the opening or closing of the switch produces either a logic level "1" or a logic level "0" with the resistor R being known as a "pull-up" resistor. 9.Draw the CMOS logic circuit for NOR gate and explain its operation.[co1-h1- Nov 2015] One of the main disadvantages of the TTL logic series is that the gates are based on bipolar transistor logic technology and as transistors are current operated devices, they consume large amounts of power from a fixed +5 volt power supply. Also, TTL bipolar Electronics and Communication Engineering Department 21 Digital Logic Circuits

22 transistor gates have a limited operating speed when switching from an "OFF" state to an "ON" state and vice-versa called the "gate" or "propagation delay". To overcome these limitations complementary MOS called "CMOS" logic gates using "Field Effect Transistors" or FET's were developed. As these gates use both P-channel and N-channel MOSFET's as their input device, at quiescent conditions with no switching, the power consumption of CMOS gates is almost zero, (1 to 2uA) making them ideal for use in low-power battery circuits and with switching speeds upwards of 100MHz for use in high frequency timing and computer circuits. 2-input NAND gate This CMOS gate example contains 3 N-channel MOSFET's, one for each input FET 1 and FET 2 and one for the output FET 3. When both the inputs A and B are at logic level "0", FET 1 and FET 2 are both switched "OFF" giving an output logic "1" from the source of FET 3. When one or both of the inputs are at logic level "1" current flows through the corresponding FET giving an output state at Q equivalent to logic "0", thus producing a NAND gate function. Electronics and Communication Engineering Department 22 Digital Logic Circuits

23 Improvements in the circuit design with regards to switching speed, low power consumption and improved propagation delays has resulted in the standard CMOS 4000 "CD" family of logic IC's being developed that complement the TTL range. As with the standard TTL digital logic gates, all the major digital logic gates and devices are available in the CMOS package such as the CD4011, a Quad 2-input NAND gate, or the CD4001, a Quad 2-input NOR gate along with all their sub-families. Like TTL logic, complementary MOS (CMOS) circuits take advantage of the fact that both N-channel and P-channel devices can be fabricated together on the same substrate material to form various logic functions. One of the main disadvantage with the CMOS range of IC's compared to their equivalent TTL types is that they are easily damaged by static electricity so extra care must be taken when handling these devices.also unlike TTL logic gates that operate on single +5V voltages for both their input and output levels, CMOS digital logic gates operate on a single supply voltage of between +3 and +18 volts. In the next tutorial about Digital Logic Gates, we will look at the digital Logic AND Gate function as used in both TTL and CMOS logic circuits as well as its Boolean Algebra definition and truth tables. 10.Explain "Tri-state Buffer" logic..[co1-h1] A Tri-state Buffer can be thought of as an input controlled switch which has an output that can be electronically turned "ON" or "OFF" by means of an external "Control" or "Enable" signal input. This control signal can be either a logic "0" or a logic "1" type signal resulting in the Tri-state Buffer being in one state allowing its output to operate normally giving either a logic "0" or logic "1" output. But when activated in the other state it disables or turns "OFF" its output producing an open circuit condition that is neither "High" or "low", but instead gives an output state of very high impedance, high-z, or more commonly Hi-Z. Then this type of device has two logic state inputs, "0" or a "1" but can produce three different output states, "0", "1" or Electronics and Communication Engineering Department 23 Digital Logic Circuits

24 "Hi-Z" which is why it is called a "3-state" device.there are two different types of Tristate Buffer, one whose output is controlled by an "Active-HIGH" control signal and the other which is controlled by an "Active-LOW" control signal, as shown below. Active "HIGH" Tri-state Buffer Symbol Truth Table Enable A Q Tri-state Buffer 0 0 Hi-Z 0 1 Hi-Z Read as Output = Input if Enable is equal to "1" An Active-high Tri-state Buffer is activated when a logic level "1" is applied to its "enable" control line and the data passes through from its input to its output. When the enable control line is at logic level "0", the buffer output is disabled and a high impedance condition, Hi-Z is present on the output. Active "LOW" Tri-state Buffer is shown below. Enable A Q Tri-state Buffer 1 0 Hi-Z 1 1 Hi-Z Read as Output = Input if Enable is NOT equal to "1" Electronics and Communication Engineering Department 24 Digital Logic Circuits

25 An Active-low Tri-state Buffer is the opposite to the above, and is activated when a logic level "0" is applied to its "enable" control line. The data passes through from its input to its output. When the enable control line is at logic level "1", the buffer output is disabled and a high impedance condition, Hi-Z is present on the output. Electronics and Communication Engineering Department 25 Digital Logic Circuits

26 Unit - II Combinational Circuits Part A 1. Write the POS representation of the following SOP function : [CO2-L2] F(x,y,z) = m (0,1,3,5,7) Answer: The POS function is written as F(x,y,z) = πm (2,4,6) (or) F(x,y,z) = (x+y +z) (x +y+z) (x +y +z) 2. Draw the logic diagram of EX-OR using NAND gates. [CO2-L2] 3. Define Minterm and Maxterm. [CO2-L1] Each individual term in standard SOP form is called minterm. Minterms are standard product.(and terms) Each individual term in standard POS form is called maxterm. Maxterms are standard sum.(or terms) Electronics and Communication Engineering Department 26 Digital Logic Circuits

27 4. What are Canonical form? [CO2-L1] Any Boolean function that is expressed as a sum of minterms or as a product of max terms is said to be in its canonical form.it mainly involves in two Boolean terms, minterms and maxterms. 5. Define SOP and POS. [CO2-L1] Sum of Products (SOP): The logical sum of two or more logical product terms is called a Sum of Products expression. It is basically an OR operation of AND operated variables. Example : AB + ABC + CDE Product of Sum (POS): A product of sums expression is a logical product of two or more logical sum terms. It is basically an AND operation of OR operated variables. Example : (A+B) * (A + B + C) * (C +D) 6. Enumerate some of the combinational circuits. [CO2-L3] Multiplexer, Decoder, Demultiplexer, Encoder, Magnitude comparator, Adder, Subtractor and Code converters are some of the combinational circuits. 7. State DeMorgan s Theorem. [CO2-L2] Theorem 1: The complement of a product is equal to the sum of the complements. The complement of a sum is equal to the product of the complements. 8. What are Don t care terms? [CO2-L1] In some logic circuits, certain input conditions never occur, therefore the corresponding never appears. In such cases, the output level is not defined and it can Electronics and Communication Engineering Department 27 Digital Logic Circuits

28 be either High or Low. These output levels are indicated by X or d in the truth table. These terms are called as don t care terms or don t care conditions. 9. What are the methods adopted to reduce Boolean function? [CO2-L1] (i) Minimization using Boolean theorems (ii) Karnaugh mapping (iii) Quine-McCluskey method (Tabulation method) 10. Define prime implicant. [CO2-L1] All the implicants of a function determined using a Karnaugh map are called prime implicants. 11. What is a multiplexer? [CO2-L1] A multiplexer (MUX) also called a data selector, is a combinational circuit with more than one input line, one output line and more than one selection line. A multiplexer selects binary information present on any one of the input lines, depending upon the logic status of the selection inputs and routes it to the output line. If there are n selection lines, then the number of maximum possible input lines is 2 n and the multiplexer is referred to as a 2 n -to-1multiplexer or 2 n 1 multiplexer. F 12. Give one application each for Multiplexer and Decoder. [CO2-L2] Application of Multiplexer: In telephone network, multiple audio signals are integrated on a single line for transmission with the help of multiplexers Application of Decoder: Used in code converters and for address decoding. Electronics and Communication Engineering Department 28 Digital Logic Circuits

29 13.Differentiate a decoder from a demultiplexer. [CO2-L2] Decoder Demultiplexer Converts binary information from n It receives information on a single input input lines to 2 n unique output lines. and transmits the same information over one of several (2 n ) output lines. There are no selection lines. The selection of specific output line is controlled by the value of selection line. 14. Realize the Boolean function using appropriate multiplexer. [CO2-L3] F (A, B, C) = (1, 2, 5, 7) 15. List few applications of Multiplexer. [CO2-L2] Data routing Logic function generator Control sequencer and Parallel to Serial converter Electronics and Communication Engineering Department 29 Digital Logic Circuits

30 16. Draw the logic diagram of a 4 line to 1 line Multiplexer[CO2-L1] 17. Draw the logic diagram of a 2 :1 Multiplexer[CO2-L1] 18.What is encoder? [CO2-L1] A encoder is a combinational circuit that has 2 n input lines and n output lines. Converts an active input signal into a coded output signal. No of outputs is less than the number of inputs Electronics and Communication Engineering Department 30 Digital Logic Circuits

31 19, What is priority encoder? [CO2-L1] A priority encoder is an encoder circuit in which if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 20. Design a half subtractor. [CO2-L1] 21. Write an expression for borrow and difference in a full subtractor circuit. [CO2-L2] Borrow = (or) = Difference = Electronics and Communication Engineering Department 31 Digital Logic Circuits

32 Part B 1. What is a combinational logic circuit? Explain with an example.[co2-h1] Circuits in which all outputs at any given time depend only on the inputs at that time are called combinational logic circuits. The outputs are functions only of the inputs Combinational circuits consist of input binary variables, logic gates and output binary variables. Examples for combinational circuits The output of combinational circuit at any instant of time, depends only on the levels present at input terminals. The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit. A combinational circuit can have an n number of inputs and m number of outputs. The three main ways of specifying the function of a combinational logic circuit are: 1. Boolean Algebra This forms the algebraic expression showing the operation of the logic circuit for each input variable either True or False that results in a logic 1 output. 2. Truth Table A truth table defines the function of a logic gate by providing a concise list that shows all the output states in tabular form for each possible combination of input variable that the gate could encounter. Electronics and Communication Engineering Department 32 Digital Logic Circuits

33 3. Logic Diagram This is a graphical representation of a logic circuit that shows the wiring and connections of each individual logic gate, represented by a specific graphical symbol, that implements the logic circuit. All three of these logic circuit representations are shown below. 2. Explain SOP AND POS FORMS.[CO2-H1] Sum of Products (SOP): The logical sum of two or more logical product terms is called a Sum of Products expression. It is basically an OR operation of AND operated variables. Example: AB + ABC + CDE Product of Sum (POS): A product of sums expression is a logical product of two or more logical sum terms. It is basically an AND operation of OR operated variables. Example : (A+B) * (A + B + C) * (C +D) The term "standard" here means that the expression consists exclusively of minterms (in the case of Standard SOP) or maxterms (in the case of Standard POS). Converting Boolean Expressions into SOP/POS Form Electronics and Communication Engineering Department 33 Digital Logic Circuits

34 The process of converting any Boolean expression into either POS or SOP form (canonical or otherwise) is very straightforward. To get the expression in SOP form, you simply distribute all AND operations over any OR operations and continue doing this as long as possible. When finished, you will have an expression in SOP form. If you want it in canonical form, then you simply expand each term as necessary. To get the expression in POS form, you simply distribute all OR operations over any AND operations and continue doing this as long as possible. When finished, you will have an expression in POS form. If you want it in canonical form, then you simply expand each term as necessary. 3. What are Minterms and Maxterms? [CO2-L1] Each individual term in standard SOP form is called minterm. Minterms are standard product.(and terms) Each individual term in standard POS form is called maxterm. Maxterms are standard sum.(or terms) 4. Write short notes on various K-MAP representations. [CO2-H1] Electronics and Communication Engineering Department 34 Digital Logic Circuits

35 A Karnaugh map provides a pictorial method of grouping together expressions with common factors and therefore eliminating unwanted variables. The Karnaugh map can also be described as a special arrangement of a truth table. The diagram below illustrates the correspondence between the Karnaugh map and the truth table for the general case of a two variable problem. The values inside the squares are copied from the output column of the truth table, therefore there is one square in the map for every row in the truth table. Around the edge of the Karnaugh map are the values of the two input variable. A is along the top and B is down the left hand side. The diagram below explains this: The values around the edge of the map can be thought of as coordinates. So as an example, the square on the top right hand corner of the map in the above diagram has coordinates A=1 and B=0. This square corresponds to the row in Electronics and Communication Engineering Department 35 Digital Logic Circuits

36 the truth table where A=1 and B=0 and F=1. Note that the value in the F column represents a particular function to which the Karnaugh map corresponds. If we have n variables then there would be 2 n min terms and hence 2 n number of blocks in the K-map and also min terms are arranged in their gray code order (not in binary order). 2-variable map and 3-variable map are shown below: Also there are minterms mentioned in the squares of the map Similarly we can have a K-map for 4 variables, 5 variables, 6 variables etc but we generally use only till 4 variables maps as higher maps are difficult to use. Now to simplify any expression we first convert the expression into its canonical form and then mark a 1 in the corresponding column of min terms present in the expression and then we ll combine 1 s and make groups of 2 or 4 or 8 or 16 terms and then write the shortened expression. Any two adjacent squares in the K map differ only by 1 bit change. So the thing where the term corresponding to one square differs from the term corresponding to the adjacent square is that one literal is in compliment form and same literal in other is noncompliment. So sum of those min terms would lead to elimination of one literal and simplified result would be a single AND term. Also note that squares on one edge of the k-map are adjacent to the opposite edge of the K-map. Hence m0 is adjacent to m2, m4 is adjacent to m6 but m0 is not adjacent to m6. Similarly we can check the adjacent cells in 4-variable map. Electronics and Communication Engineering Department 36 Digital Logic Circuits

37 5. Explain Don t care conditions. [CO2-H1] When ever there are don t cares present in the K-map then we have the option of including don t care in the group to maximize the size of group and hence we get more minimized form but this is not compulsory to include each and every don t care. So we can use don t care to our advantage otherwise skip them. e.g. Minimize the K-map given below: And we see that we have used 2 don t care and we make a group of 4 rather than 2 while we skip the 3 rd don t care as we do not have to use each don t care. Electronics and Communication Engineering Department 37 Digital Logic Circuits

38 Hence we see that using 2 out of 3 don t care we have got more minimized equation. 6. Simplify the given functions using K- Map Minimization method. [CO2-H2] (1) Simplify Z = f(a,b) = + A + B Consider the expression Z = f(a,b) = + A + B plotted on the Karnaugh map: Pairs of 1's are grouped as shown above, and the simplified answer is obtained by using the following steps: Note that two groups can be formed for the example given above, bearing in mind that the largest rectangular clusters that can be made consist of two 1s. Notice that a 1 can belong to more than one group. The first group labelled I, consists of two 1s which correspond to A = 0, B = 0 and A = 1, B = 0. Put in another way, all squares in this example that correspond to the area of the map where B = 0 contains 1s, independent of the value of A. So when B = 0 the output is 1. The expression of the output will contain the term For group labelled II corresponds to the area of the map where A = 0. The group can therefore be defined as. This implies that when A = 0 the output is 1. The output is therefore 1 whenever B = 0 and A = 0 Hence the simplified answer is Z = + Electronics and Communication Engineering Department 38 Digital Logic Circuits

39 7. Minimise the following problems using the Karnaugh maps method. [CO2- H1] Z = f(a,b,c) = + B + AB + AC Z = f(a,b,c) = B + B + BC + A 8. Explain redundancy in K map. [CO2-H1] Redundant groups A groups of 1s or 0s whose all members are overlapped by other groups is called redundant group. We don t consider this group while writing the simplified equations from the K-map. Electronics and Communication Engineering Department 39 Digital Logic Circuits

40 In the above K-map the group which is represented by the oval is a redundant group and hence while writing the equations we ignore it or we don t make this kind of group and the K-map representation becomes as given next: The equation we get is F= yz w + x z w (ignoring the redundant group) If we consider this group then equation would be F= yz w + x z w + x yz And this is a not the simplified expression and hence WRONG. K-map without the redundant group is: Electronics and Communication Engineering Department 40 Digital Logic Circuits

41 9. Explain with a neat sketch Half Adder. [CO2-H1] Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum. Block diagram Truth Table Electronics and Communication Engineering Department 41 Digital Logic Circuits

42 Circuit Diagram 10. Design a full adder using two half adders and an OR gate. [CO2-H1] A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables, denoted by x and y, represent the two significant bits to be added. The third input z, represents the carry from the previous lower significant position. Step 1 : Determine the number of inputs and outputs. Step 2 : Draw the truth table for a full adder with three inputs x,y and z and two outputs S and C out. Inputs Outputs x y z S um C out Electronics and Communication Engineering Department 42 Digital Logic Circuits

43 Step 3 : Obtain the K map Simplification for Sum and Carry Out Step 4 : Implementation A full adder can be implemented with two half adders and one OR gate as shown in the Fig. The S output from the second half-adder is the exclusive-or of Z and the output of the first half adder, giving and the carry output is Fig. Implementation of a full adder with two Half adders and an OR gate Electronics and Communication Engineering Department 43 Digital Logic Circuits

44 11. Explain Full Adder with neat sketch. [CO2-H1] Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit. Block diagram Truth Table Circuit Diagram Electronics and Communication Engineering Department 44 Digital Logic Circuits

45 12. Design a Half Subtractor and explain its operation. [CO2-H1] Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit. Truth Table Circuit Diagram 13. Design a Full Subtractor circuit and explain its operation. [CO2-H1] The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is the borrow output. Electronics and Communication Engineering Department 45 Digital Logic Circuits

46 Truth Table Circuit Diagram 14. Explain the operation of Multiplexer circuit. [CO2-H1] Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of Electronics and Communication Engineering Department 46 Digital Logic Circuits

47 the n data inputs and routes it to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal that means it will perform the required operation when it is low. Block diagram Multiplexers come in multiple variations 2 : 1 multiplexer 4 : 1 multiplexer 16 : 1 multiplexer 32 : 1 multiplexer Electronics and Communication Engineering Department 47 Digital Logic Circuits

48 Block Diagram Truth Table 15. Implement the given Boolean function using 8: 1 multiplexer. [CO2-H1] F (A, B, C) = (1, 3, 5, 6) Step 1 : The given function can be implemented using a 4 x1 multiplexer B and C inputs are connected to the Selection lines S 1 and S 0 respectively. Figures (a) shows the multiplexer implementation Fig (a) Multiplexer implementation Electronics and Communication Engineering Department 48 Digital Logic Circuits

49 Fig (b) Truth table 16. Implement the full subtractor using demultiplexer. [CO2-H1] Step 1 : Write the truth table of full subtractor. Step 2 : Represent output of full subtractor in minterm form. For full subtractor, difference D function can be written as D = f(a,b,c) = m = (1,2,4,7) and the Borrow out can be written as B out = f(a,b,c) = m = (1,2,3,7) Electronics and Communication Engineering Department 49 Digital Logic Circuits

50 Step 3 : Logically OR the outputs corresponding to minterms. With D 0 input 1, demultiplexer gives minterms at the output so by logically ORing the required minterms we can implement Boolean functions for full subtractor. 17. Explain Decoders and its types. [CO2-H1] A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder. Block diagram Electronics and Communication Engineering Department 50 Digital Logic Circuits

51 Examples of Decoders are following. Code converters BCD to seven segment decoders Nixie tube decoders Relay actuator 2 to 4 Line Decoder The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where D through D are the four outputs. Truth table explains the operations of a decoder. It shows that each output is 1 for only a specific combination of inputs. Block diagram Truth Table Electronics and Communication Engineering Department 51 Digital Logic Circuits

52 Logic Circuit 18. Design a 3:8 decoder using basic gates. [CO2-H1] A 3 to 8 decoder has three inputs(a,b,c) and eight outputs (D 0 to D 7 ). Based on the three inputs one of the eight outputs is selected. The Truth table for 3 to 8 Decoder is given below : Electronics and Communication Engineering Department 52 Digital Logic Circuits

53 19.Explain Encoders. [CO2-H1] Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. The encoder accepts an n input digital word and converts it into an m bit another digital word. Block diagram Electronics and Communication Engineering Department 53 Digital Logic Circuits

54 Examples of Encoders are following. Priority encoders Decimal to BCD encoder Octal to binary encoder Hexadecimal to binary encoder 20. What is a code converter? State its types. [CO2-L1] A code converter circuit will convert coded information in one form to a different coding form. Types of code converters ; (i) Binary to Gray code converter (ii) Gray to Binary code converter (iii) BCD to Excess 3 code converter (iv) Excess 3 to BCD converter 21.Design a binary to gray code converter. [CO2-H1] Step 1 : Form a truth table relating Binary code as input and Gray code as output. Binary Code Gray Code Decimal D C B A G 3 G 2 G 1 G Electronics and Communication Engineering Department 54 Digital Logic Circuits

55 Step 2 : Perform K map simplification for each gray code output. Electronics and Communication Engineering Department 55 Digital Logic Circuits

56 Step 3 : Realization of code converter using XOR gate. 23. Design a four bit BCD to excess-3 code converter. Draw the logic diagram. [16] Step 1 : Form a truth table relating BCD code and Excess-3 code. Electronics and Communication Engineering Department 56 Digital Logic Circuits

57 Step 2 : K map simplification for each Excess-3 code output Electronics and Communication Engineering Department 57 Digital Logic Circuits

58 Step 3 : Realization of Code converter Electronics and Communication Engineering Department 58 Digital Logic Circuits

59 Unit - III Synchronous Sequential Circuits Part A 1. Show how the JK flip flop can be modified into a D flip flop or a T flip flop[co3-l2]. D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four combinations. J and K are expressed in terms of D and Qp. The four combination conversion table, the K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from JK to D are given below. 2. Draw the truth table and state diagram of SR flip-flop. [CO3-L1]. State diagram Truth table Electronics and Communication Engineering Department 59 Digital Logic Circuits

60 3. Give the characteristic equation and characteristic table of SR flip-flop. [CO3-L1- A/M 2016]. 4. Write down the characteristic equation for JK flip-flop. [CO3-L1] Characteristic equation for JK flip-flop is Q t+1 = 5. How do you eliminate the race around condition in a JK flip-flop. [CO3-L1] Race around condition in a JK flip-flop can be eliminated using master-slave configuration. A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and other as a slave. The output of the master is fed as an input to the slave. Electronics and Communication Engineering Department 60 Digital Logic Circuits

61 6. Realize JK flip flop using D flip flop. [CO3-L3] In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qp. The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to JK are given in the figure below. 7. Draw the state table and excitation table of T flip-flop. [CO3-L1] Electronics and Communication Engineering Department 61 Digital Logic Circuits

62 8. How a D flipflop is converted into T flip-flop./ Convert D flip to T flip-flop. [CO3-L2] 9. How many flipflops are required to build a binary counter that counts from 0 to [CO3-L2] Number of flip-flops is given as 2 n count +1, where n is the number of flipflops. Therefore, 2 n , i.e., 2 n It implies, n = 10 Hence, 10 flip-flops are required to build a binary counter that counts form 0 to Electronics and Communication Engineering Department 62 Digital Logic Circuits

63 10. Define : Latches. The flip-flops that operate with signal levels are referred as latches. Latch is a memory cell which is capable of storing one bit of information, ie. Logic 1 or logic 0. Latches are controlled by enable signals and they are level sensitive devices. Latches are basic building blocks of flip-flops. 11.Sketch the logic diagram of a clocked SR flip flop. [CO3-L1] 12. Draw the master-slave JK flip-flop. [CO3-L1] 13.What are edge triggered flip flops? [CO3-L1] Flip-flop changes its state either at positive edge or negative edge of the clock pulse and is sensitive to its inputs only at this transition of the clock. These type of flipflops are referred to as edge triggered flip flops. Electronics and Communication Engineering Department 63 Digital Logic Circuits

64 14. Mention any two differences between the edge triggering and level triggering. [CO3-L1] Edge Triggering Level Triggering Flip-flop changes its state either at When the clock pulse goes high the flipflop is said to be level triggered flip-flop. positive edge or negative edge of the clock pulse and is sensitive to its inputs When flip-flop, changes its state by only at this transition of the clock. applying positive clock- positive level triggering. When flip-flop, changes its state by applying negative clock negative level triggering. 15. What is meant by programmable counter? Mention its application. [CO3-L1] A counter that divides an input frequency by a number which can be programmed is called programmable counter. Applications: Frequency division, digital clock, stop watch and programmable logic controller. 16. Compare the logics of synchronous counter and ripple counter. [CO3-L1] Synchronous counter Ripple ( Asynchronous counter) In Synchronous counter, no connection Here flip-flops are connected in such a exists between output of first flip-flop and clock input of next flip-flop. way that output of first flip-flop drives the clock for the next flip-flop. All flip-flops are clocked simultaneously. All flip-flops are not clocked simultaneously. Circuit is simple. Circuit is complex. High speed counters. Low speed is the drawback. Electronics and Communication Engineering Department 64 Digital Logic Circuits

65 17. What is a ripple counter? [CO3-L1] A ripple counter is a cascaded arrangement of flip-flops where the output of one flipflop drives the clock input of the following flip-flop. A ripple counter is also called as asynchronous counter or a serial counter, as the clock input is applied only to the first flip-flop, also called the input flip-flop in the cascaded arrangement. 18.What is a shift register? [CO3-L1] A register capable of shifting its binary information in one or both directions is called a shift register. 19.Mention the types of shift register? [CO3-L1] (i) SISO Serial in Serial Out (ii) SIPO - Serial in Parallel Out (iii) PISO- Parallel in Serial Out (iv) PIPO Parallel in Parallel Out (v) Bidirectional shift register 20. State the differences between Mealy and Moore state machines. [CO3-L2] Moore Machine Mealy Machine Its output is a function of present state Its output is a function of present state as only. well as present input. Input changes does not affect the output. Input changes may affect the output of the circuit. It requires more number of states for It requires less number of states for implementing the same function. implementing the same function. 21. State the rules for state assignment. [CO3-L2] Assignment of values to state variables is called state assignment. A binary value is assigned to each of the states Electronics and Communication Engineering Department 65 Digital Logic Circuits

66 22. What is state reduction? [CO3-L1] The reduction of number of states in a state table is called as state reduction.by state reduction the number of flip-flops in a sequential circuit is reduced Part B 1. Explain the circuit of a SR flip-flop and explain its operation. [CO3- H1] The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two gates connected as shown in Fig Notice that the output of each gate is connected to one of the inputs of the other gate, giving a form of positive feedback or cross-coupling. The circuit has two active low inputs marked S and R, NOT being indicated by the bar above the letter, as well as two outputs, Q and Q. Table shows what happens to the Q and Q outputs when a logic 0 is applied to either the S or R inputs. Electronics and Communication Engineering Department 66 Digital Logic Circuits

67 The SR Flip-flop Truth Table 1. Q output is set to logic 1 by applying logic 0 to the S input. 2. Returning the S input to logic 1 has no effect. The 0 pulse (high-low-high) has been remembered by the Q. 3. Q is reset to 0 by logic 0 applied to the R input. 4. As R returns to logic 1 the 0 on Q is remembered by Q. From the diagram it is evident that the flip flop has mainly four states. They are S=1, R=0 Q=1, Q =0 This state is also called the SET state. S=0, R=1 Q=0, Q =1 Electronics and Communication Engineering Department 67 Digital Logic Circuits

68 This state is known as the RESET state. In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the value of S. S=0, R=0 Q & Q = Remember If both the values of S and R are switched to 0, then the circuit remembers the value of S and R in their previous state. S=1, R=1 Q=0, Q =0 [Invalid] This is an invalid state because the values of both Q and Q are 0. They are supposed to be compliments of each other. Normally, this state must be avoided. 2. Explain the operation of a master slave JK flip flop. [CO3- H1] Electronics and Communication Engineering Department 68 Digital Logic Circuits

69 UNIT- IV Asynchronous Sequential Circuits and PLD Part A 1. Compare pulsed mode and fundamental mode asynchronous circuit. [CO4- L2] In a fundamental mode circuit, all of the input signals are considered to be levels. Fundamental mode operation assumes that the input signals will be changed only when the circuit is in a stable state and that only one variable can change at a given time. In pulse mode circuits, the inputs are pulses rather than levels. In this mode of operation the width of the input pulses is critical to the circuit operation. The input pulse must be long enough for the circuit to respond to the input but it must not be so long as to be present even after new state is reached. 2. What are the two types of asynchronous sequential circuits? [CO4-L1] Two types of asynchronous sequential circuits are fundamental mode and pulse mode asynchronous circuits. 3. Define critical race. [CO4-L1] If the order in which the changes are recognized does alter the final state in which the machine rests then we have a critical race. A critical race always leads to unpredictable behavior which must be avoided at all costs in the fundamental mode machine. Electronics and Communication Engineering Department 69 Digital Logic Circuits

70 4. Define non-critical race. [CO4-L1] If the order in which the changes are recognized does not alter the final state in which the machine rests after all the changes have occurred, then we have a non-critical race. A non-critical race condition can be and is tolerated in the fundamental mode machines. 5. What is a state table? [CO4-L1] The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. 6. What is a State Diagram? [CO4-L1] In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically by a state diagram. In this diagram, a state is represented by a circle, and the transition between states is indicated by directed lines (or arcs) connecting the circles. An example of a state diagram is shown in below. Electronics and Communication Engineering Department 70 Digital Logic Circuits

71 7. What are asynchronous circuits? [CO4-L1] The circuit is considered to be asynchronous if it does not employ a periodic clock signal C to synchronize its internal changes of state. Therefore the state changes occur in direct response to signal changes on primary (data) input lines, and different memory elements can change state at different times. In asynchronous sequential circuits the inputs are levels and there are no clock pulses; the inputs events drive the circuit. 8. Explain ROM. [CO4-H1] A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit Combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2n. 9. What are the types of ROM? [CO4-L1] 1. PROM 2. EPROM 3. EEPROM 10. Explain PROM. [CO4-H1] PROM (Programmable Read Only Memory) it allows user to store data or program. PROMs use the fuses with materiallike nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 ma of current for the period 5 to 20μs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent. 11. Explain EPROM. [CO4-H1] EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They store 1 s and 0 s as a packet of charge in a buried layer of the IC Electronics and Communication Engineering Department 71 Digital Logic Circuits

72 chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed. 12. Explain EEPROM. [CO4-H1] EEPROM (Electrically Erasable Programmable Read Only Memory). EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals. 13. Define address and word: [CO4-L1] In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 14. What are the types of ROM.? [CO4-L1] 1. Masked ROM. 2. Programmable Read only Memory 3. Erasable Programmable Read only memory. 4. Electrically Erasable Programmable Read only Memory. 15 What is programmable logic array? How it differs from ROM? [CO4-L3] In some cases the number of don t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the min terms as in the ROM. 16. What is mask - programmable? [CO4-L1] With a mask programmable PLA, the user must submit a PLA program table to the manufacturer. 17. What is field programmable logic array(fpga)? [CO4-L1] The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA. Electronics and Communication Engineering Department 72 Digital Logic Circuits

73 18. List the major differences between PLA and PAL[CO4-L1] PLA:Both AND and OR arrays are programmable and Complex Costlier than PAL PAL:AND arrays are programmable OR arrays are fixed Cheaper and Simpler 19. Define PLD. [CO4-L1] Programmable Logic Devices consist of a large array of AND gates and OR gates that Can be programmed to achieve specific logic functions. 20. Give the classification of PLDs. [CO4-L1] PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL) 21. Define PROM. [CO4-L1- A/M 2015) & (N/D 2015] PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates Connected to a decoder and a programmable OR array. 22. Define PLA. [CO4-L1] PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a Programmable AND array and a programmable OR array. 23. Define PAL. [CO4-L1] PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic. 24. What is CPLD? [CO4-L1] CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs with a centralized internal interconnect matrix used to connect the device macro cells together. Electronics and Communication Engineering Department 73 Digital Logic Circuits

74 25. Define Static RAM and dynamic RAM. [CO4-L1] Static RAM use flip flops as storage elements and therefore store data indefinitely as long as dc power is applied. Dynamic RAMs use capacitors as storage elements and cannot retain data very long without capacitors being recharged by a process called refreshing. 26. List basic types of programmable logic devices[co4-l2]. 1. Read only memory 2. Programmable logic Array 3. Programmable Array Logic 27. Draw the block diagram of PLA. [CO4-L1] Electronics and Communication Engineering Department 74 Digital Logic Circuits

75 Part- B 1. Describe the various methods of race free state assignment with examples. [CO4-H1] RACE-FREE STATE ASSIGNMENT: Choose a proper binary state assignment to prevent critical races. Only one variable can change at any given time when a state transition occurs. States between which transitions occur will be given adjacent assignments Two binary values are said to be adjacent if they differ in only one variable To ensure that a transition table has no critical races, every possible state transition should be checked. 2. Explain the steps for the design of asynchronous sequential circuits. [CO4- H1] Design steps: 1. Construction of a primitive flow table from the statement. And intermediate step may include the development of a state diagram 2. Primitive flow table is reduced by eliminating redundant states by using state reduction techniques. 3. state assignment is made The primitive flow table is realized using appropriate logic elements. 3. What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches? Give an example. (16) [CO4-H2-Apr/ May 2010] Essential hazard is caused by unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in Electronics and Communication Engineering Department 75 Digital Logic Circuits

76 comparison to the delay associated with the feedback path may cause such a hazard. In digital logic, a hazard in a system is an undesirable effect caused by either a deficiency in the system or external influences. Logic hazards are manifestations of a problem in which changes in the input variables do not change theoutput correctly due to some form of delay caused by logic elements (NOT, AND, OR gates, etc.) This results in the logic not performing its function properly. The three different most common kinds of hazards are usually referred to as static, dynamic and function hazards. 4. Draw the basic block diagram of PLA device and explain each block. List out its applications. Implement a combinational circuit using PLA by taking a suitable Boolean function. (Nov/Dec 2011) A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logiccircuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms. INPUTS FIXED FIXED FUSES PROGRAMMABLE FUSES PROGRAMMABLE OUTPUT AND ARRAY OR ARRAY Electronics and Communication Engineering Department 76 Digital Logic Circuits

77 Electronics and Communication Engineering Department 77 Digital Logic Circuits