De Morgan s second theorem: The complement of a product is equal to the sum of the complements.

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Bertram Cross
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1 Q. What is Gate? State and prove De Morgan s theorems. nswer: digital circuit having one or more input signals but only one output signal is called a gate. De Morgan s first theorem: The complement of a sum is equal to the product of the complements.. Proof: We know from oolean lgebra X X, X. X, X YZ ( X Y )( X Z) Let P and Q. P Q ( ) (. ) ( )( ) [ X YZ ( X Y )( X Z)] ( )( ). Therefore, Q P.. OR P. Q ( )..... Therefore, Q P.. De Morgan s second theorem: The complement of a product is equal to the sum of the complements.. Proof: We know from oolean lgebra X X, X. X, X YZ ( X Y )( X Z) Let P and Q P Q Q P ( ) ( )( ) ( )( ). Therefore, Q P OR P. Q.( ).. Therefore, Q P Q2. Differentiate analog and digital signals. nswer: nalog signals are continuous and all possible values are considered. In the figure below, temperature is measured for water in a container which is heated for particular duration at all possible instant of time as a continuous signal. Digital signal are only finite values at particular interval. In the figure below, temperature is measured for water in a container which is heated for particular duration at discrete interval of time as a digital signal. Page:

2 Temp (Centigrate) 6 4 Continuous Signal Temp (Centigrate) 6 4 Digital Siganal t (min.) 3 6 t (min.) Q3. Define (i) rise time (ii)fall time (iii)period (iv) frequency (v) duty cycle of a digital signal. nswer: (i) Rise Time: It is defined as the time required for a signal to rise from its low level to its high level. Rise Time is measured as the time required between. L and.9h as shown in the figure. For example, suppose H=4V and L=2V, then.l=2.2v and.9h=3.6v. (ii) Fall Time: It is defined as the time required for a signal to fall from its high level to its low level. Fall Time measured is as the time required between.9h and.l as shown in the figure.. volt H.9H.L L t(sec) t f t r Page: 2

3 (iii) Period (T): Time required to complete one high and one low. s shown in the figure, t H is the time required to complete one high and t L is the time required to complete one low. T=t H +t L (iv) Frequency (f): Frequency is the reciprocal of the time period. f=/t t (v) Duty Cycle: Duty cycle H= H t and Duty cycle L= L T T Duty cycle H is the ratio of time the signal is high to the time period. Duty cycle L is the ratio of time the signal is low to the time period. T H t H t L L Q4. (i) Prove that duty cycle of a symmetrical waveform is 5%. (ii) What is the value of high duty cycle (duty cycle H) if the frequency of a digital waveform is 5 MHz and the width of the positive pulse is.5 µs? (iii) n asymmetrical signal waveform is high for 2ms and low for 3ms. Find Frequency, Period, Duty cycle low, Duty cycle high nswer: For a symmetrical waveform, High period is T/2 and the Low period is T/2 where T is the time period. T T (i) Therefore, Duty Cycle H= 2 % 5% and Duty Cycle L= T 2 % 5% T ( ii) f 5 MHz Perriod, T =.2 s 6 f 5 Width of the high pulse.5 s t Duty cycle H.5 %=25%.2 ( iii) t Width of high signal 2 ms and t Width of low signal 3ms H Period, T t t 2 3 5ms H L Frequency, f 2Hz 3 T 5 tl 3ms Duty cycle low % 6% T 5 ms th 2ms Duty cycle high % 4% T 5ms L Page: 3

4 Q5. Describe positive logic and negative logic. List the equivalences in positive and negative logic. nswer: If a binary stands for low voltage and a binary stands for high voltage, then this is called positive logic. If a binary stands for low voltage and a binary stands for high voltage, then this is called negative logic. Let us consider the table below as an example: Y LOW LOW LOW LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH If we use positive logic, the above table is converter to: Y This is the truth table for OR Gate If we negative logic, the same table is converted to: Y This is the truth table for ND Gate Therefore, positive OR negative ND Following are the equivalences in positive and negative logic: Positive OR Negative ND Positive ND Negative OR Positive NOR Negative NND Positive NND Negative NOR Q6. Prove that (a) Positive OR logic is equal to Negative ND logic (b) Positive ND logic is equal to Negative OR logic (c) Positive NOR logic is equal to Negative NND logic (d) Positive NND logic is equal to Negative NOR logic nswer: (a) Let us consider the table below: Y LOW LOW LOW LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH Page: 4

5 If we use positive logic, the above table is converter to: Y This is the truth table for OR Gate If we negative logic, the same table is converted to: Y This is the truth table for ND Gate Therefore, Positive OR logic is equal to Negative ND logic: (b) : (a) Let us consider the table below: Y LOW LOW LOW LOW HIGH LOW HIGH LOW LOW HIGH HIGH HIGH If we use positive logic, the above table is converter to: Y This is the truth table for ND Gate If we negative logic, the same table is converted to: Y This is the truth table for OR Gate Therefore, Positive ND logic is equal to Negative OR logic (c) (a) Let us consider the table below: Y LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW HIGH HIGH LOW Page: 5

6 If we use positive logic, the above table is converter to: Y This is the truth table for NOR Gate If we negative logic, the same table is converted to: Y This is the truth table for NND Gate Therefore, Positive NOR logic is equal to Negative NND (d) ) Let us consider the table below: Y LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH LOW If we use positive logic, the above table is converter to: Y This is the truth table for NND Gate If we negative logic, the same table is converted to: Y This is the truth table for NOR Gate Therefore, Positive NND logic is equal to Negative NOR logic Q7. What is a universal gate? List the universal gates and prove their universalities. nswer: universal gate is a gate that can be used to realize any other gate and therefore, a universal gate can be used to realize any oolean function without using any other gate. Universal gates are NOR gate and NND gate. Page: 6

7 Proof of NND gate as universal gate: ny oolean function can be implemented using NOT gate, ND gate and OR gate. Therefore, if NOT gate, ND gate and OR gate are implemented using NND gate only, then it will be proved that NND gate is a universal gate. Implementing NOT using NND gate Implementing of ND gate using NND gates.. =. Implementing OR using NND gate.=+=+ Proof of NOR gate as universal gate: ny oolean function can be implemented using NOT gate, ND gate and OR gate. Therefore, if NOT gate, ND gate and OR gate are implemented using NOR gate only, then it will be proved that NOR gate is a universal gate. Page: 7

8 Implementing NOT using NOR gate Implementing of OR gate using NOR gates + += + Implementing ND using NOR gates + =.=. Q8. Realize the XOR gate using (i) NND gate (ii) NOR gate. nswer: (i) The following figure shows the realization of XOR gate with NND gates:... Y=(..).(..).. Y (.. ).(.. ) ( ).( ).. Page: 8

9 (ii)the following figure shows the realization of XOR gate with NOR gates: + Y=+++ + Y ( ).( ) ( ).( ) lternately, ++ + Y=+++++ Y= Y...( ).( ).. Q9. Implement the following functions using NND gate only: (i) (( ). C) (ii) Y (( ). C). D (iii) (( ).( )) nswer: (i).=+ + +.C +.C (ii) C + (+).C ((+).C).D ((+).C).D C D Page: 9

10 (iii) ( ).( )..... Y=..+.. =+ +.. Q. Implement the following functions using NOR gate only: (i) (( ). C) (ii) Y (( ). C). D (iii) (( ).( )) nswer: (i) + +=+ (+).C C C (ii) + (+).C ((+).C).D C C D D (iii) ( ).( ) Y=+++++ =+ ++ Y.( ).( ).( ).( ).. Page:

11 Q. Define canonical Minterm form and canonical Maxterm form. nswer: Minterm: minterm, denoted by m i, i<2 n, is a product of n variables in which each variable is complemented if the value assigned to it is. Let us consider a oolean function F f ( x, y, z) x yz xy z xyz xyz. Truth table of the above function along with the minterms is shown below: x y z Minterm F m =x y z m = x y z m 2 = x yz m 3 = x yz m 4 = xy z m 5 = xy z m 6 = xyz m 7 = xyz The above function can be expressed in term of minterms as F=m 3 +m 5 +m 6 +m 7 =Σm(3,5,6,7) The inverse of the function can be expressed as F = Σm(,,2,4) Maxterm: maxterm, denoted by M i, i <2 n, is a sum of n variables in which each variable is complemented if the value assigned to it is. Let us consider a oolean function F f ( x, y, z) ( x y z)( x y z )( x y z)( x y z) Truth table of the above function along with maxterm is shown below: x y z Maxterm F M =x+y+z M = x+y+z M 2 = x+y +z M 3 = x+y +z M 4 = x +y+z M 5 = x +y+z M 6 = x +y +z M 7 = x +y +z The above function can be expressed in term of maxterms as F=M.M.M 2.M 4 =ΠM(,,2,4) The inverse of the function can be expressed as F = ΠM(3,5,6,7).Q2. Express the function F=x+yz as the sum of its minterms and product of maxterms. nswer : F x yz x( y y )( z z ) yz( x x ) xyz xyz xy z xy z xyz x yz F xyz xyz xy z xy z x yz m7 m6 m5 m4 m3 m(3,4,5,6,7) gain, F x yz ( x y)( x z) ( x y zz )( x z yy ) F ( x y z)( x y z )( x z y)( x z y ) ( x y z)( x y z )( x y z) M. M. M M (,, 2) 2 Page:

12 Q3. Express the function F=(x+yz) as the sum of its minterms and product of maxterms. nswer : F ( x yz) ( x ( yz)) x.( yz) x.( y z ) x y x z x y ( z z ) x z ( y y ) F x y z x y z x yz x y z x y z x y z x yz m m m2 m(,, 2) gain, F ( x yz) ( x ( yz)) x.( yz) x.( y z ) ( x yy zz )( y z xx ) F ( x yy z)( x yy z )( y z x)( y z x ) F ( x y z)( x y z)( x y z )( x y z )( x y z )( x y z ) F ( x y z)( x y z)( x y z )( x y z )( x y z ) F M. M. M. M. M M (3,4,5,6,7) Q4, Convert the following 3-variable SOP to POS form. (i) Σm(3,5,6,7) (ii) Σm(,2,5,6) nswer: (i) Σm(3,5,6,7)=ΠM(,,2,4) (ii) Σm(,2,5,6)=ΠM(,3,4,7) Q5. Convert the following 4-variable POS to SOP form. (i) ΠM(,3,4,7) (ii) ΠM(,,2,4,,3,5) nswer: (i) ) ΠM(,3,4,7)=Σm(,2,5,6,8,9,,,2,3,4,5) (ii) ΠM(,,2,4,,3,5)=Σ(3,5,6,7,8,9,,2,4) Q6. Use K-Map to simplify the following functions: ( i) f (,, C, D) m(, 2,6,,,2,3) d(3,4,5,4,5) ( ii) f m(, 2, 6, 7,8,3,4,5) d(3,5,2) ( iii) f m(,3, 4,5,3,5) d(8,9,,) ( iv) f (,, C, D) ( C)( D)( C)( C) ( v) f (,, C, D) (, 2, 4,5,7,8,,,3, 4) nswer: (i) CD X X X X X f (,, C, D) CD C D Page: 2

13 (ii)let us consider the variables as,, C and D. CD X X X f (,, C, D) D C CD (iii) Let us consider the variables as,, C and D. CD X X X X f (,, C, D) D D C ( iv) f (,, C, D) ( C)( D)( C)( C) ( C D)( C D)( C D)( C D)( C D)( C D) ( C D)( C D)( C D)( C D)( C D)( C D) ( C D)( C D) M 3. M 2. M5. M3. M 7. M 5. M2. M 9. M 8. M. M M. M. M 2. M 3. M 5. M 7. M 8. M 9. M2. M3. M5 Page: 3

14 CD (v) CD f (,, C, D) ( )( C D)( D)( C) f ( C)( D)( C D)( C D)( C)( C D)( D)( C D) Q7, Simplify the Product of Sum expression below and provide the result in POS form. F(,, C, D) ( C D)( C D)( C D)( C D)( C D) ( C D)( C D) Page: 4

15 nswer: CD (+C+D) ++C+D ++C+D ++C+D ++C+D ++C+D ++C+D (C+D) +C+D ++C+D Therefore, the result in POS, F ( C D)( C D)( C D) Q8. Simplify the Product Of Sum expression below and provide the result in SOP form. F(,, C, D) ( C D)( C D)( C D)( C D)( C D) ( C D)( C D) nswer: CD Therefore, the result in SOP, F C D CD D Page: 5

16 Q9. Find the minimal SOP and minimal POS of the following oolean function using K-Map. f ( a, b, c, d) m(6,7,9,,3) d(, 4,5,) nswer: ab cd X X X X ab Minimal SOP is given by f ( a, b, c, d) ab cd abc cd X X X X Minimal POS is given by f ( a, b, c, d) ( a b)( c d)( a b c) Q2. Reduce the following oolean function using K-Map and realize the simplified expression using NND gates. T f ( a, b, c, d) m(,3, 4,5,3,5) d(8,9,,) Page: 6

17 nswer: ab cd X X X X T f ( a, b, c, d) cd ad bd abc Following diagram shows the realization of the above expression with NND gates a b c d T Page: 7

18 Q2. Simplify the following expressions using Karnaugh map. Implement the simplified circuit using the gates as indicated: ( i) f ( w, x, y, z) m(,5, 7,9,,3,5) d(8,,4) using NND gates. (ii) f (,, C, D) M (,, 2, 4,5, 6,8,9,2,3,4) using NOR gates. nswer: (i) wx yz X X X f ( w, x, y, z) yz wx xz Following is the implementation of the simplified circuit with NND gates. w x y z f Page: 8

19 (ii) CD f (,, C, D) C( D)( D) Following is the implementation of the simplified circuit with NOR gates. C D +D (+D)(+D) (+D)(+D) +D C f Page: 9

20 Q22. Simplify the following using Quine McClusky minimization technique: ( i) P f ( w, x, y, z) m(7,9,2,3,4,5) d(4,) ( ii) Y f ( a, b, c, d) (,, 2, 6, 7,9,,2) d(3,5). Verify the result using K-map. ( iii) f (,, C, D) m(,,2,3,,,2,3,4,5) ( iv) f ( W, X, Y, Z) m(,3,6,7,8,9,,2,3,4) nswer: (i) f(w,x,y,z)=σm(7,9,2,3,4,5)+d(4,) Stage Stage 2 Stage 3 wxyz wxyz wxyz (4) (9) (2) (7) ) (3) (4) (5) (4,2) (9,) (9,3) (2,3) (2,4) (7,5) (,5) (3,5) (4,5) (9,,3,5) (9,3,,5) (2,3,4,5) (2,4,3,5) wz (9,,3,5) wx (2,3,4,5) xy z (4,2) xyz (7,5) P f ( w, x, y, z) wz wx xyz Page: 2

21 Verification: yz wx X X P f ( w, x, y, z) wz wx xyz (ii) Y=f(a,b,c,d)=Σm(,,2,6,7,9,,2)+d(3,5) Stage Stage 2 Stage 3 abcd abcd abcd () () (2) (3) (5) (6) (9) () (2) (7) (,) (,2) (,3) (,5) (,9) (2,3) (2,6) (2,) (3,7) (5,7) (6,7) (,,2,3) (,2,,3) (,3,5,7) (,5,3,7) (2,3,6,7) (2,6,3,7) Page: 2

22 abc d (2) b c d(,9) b cd (2,) a b (,,2,3) a d(,3,5,7) a c(2,3,6,7) Y= abc d + b c d + b cd + a b + a c Verification: ab cd X X Y= abc d + b c d + b cd + a b + a c Page: 22

23 (iii) f(,,c,d)=σm(,,2,3,,,2,3,4,5) Stage Stage 2 Stage 3 CD CD CD () () (2) - - (,) (,2) (3) () (2) () (3) (4) (5) (,3) (2,3) (2,) (3,) (,) (,4) (2,3) (2,4) (,5) (3,5) (4,5) (,,2,3) (,2,,3) (2,3,,) (2,,3,) (,,4,5) (,4,,5) (2,3,4,5) (2,4,3,5) (,, 2,3) C(2,3,,) C (,,4,5) (2,3,4,5) f (,, C, D) C or f (,, C, D) C Verification: CD f (,, C, D) C Page: 23

24 (iv) f(w,x,y,z)=σm(,3,6,7,8,9,,2,3,4) Stage Stage 2 Stage 3 WXYZ WXYZ WXYZ () (8) (3) (6) (9) () (2) (7) (3) (4) (,3) (,9) (8,9) (8,) (8,2) (3,7) (6,7) (6,4) (9,3) (,4) (2,3) (2,4) (8,9,2,3) (8,,2,4) (8,2,,4) W X Z(,3) X Y Z(,9) W YZ(3,7) W XY (6,7) XYZ (6,4) WY Z (9,3) WY (8,9,2,3) WZ (8,,2,4) f ( W, X, Y, Z) W X Z W XY WY WZ Page: 24

25 Verification: WX YZ f ( W, X, Y, Z) W X Z W XY WY WZ Q23. What are static hazards? How to design a hazard free circuit? Explain with an example. nswer: When the input to a combinational circuit changes, unwanted switching transients may appear in the output. These transients occurs when different paths from input to output have different propagation delays. Static- hazard: This type of hazard occurs when makes a transition. Y type situation appears for a logic circuit and T =NOT gate delay Y T T 2 =OR gate delay Y T 2 n condition should always generate at the output i.e static-. ut the NOT gate output takes finite time to become following transition of. Thus for the OR gate there are two zeros appears at the input for that small duration resulting a at the output. The width of this zero is in nanosecond order and is called glitch. Designing static- hazard free circuit: Page: 25

26 C C C Y The karnaugh map shown above represented by Y C C Consider the circuit input = and = and then C makes transition. The output shows glitches. Now, consider the following grouping: C C C Y The above circuit includes one additional and from glitches. Static--hazard: Y C C. The additional ensures free This type of hazard occurs when Y kind of situation occurs in a logic circuit and makes a transition. condition should always generate at the output i.e static-. ut the NOT gate output takes finite time to become following a transition of. Thus for final ND gate there are two ones appearing at the inputs for small duration resulting a at its output. Page: 26

27 Y T T =NOT gate delay T 2 =ND gate delay T 2 Y The circuit below is with static- hazard: C Y Consider the circuit input = and = and then C makes transition. The output shows glitches. The circuit below is static- hazard free Y C Page: 27

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1