14:332:231 DIGITAL LOGIC DESIGN. Gate Delays

Size: px

Start display at page:

Download "14:332:231 DIGITAL LOGIC DESIGN. Gate Delays"

Charles Porter
5 years ago
Views:

1 4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all 23 Lecture #8: Timing Hazards Gate Delays hen the input to a logic gate is changed, the output will not change immediately. The switching elements within a gate take a finite time to react to a change (transition) in input. As a result the change in the gate output is delayed w.r.t. to the input change. Such delay is called the propagation delay of the logic gate (t p ) The propagation delay for a -to- output change (t plh ) may be different than the delay for a -to- change (t phl ). 2of 2

2 [RECALL from Lecture #] Transition Delays (a) Ideal case of zero-time switching: (b) A more realistic approximation: t r t f (c) Actual timing for rise (t r, low-to-high) and fall (t f, high-to-low) times: HIGH UNDEINED V IHmin LO V ILmax t r t f 3of 2 Propagation Delays for a CMOS Inverter (a) Ignoring rise and fall times: V IN NOT V OUT t phl t plh (b) Measured at midpoints of transitions: V IN V OUT t phl t plh 4of 2 2

3 Effect of Gate Delays The analysis of a combinational circuit ignoring delays can predict only its steady-state behavior Predicts a circuit s output as a function of its inputs assuming that the inputs have been stable for a long time, relative to the delays in the circuit s electronics. Because of circuit delays, the transient behavior of a combinational logic circuit may differ from what is predicted by steady-state analysis. Timing hazard: a circuit s output may produce a short pulse ( glitch ) at a time when steady state analysis predicts that the output should not change. 5of 2 Timing Hazard A gate has measurable response time t plh and t phl. Around ns per gate. Delays through transmission gates can add up and introduce timing hazards. t plh = low-to-high, t phl = high-to-low propagation times static- hazard is a short glitch when for a changed input, we expect (by logic theorems) the output to remain constant. static- hazard is a short glitch when we expect the output to remain constant. (delay) input Logic circuit Gate (no delay) 6of 2 3

4 Circuit with a Static- Hazard Ideal scenario: P P Assume:,, = Consider a transition to,,= hat we logically expect: = + Before: = () + = + = After: = () + = + = No change in the output!! P P time 7of 2 Real orld Gates Introduce Delays delay Input signal of each gate is shifted in the output by a constant delay 8of 2 4

5 Different Paths Introduce Different Delays second path P P first path : Change occurs at input and propagates to output along two paths with different delays Basically because of gate delays for a moment when input changes it is not true that A+A =! 9of 2 Circuit with a Static- Hazard Real world: P AND- NOT AND-2 P OR Assume: = = = time P P delay in NOT gate delay in AND-2 gate delay in AND- gate (following NOT gate) Unexpected glitch in the output delay in OR gate of 2 5

6 Timing Hazards and Karnaugh Maps Recall that in Sum-of-Products (AND-OR) circuits, AND gates correspond to prime implicants of the Karnaugh map A potential hazard exists wherever two adjacent -cells in a Karnaugh map are not covered by a single product term (prime implicant) A hazard occurs when there is a transition between adjacent prime implicants of 2 Eliminating the Timing Hazard To eliminate hazards, find a cover in which all adjacent -cells are covered by a prime implicant Define consensus prime implicant, as a product term not covered in Therefore, include an extra product term to cover the hazardous input combination 2 of 2 6

7 Eliminating the Timing Hazard 2 3 Minimal cost = + (these adjacent -cells are NOT covered -hazard) = + + (consensus term) P P A redundant term was introduced. 3 of 2 So, How Does This Help? P P Unexpected glitch is eliminated! A change in input variable causes a transition between two adjacent -cells but now these -cells are included in the product term : 4 of 2 7

8 hy This orks Because the consensus term fills in ( covers ) the temporary gaps during switching from one active AND gate (e.g., ) to another (e.g., ) = + + (consensus term) P P 5 of 2 Another Example (four variables) = + + = of 2 8

9 Circuit with a Static- Hazard P P P second path ++P first path + P+P Product of sums: static- hazard Output is supposed to remain constant at logic when input variable changes its value, but instead the output undergoes a short change to logic 7 of 2 Circuit with a Static- Hazard P P P ++P + P+P P + ++P time 8 of 2 9

10 Dynamic Hazards Dynamic hazard: Output signal is supposed to change or but a short oscillation occurs before the output settles to its new logic value. Occurs if there are multiple paths with different delays from the changing input to the changing output. In practice many input variables, multiple outputs; solved by computer programs 9 of 2 Example of Dynamic Hazard slow second path slower third path oscillation in output: first path Change occurs at input and propagates to output along three paths with different delays 2 of 2

11 Example of Dynamic Hazard slow slower : Change occurs at input and propagates to output along three paths with different delays 2 of 2

Chapter 2 Combinational Circuits

Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits