Elektrische Parameter Grundlagen der technischen Informatik

Transcription

1 Elektrische Parameter Grundlagen der technischen Informatik Wintersemester 28/9 Folien basierend auf F. Vahid und S. Werner Wintersemester 28/9

2 Review - Multiple-Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c, G = ab + bc a b c F a b c F G G (a) Option : Separate circuits (b) Option 2: Shared gates Wintersemester 28/9 2

3 Review - Combinational Logic Design Process Step : Capture behavior Step Capture the function Description Create a truth table or equations, whichever is most natural for the given problem, to describe the desired behavior of each output of the combinational logic. Step 2: Convert to circuit 2A: Create equations 2B: Implement as a gatebased circuit This substep is only necessary if you captured the function using a truth table instead of equations. Create an equation for each output by ORing all the minterms for that output. Simplify the equations if desired. For each output, create a circuit corresponding to the output s equation. (Sharing gates among multiple outputs is OK optionally.) Wintersemester 28/9 3

4 Review - Decoders and Muxes Decoder: Popular combinational logic building block, in addition to logic gates Converts input binary number to one high output 2-input decoder: four possible input binary numbers So has four outputs, one for each possible input binary number Internal design AND gate for each output to detect input combination Decoder with enable e Outputs all if e= Regular behavior if e= n-input decoder: 2 n outputs i i i d d i d2 i d3 i i i i ii ii i d d d2 d3 d d d2 d3 i i d d d2 d3 d i i i i d d2 e d3 i i e d d d2 d3 d d d2 d3 Wintersemester 28/9 4

5 Ranges for logical values Low: signal must be smaller than the upper border of the Low range High: signal must be higher than the lower border of the High range these two areas are separated by a third area (thus U L,max U H,min ) so that a corrupted logical signal might be recognized U H,max U H,min Range for logical Logic values undefined U L,max U L,min Range for logical Wintersemester 28/9 5

6 Typical voltage ranges for logic gates Logical Low Logical High TTL circuits.7 V V CMOS circuits.5 V 3.3 V Wintersemester 28/9 6

7 Example: timing diagram for the conjunction X=AB A B X Wintersemester 28/9 7

8 Example: timing diagram for the disjunction X=A+B Wintersemester 28/9 8

9 Example: propagation delays for an inverter U in U out t High Low High change of Input signal t PLH output response to inputs change change of Input signal t PHL output response to inputs change t Low Output goes from low -> high Output goes from high -> low Keep in mind: it is the output that rules Wintersemester 28/9 9

10 Example: propagation delays for an inverter U in High U out t t Low High Low t PLH <!!! t PHL Wintersemester 28/9

11 Rise time and fall time U in High U out Signals need time to fall => fall time t F Signals need time to rise => rise time t R t t Low High Low Wintersemester 28/9

12 Extra - Why rise and fall time? Terminals of transistor have a capacitance Inputs of a logic gate are connected to (gate) terminal of transistor Output of logic gate is input of next logic gate output of logic gate connected to capacitance Change of output signal = charge/discharge capacitance INV Wintersemester 28/9 2

13 How to calculate t R and t F? U out 9% % t R t F t To calculate t R and t F measure the actual times for the signal having % and 9% of the actual voltage. t R =t(u=.9 U max ) t (U=. U max ) t F =t(u=. U max ) t (U=.9 U max ) Keep in mind: not neccessarily t F = t R Wintersemester 28/9 3

14 Propagation delays and signal flanks U input t 9% 5% % U out Now: several possibilities to measure delays, e.g.:?? Input starts changing to ouput starts changing?? Input starts changing to ouput ends changing?? etc... t 9% 5% % Wintersemester 28/9 4

15 Propagation delays and signal flanks U input t 9% 5% % U out t PLH t PHL Propagation delays are measured as the time between the input signal being 5% of the maximum voltage and the output voltage being 5% of the maximum voltage t 9% 5% % Wintersemester 28/9 5

16 Example: Propagation delays of combinational circuits D C B A A+B+C K=A+B+C A B C D X D E=D Theoretical result for four different input states Implementation of x=(a+b+c) D X X=E K All gates have the same propagation delays: t PLH =t PHL =t PL =ns Assign: E=D K=A+B+C X=E K Wintersemester 28/9 6

17 Timing diagram A B C D E K X I I I I I I I t P t P t T= 2t P t P t T= 2t P t P E=D K=A+B+C X=E K D C B A The circuit is called a regular two layer circuit, as any input signal has to pass exactly two elements with a fixed transition time for all Grundlagen possible der Technische input Informatik combinations of t 7 Wintersemester 28/9 T =2 t P. D A+B+C X

18 Timing diagram for a different implementation D C B A W Z Y X Different implementation of f = (A+B+C) D A B C D Z A+B+C X the total propagation delay for this input state is t p =3 ns. Wintersemester 28/9 8

19 Example for glitch Consider the following implementation of a function X=(A+B)C and the given input sequence C A B Y X time A B C X t t t2 t3 Obviously the output of a circuit implementing this function should remain for the given input sequence. Now: Consider the given implementation propagation delays of ns Draw the timing diagram Wintersemester 28/9 9

20 Example for glitch Consider the following implementation of a function X=(A+B)C and the given input sequence C A B Y X time A B C X t t t2 t3 the information about C going up reaches the last gate by t P earlier than the information about A going down. Wintersemester 28/9 2

21 A B C Y X Example for glitch Consider the following implementation of a function X=(A+B)C and the given input sequence C A B Y X A B C X ns ns glitches might trigger unwanted states in the circuit some-where else, so they must not be ignored Wintersemester 28/9 2

22 Problems of power dissipation Continuously increasing performance demands Increasing power dissipation of technical devices Today: power dissipation is a main problem High Power dissipation leads to: Reduced time of operation High efforts for cooling Higher weight (batteries) Increasing operational costs Reduced mobility Reduced reliability Wintersemester 28/9 22

23 Trends for power dissipation Nuclear Reactor Hot Plate Source: Wintersemester 28/9 23

24 Power consumption in CMOS Two dominating forms of power consumption: Dynamic power consumption Depends on circuit activity See next slides Static (leakage) power consumption Always present Rising importance Wintersemester 28/9 24

25 Dynamic power consumption Voltage (Volt, V) Current (Ampere, A) Energy Water pressure (bar) Water quantity per second (liter/s) Amount of Water C L Wintersemester 28/9 25

26 Dynamic power consumption Voltage (Volt, V) Current (Ampere, A) Energy Water pressure (bar) Water quantity per second (liter/s) Amount of Water C L Power/Energy only consumed if output changes Wintersemester 28/9 26

27 Example: Low Power Strategy Dynamic power dissipation: any calculation has power costs Idea: avoid unnecessary calculations Problem: If sel selects A, multiplication was not necessary Solution: AND inputs to multiplier with sel new values for multiplier only when needed B A sel B A sel X Wintersemester 28/9 multiplier X mux muxout muxout 27

28 Was haben Sie heute gelernt? Wertebereiche für Spannung für logische Signale Signalverzögerungszeiten Leistungsverbrauch in digitalen Schaltungen Wintersemester 28/9 28