# Logic families (TTL, CMOS)

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 Logic families (TTL, CMOS) When you work with digital IC's, you should be familiar, not only with their logical operation, but also with such operational properties as voltage levels, noise immunity, power dissipation, fan-out, and propagation delays. DC Supply Voltage The nominal value of the dc supply voltage for TTL (transisitor-transistor logic) and CMOS (complementary metal-oxide semiconductor) devices is +5V. Although ommitted from logic diagrams for simplicity, this voltage is connected to Vcc or VDD pin of an IC package and ground is connected to the GND pin. TTL Logic Levels B431 Principles of Digital Systems : assan Parchizadeh Page 1

2 CMOS Logic Levels Noise Immunity Noise is the unwanted voltage that is induced in electrical circuits and can present a threat to the poor operation of the circuit. Wires and other conductors within a system can pickup stray high-frequency electromagnetic radiation from adjacent conductors in which currents are changing rapidly or from many other sources external to the system. In order not to be adversely effected by noise, a logic circuit must have a certain amount of 'noise immunity'. This is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing its output state. Consider Now Consider B431 Principles of Digital Systems : assan Parchizadeh Page 2

3 Noise Margin A measure of a circuit's noise immunity is called 'noise margin' which is expressed in volts. There are two values of noise margin specified for a given logic circuit: the IG (V N ) and LOW (V NL ) noise margins. These are defined by following equations : V N = V O (Min) - V I (Min) V NL = V IL (Max) - V OL (Max) Example : Determine the noise margins for TTL and CMOS using the information given above. TTL : V I (Min) = 2.0 V, V IL (Max) = 0.8 V, V O (Min) = 2.4 V, V OL (Max) = 0.4 V V N = V O (Min) - V I (Min) = 2.4 V 2.0 V = 0.4 V V NL = V IL (Max) - V OL (Max) = 0.8 V 0.4 V = 0.4 V CMOS : V I (Min) = 3.5 V, V IL (Max) = 1.5 V, V O (Min) = 4.9 V, V OL (Max) = 0.1 V V N = V O (Min) - V I (Min) = 4.9 V 3.5 V = 1.4 V V NL = V IL (Max) - V OL (Max) = 1.5 V 0.1 V = 1.4 V Power Dissipation A logic gate draws I CC current from the supply when the gate is in the IG output state, draws I CCL current from the supply in the LOW output state. 5V 5V I CC I CCL L X L 0V 0V Average power is PD = V CC I CC where I CC = (I CC + I CCL ) / 2 B431 Principles of Digital Systems : assan Parchizadeh Page 3

4 Example : A certain gate draws 2 ma when its output is IG and 3.6 ma when its output is LOW. What is its average power disspiation if V CC is 5 V and the gate is operated on a 50% duty cycle. I CC = ( I CC + I CCL )/2 = ( 2 ma ma ) / 2 = 2.8 ma PD = V CC I CC = 5 V * 2.8 ma = 14 mw Propagation Delay time When a signal passes ( propagates ) through a logic circuit, it always experiences a time delay as shown below. A change in the output level always occurs a short time, called 'propagation delay time', later than the change in the input level that caused it. input output t PL t PL Loading and Fan Out of Gates When the output of a logic gate is connected to one or more inputs of other gates, a load on the driving gate is created. There is a limit to the number of load gates that a given gate can drive. This limit is called the 'Fan-Out' of the gate. TTL Loading : A TTL driving gate, when IG, sources current (I Source ) into a load gate input (I I ) and sinks current (I OL ) from the load gate in the LOW state ((I Sink ). B431 Principles of Digital Systems : assan Parchizadeh Page 4 0 V Current sourcing

5 CMOS Loading : Loading CMOS differs from TTL because the fieldeffect-transistors (FET used in CMOS logic present a predominantly capacitive load to the driving gate. In this case the limitations are charging and discharging times associated time with the output resistance of the driving gate and input capacitance of the load gate. TTL Circuits TTL Inverter : Open Collector : Gates with TriState output : B431 Principles of Digital Systems : assan Parchizadeh Page 5

6 CMOS Circuits CMOS Inverter : Open Drain : CMOS Gates with TriState output : B431 Principles of Digital Systems : assan Parchizadeh Page 6

7 Schmitt triggers Many logic elements (flip-flops, monostables, etc.) require fast rising and falling edges for reliable operation. Edges can be degraded for a variety of reasons ; stray capacitance or even a signal from some slow external device. The schmitt trigger always gives fast edges on its output signal regardless of the input edge speed. The transfer functions of a schmitt trigger gate, is shown below. B431 Principles of Digital Systems : assan Parchizadeh Page 7

### Appendix B Page 1 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS)

Appendix B Page 1 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS) See page 3 See page 3 See page 7 See page 14 See page 9 See page 16 See page 10 TEXAS INSTRUMENTS LTD have given their

### Abu Dhabi Men s College, Electronics Department. Logic Families

bu Dhabi Men s College, Electronics Department Logic Families There are several different families of logic gates. Each family has its capabilities and limitations, its advantages and disadvantages. The

### Logic Families. A-PDF Split DEMO : Purchase from to remove the watermark. 5.1 Logic Families Significance and Types. 5.1.

A-PDF Split DEMO : Purchase from www.a-pdf.com to remove the watermark 5 Logic Families Digital integrated circuits are produced using several different circuit configurations and production technologies.

### Microcontroller Systems. ELET 3232 Topic 13: Load Analysis

Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission

### Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates

Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates Learning Outcome: an ability to analyze and design CMOS logic gates Learning Objectives: 1-1. convert numbers from one base (radix) to another:

### AC/DC to Logic Interface Optocouplers Technical Data

H AC/DC to Logic Interface Optocouplers Technical Data HCPL-37 HCPL-376 Features Standard (HCPL-37) and Low Input Current (HCPL-376) Versions AC or DC Input Programmable Sense Voltage Hysteresis Logic

### Module-1: Logic Families Characteristics and Types. Table of Content

1 Module-1: Logic Families Characteristics and Types Table of Content 1.1 Introduction 1.2 Logic families 1.3 Positive and Negative logic 1.4 Types of logic families 1.5 Characteristics of logic families

### Logic signal voltage levels

Logic signal voltage levels Logic gate circuits are designed to input and output only two types of signals: "high" (1) and "low" (0), as represented by a variable voltage: full power supply voltage for

### Obsolete Product(s) - Obsolete Product(s)

HEX INVERTER (OPEN DRAIN) HIGH SPEED: t PD = 10ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) WIDE OPERATING VOLTAGE RANGE:

### Schematic V F HCPL-7601/11 SHIELD. USE OF A 0.1 µf BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1).

CMOS/TTL Compatible, Low Input Current, High Speed, High CMR Optocoupler Technical Data HCPL-7601 HCPL-7611 Features Low Input Current Version of HCPL-2601/11 and 6N137 Wide Input Current Range: I F =

### CD54/74HC74, CD54/74HCT74

CD54/74HC74, CD54/74HCT74 Data sheet acquired from Harris Semiconductor SCHS124A January 1998 - Revised May 2000 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger Features Description [ /Title

### PLASTIC SILICON OPTOLOGIC PHOTOSENSOR

PACKAGE DIMENSIONS 0.75 (.) Ø 0.065 (.65) 0.00 (.5) 0.00 (5.08) Ø 0.095 (.) 0.00 (.5) 0.500 (.7) MIN 0.00 (0.5) SQ. 3X 0.075 (.90) X 0.05 (0.6) Part Number Definitions Color Code QSE56 Totem-Pole, buffer

### M74HCT02TTR QUAD 2-INPUT NOR GATE

QUAD 2-INPUT NOR GATE HIGH SPEED: t PD = 15 ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) BALANCED PROPAGATION

### 74LVC1G07-Q100. Buffer with open-drain output. The 74LVC1G07-Q100 provides the non-inverting buffer.

Rev. 2 7 December 2016 Product data sheet 1. General description The provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain outputs to implement

### Obsolete Product(s) - Obsolete Product(s)

QUAD 2-INPUT NAND GATE HIGH SPEED: t PD = 12ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) BALANCED PROPAGATION

### M74HC165TTR 8 BIT PISO SHIFT REGISTER

8 BIT PISO SHIFT REGISTER HIGH SPEED : t PD = 15 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

### Obsolete Product(s) - Obsolete Product(s)

HEX BUFFER/CONVERTER (INVERTING) PROPAGATION DELAY TIME t PD = 40ns (TYP.) at V DD = 10V C L = 50pF HIGH TO LOW LEVEL LOGIC CONVERSION MULTIPLEXER: 1 TO 6 OR 6 TO 1 HIGH "SINK" AND "SOURCE" CURRENT CAPABILITY

### Obsolete Product(s) - Obsolete Product(s)

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER HIGH SPEED: f MAX = 250MHz (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 8µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN.), V IL = 0.8V (MAX.)

### HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

HIGH SPEED- MBit/s DESCRIPTION The, /6 single-channel and /6 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable

### ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture

### Logic C1 TTL Buffer Level Shifter. Logic C2. Logic C3. Logic C4

Features Functional Schematic High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost 4 mm, 20-lead PQFN Package 100% Matte

### HIGH LOW Astable multivibrators HIGH LOW 1:1

1. Multivibrators A multivibrator circuit oscillates between a HIGH state and a LOW state producing a continuous output. Astable multivibrators generally have an even 50% duty cycle, that is that 50% of

### Obsolete Product(s) - Obsolete Product(s)

7 STAGE BINARY COUNTER HIGH SPEED : f MAX = 79 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

### HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

DESCRIPTION The, /6 single-channel and /6 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This

### M74HCT244TTR OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)

OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) HIGH SPEED: t PD = 15 ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V

### 8-bit shift register and latch driver

8-bit shift register and latch driver The BU2114 and BU2114F are CMOS ICs with low power consumption, and are equipped with an 8-bit shift register latch. Data in the shift register can be latched asynchronously.

### 30 A Low-Side RF MOSFET Driver IXRFD631

A Low-Side RF MOSFET Driver IXRFD Features High Peak Output Current Low Output Impedance Low Quiescent Supply Current Low Propagation Delay High Capacitive Load Drive Capability Wide Operating Voltage

### Low-power configurable multiple function gate

Rev. 9 7 December 2016 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic

### Obsolete Product(s) - Obsolete Product(s)

QUAD 2 INPUT NAND GATE PROPAGATION DELAY TIME t PD = 60ns (Typ.) at V DD = 10V BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V

### M74HC10TTR TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE HIGH SPEED: t PD = 8ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

### Obsolete Product(s) - Obsolete Product(s)

QUAD 2-INPUT NAND GATE HIGH SPEED: t PD = 8ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

### Agilent HCPL-3100/HCPL-3101 Power MOSFET/IGBT Gate Drive Optocouplers

Agilent HCPL/HCPL Power MOSFET/IGBT Gate Drive Optocouplers Data Sheet Description The HCPL/ consists of an LED* optically coupled to an integrated circuit with a power output stage. These optocouplers

### HCF4072B DUAL 4 INPUT OR GATE

DUAL 4 INPUT OR GATE MEDIUM SPEED OPERATION : t PD = 60ns (TYP.) at DD = 10 QUIESCENT CURRENT SPECIFIED UP TO 20 5, 10 AND 15 PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I I = 100nA (MAX) AT DD = 18 T A =

### OLS249: Radiation-Tolerant Phototransistor Hermetic Surface-Mount Optocoupler

DATA SHEET OLS249: Radiation-Tolerant Phototransistor Hermetic Surface-Mount Optocoupler Features Hermetic SMT package 1500 DC electrical isolation High CTR Small package size High reliability and rugged

### AND ITS APPLICATIONS M.C.SHARMA

AND ITS APPLICATIONS M.C.SHARMA 555 TIMER AND ITS APPLICATIONS BY M. C. SHARMA, M. Sc. PUBLISHERS: BUSINESS PROMOTION PUBLICATIONS 376, Lajpat Rai Market, Delhi-110006 By the same author Transistor Novelties

### ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

### PRESENTATION ON 555 TIMER A Practical Approach

PRESENTATION ON 555 TIMER A Practical Approach By Nagaraj Vannal Assistant Professor School of Electronics Engineering, K.L.E Technological University, Hubballi-31 nagaraj_vannal@bvb.edu 555 Timer The

### Obsolete Product(s) - Obsolete Product(s)

SINGLE INVERTER (OPEN DRAIN) HIGH SPEED: t PD = 3.7ns (TYP.) at V CC =5V LOW POWER DISSIPATION: I CC =1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH =V NIL = 28% V CC (MIN.) POWER DOWN PROTECTION ON

### Obsolete Product(s) - Obsolete Product(s)

DUAL BINARY UP COUNTER MEDIUM SPEED OPERATION : 6MHz (Typ.) at 10V POSITIVE -OR NEGATIVE- EDGE TRIGGERING SYNCHRONOUS INTERNAL CARRY PROPAGATION QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC

### Obsolete Product(s) - Obsolete Product(s)

HIGH SPEED: f MAX = 180 MHz (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 4 µa (MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28% V CC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT

### The 74LVC1G34 provides a low-power, low-voltage single buffer.

Rev. 6 5 December 2016 Product data sheet 1. General description The provides a low-power, low-voltage single buffer. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use

### SP26LV431 HIGH SPEED +3.3V QUAD RS-422 DIFFERENTIAL LINE DRIVER

HIGH SPEED +3.3V QUAD RS-422 DIFFERENTIAL LINE DRIVER JUNE 2011 REV. 1.1.1 GENERAL DESCRIPTION The SP26LV431 is a quad differential line driver that meets the specifications of the EIA standard RS-422

### 74LCX646TTR LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)

74LCX646 LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE) 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: t PD = 7.0 ns (MAX.) at V CC = 3V POWER DOWN PROTECTION

### HCF4050B HEX BUFFER/CONVERTER (NON INVERTING)

HEX BUFFER/CONVERTER (NON INVERTING) PROPAGATION DELAY TIME : t PD = 40ns (TYP.) at V DD = 10V C L = 50pF HIGH TO LOW LEVEL LOGIC CONVERSION HIGH "SINK" AND "SOURCE" CURRENT CAPABILITY QUIESCENT CURRENT

### UTC UNISONIC TECHNOLOGIES CO. LTD 1 INVERTER CIRCUITS

UTC CD469 INERTER CIRCUITS DESCRIPTION The UTC CD469 consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power consumption,

### CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423

CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Data sheet acquired from Harris Semiconductor SCHS1A September 1997 - Revised May 000 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

### HCPL0600, HCPL0601, HCPL0611, HCPL0637, HCPL0638, HCPL0639 High Speed-10 MBit/s Logic Gate Optocouplers

HCPL, HCPL, HCPL, HCPL7, HCPL8, HCPL9 High Speed- MBit/s Logic Gate Optocouplers Single Channel: HCPL, HCPL, HCPL Dual Channel: HCPL7, HCPL8, HCPL9 Features Compact SO8 package Very high speed- MBit/s

### Obsolete Product(s) - Obsolete Product(s)

HEX BUS BUFFER WITH 3 STATE OUTPUT INVERTING HIGH SPEED: t PD = 9 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL

### 8-BIT SERIAL-INPUT SHIFT REGISTER WITH LATCHED 3-STATE OUTPUTS High-Performance Silicon-Gate CMOS

8-BIT SERIAL-INPUT SHIFT REGISTER WITH LATCHED -STATE OUTPUTS High-Performance Silicon-Gate CMOS The IN74HC4094 is identical in pinout to the LS/ALS4094. The device inputs are compatible with standard

### Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

### Obsolete Product(s) - Obsolete Product(s)

OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) HIGH SPEED: t PD = 10 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.)

### Dual non-inverting Schmitt trigger with 5 V tolerant input

Rev. 9 15 December 2016 Product data sheet 1. General description The provides two non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply

### HCF4020B RIPPLE-CARRY BINARY COUNTER/DIVIDERS 14 STAGE

RIPPLE-CARRY BINARY COUNTER/DIVIDERS 14 STAGE MEDIUM SPEED OPERATION: 16MHz (Typ.) at V DD = 10V FULLY STATIC OPERATION COMMON RESET BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS

### Obsolete Product(s) - Obsolete Product(s)

SINGLE 2-INPUT NAND GATE 5V TOLERANT INPUTS HIGH SPEED: t PD = 4.7ns (MAX.) at V CC =3V LOW POWER DISSIPATION: I CC =1µA (MAX.)atT A =25 C POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT

### INTEGRATED CIRCUITS. 74LVT14 3.3V Hex inverter Schmitt trigger. Product specification 1996 Aug 28 IC24 Data Handbook

INTEGRATED CIRCUITS 1996 Aug 28 IC24 Data Handbook DESCRIPTION The is a high-performance BiCMOS product designed for V CC operation at 3.3V. They are capable of transforming slowly changing input signals

### Obsolete Product(s) - Obsolete Product(s)

QUAD 2-INPUT AND GATE HIGH SPEED: t PD = 4.7 ns (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 2 µa (MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS: V IH = 2V (MIN.), V IL = 0.8V (MAX) POWER DOWN PROTECTION

### Design considerations (D)

7/31/2011 15 Design considerations (D) In order to properly design a system, the designer must consider other items than just the logic of the circuit. We will discuss: Power onsumption Propagation delays

### Dual Passive Input Digital Isolator. Features. Applications

Dual Passive Input Digital Isolator Functional Diagram Each device in the dual channel IL611 consists of a coil, vertically isolated from a GMR Wheatstone bridge by a polymer dielectric layer. A magnetic

### 74AHC1G79; 74AHCT1G79

Rev. 6 23 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge

### ASTABLE MULTIVIBRATOR

555 TIMER ASTABLE MULTIIBRATOR MONOSTABLE MULTIIBRATOR 555 TIMER PHYSICS (LAB MANUAL) PHYSICS (LAB MANUAL) 555 TIMER Introduction The 555 timer is an integrated circuit (chip) implementing a variety of

### High Current MOSFET Toggle Switch with Debounced Push Button

Set/Reset Flip Flop This is an example of a set/reset flip flop using discrete components. When power is applied, only one of the transistors will conduct causing the other to remain off. The conducting

### LM555 and LM556 Timer Circuits

LM555 and LM556 Timer Circuits LM555 TIMER INTERNAL CIRCUIT BLOCK DIAGRAM "RESET" And "CONTROL" Input Terminal Notes Most of the circuits at this web site that use the LM555 and LM556 timer chips do not

### ECE 301 Digital Electronics

ECE 301 Digital Electronics Constraints in Logic Circuit Design (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and

### Practice Homework Problems for Module 1

Practice Homework Problems for Module 1 1. Unsigned base conversions (LO 1-1). (a) (2C9E) 16 to base 2 (b) (1101001) 2 to base 10 (c) (1101001) 2 to base 16 (d) (8576) 10 to base 16 (e) (A27F) 16 to base

### 74LVC273 Octal D-type flip-flop with reset; positive-edge trigger

INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger Supersedes data of 1996 Jun 06 IC24 Data Handbook 1998 May 20 FEATURES Wide supply voltage range of 1.2V to 3.6V Conforms to

### . HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC393 M74HC393 DUAL BINARY COUNTER. fmax = 72 MHz (TYP.) AT VCC =5V

M54HC393 M74HC393 DUAL BINARY COUNTER. HIGH SPEED fmax = 72 MHz (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY

### S-8130AA Series TEMPERATURE SWITCH IC WITH LATCH. Rev.2.2_00

Rev.2.2_00 TEMPERATURE SWITCH IC WITH LATCH Features Detection temperature : +60 to +95 C, 5 C step Detection accuracy : ±2.5 C V SS grounded temperature voltage output Low voltage operation : V DD (min.)=2.2

### 74AHC1G79-Q100; 74AHCT1G79-Q100

74AHC1G79-Q100; 74AHCT1G79-Q100 Rev. 2 23 September 2014 Product data sheet 1. General description 74AHC1G79-Q100 and 74AHCT1G79-Q100 are high-speed Si-gate CMOS devices. They provide a single positive-edge

### Type Ordering Code Package TLE 4226 G Q67000-A9118 P-DSO-24-3 (SMD) New type

Intelligent Sixfold -Side Switch TLE 4226 G Bipolar-IC Features Quad 50 outputs Dual 500 outputs Operating range S = 5 ± 5 % Output stages with power limiting Open-collector outputs Shorted load protected

### 74LVX04TTR LOW VOLTAGE CMOS HEX INVERTER WITH 5V TOLERANT INPUTS

LOW OLTAGE CMOS HEX INERTER WITH 5 TOLERANT INPUTS HIGH SPEED : t PD = 4.1ns (TYP.) at CC = 3.3 5 TOLERANT INPUTS INPUT OLTAGE LEEL : IL =0.8, IH =2 at CC =3 LOW POWER DISSIPATION: I CC = 2 µa (MAX.) at

### Industrial Inverters Switch Mode Power Supplies (SMPS)

H. Amp Output Current IGBT Gate Drive Optocoupler Technical Data HCPL- Features. A Minimum Peak Output Current kv/µs Minimum Common Mode Rejection (CMR) at V CM = V. V Maximum Low Level Output Voltage

### CMOS Schmitt Trigger A Uniquely Versatile Design Component

CMOS Schmitt Trigger A Uniquely Versatile Design Component INTRODUCTION The Schmitt trigger has found many applications in numerous circuits, both analog and digital. The versatility of a TTL Schmitt is

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. NC7SZ02 TinyLogic UHS 2-Input NOR Gate General Description The NC7SZ02 is

### 2-input NAND gate; open drain. The 74LVC1G38 provides a 2-input NAND function.

Rev. 8 7 December 2016 Product data sheet 1. General description The provides a 2-input NAND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device

### 74AC10B TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE HIGH SPEED: t PD = 4ns (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 2µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) 50Ω TRANSMISSION LINE DRIVING

19-0525; Rev 3; 1/07 EVALUATION KIT AVAILABLE Dual-/Triple-/Quad-Voltage, Capacitor- General Description The are dual-/triple-/quad-voltage monitors and sequencers that are offered in a small TQFN package.

### . HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC109 M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR. f MAX = 63 MHz (TYP.

M54HC109 M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR. HIGH SPEED f MAX = 63 MHz (TYP.) AT V CC =5V.LOW POWER DISSIPATION ICC =2µA (MAX.) AT TA =25 C.HIGH NOISE IMMUNITY V NIH =V NIL =28%V CC (MIN.)

### 74HC377; 74HCT General description. 2. Features and benefits. 3. Ordering information

Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)

### Obsolete Product(s) - Obsolete Product(s)

TRIPLE 3-INPUT NOR GATE HIGH SPEED: t PD = 4.1 ns (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 2 µa (MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28% V CC (MIN.) POWER DOWN PROTECTION ON

### . HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC4022 M74HC4022 OCTAL COUNTER/DIVIDER. fmax = 57 MHz (TYP.

M54HC4022 M74HC4022 OCTAL COUNTER/DIVIDER. HIGH SPEED fmax = 57 MHz (TYP.) at VCC = 5V.LOW POWER DISSIPATION I CC 4 µa (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY

### NC7WZ86 TinyLogic UHS Dual 2-Input Exclusive-OR Gate

TinyLogic UHS Dual 2-Input Exclusive-OR Gate General Description The NC7WZ86 is a dual 2-Input Exclusive-OR Gate from Fairchild s Ultra High Speed Series of TinyLogic. The device is fabricated with advanced

### TF2103. Half-Bridge Gate Driver. Description. Features. Applications. Ordering Information. Typical Application. Advance Info.

Features Floating high-side driver in bootstrap operation to 600V Drives two N-channel MOSFETs or IGBTs in a half bridge configuration 290mA source/600ma sink output current capability Outputs tolerant

### Police Siren Circuit using NE555 Timer

Police Siren Circuit using NE555 Timer Multivibrator: Multivibrator discover their own space in lots of applications as they are among the most broadly used circuits. The application can be anyone either

### TC4467 TC4468 LOGIC-INPUT CMOS QUAD DRIVERS TC4467 TC4468 TC4469 GENERAL DESCRIPTION FEATURES APPLICATIONS ORDERING INFORMATION

TC TC LOGIC-INPUT CMOS FEATURES High Peak Output Current....A Wide Operating Range.... to V Symmetrical Rise and Fall Times... nsec Short, Equal Delay Times... nsec Latchproof! Withstands ma Inductive

### CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI

### OLH5530/5531: Hermetic High-Speed Transistor Dual-Channel Optocoupler

DATA SHEET OLH5530/5531: Hermetic High-Speed Transistor Dual-Channel Optocoupler Features Dual-channel, rugged, reliable hermetic Dual Inline Package (DIP) Performance guaranteed over full military temperature

### 74VHC20 DUAL 4-INPUT NAND GATE

DUAL 4-INPUT NAND GATE HIGH SPEED: t PD = 3.3 ns (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 2 µa (MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28% V CC (MIN.) POWER DOWN PROTECTION ON

### Obsolete Product(s) - Obsolete Product(s)

8 BINARY COUNTER REGISTER WITH 3 STATE OUTPUT HIGH SPEED: f MAX = 61 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL

### Lecture 9 Transistors

Lecture 9 Transistors Physics Transistor/transistor logic CMOS logic CA 1947 http://www.extremetech.com/extreme/164301-graphenetransistors-based-on-negative-resistance-could-spell-theend-of-silicon-and-semiconductors

### . LOW POWER DISSIPATION .COMPATIBLE WITH TTL OUTPUTS M74HCT BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER (OPEN DRAIN, INVERTING OUTPUT)

8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER (OPEN DRAIN, INVERTING OUTPUT). LOW POWER DISSIPATION ICC =4µA (MAX.) AT TA =25 C.COMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN) V IL = 0.8V (MAX). OUTPUT DRIVE

### Designing Information Devices and Systems II Fall 2017 Note 1

EECS 16B Designing Information Devices and Systems II Fall 2017 Note 1 1 Digital Information Processing Electrical circuits manipulate voltages (V ) and currents (I) in order to: 1. Process information

### 74LVC2G General description. 2. Features and benefits. Dual 10 single-pole double-throw analog switch

Dual 10 single-pole double-throw analog switch Rev. 2 15 December 2016 Product data sheet 1. General description The is a dual low-ohmic single-pole double-throw analog switch suitable for use as an analog

### BAP1551 Gate Drive Board

Application Note and Datasheet for Half Bridge Inverters Figure 1: BAP1551 IGBT Gate Driver Board Patent Pending Introduction The BAP1551 Insulated Gate Bipolar Transistor (IGBT) Gate Drive Board (GDB)

### 54AC191 Up/Down Counter with Preset and Ripple Clock

54AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature

### APPLICATION NOTE.

APPLICATION NOTE High Speed Logic.......................... 2 MECL Products........................... 2 MECL Family Comparison.................. 3 Basic Design Considerations................ 4 Definitions

### CMOS Digital Integrated Circuits Analysis and Design

CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative

19-0622; Rev 0; 8/06 Dual-/Triple-/Quad-Voltage, Capacitor- General Description The are dual-/triple-/ quad-voltage monitors and sequencers that are offered in a small thin QFN package. These devices offer

### TOTAL IONIZING DOSE TEST REPORT No. 03T-RT54SX32S-T25JS004 March 12, 2003

J.J. Wang (408) 522-4576 jih-jong.wang@actel.com TOTAL IONIZING DOSE TEST REPORT No. 03T-RT54SX32S-T25JS004 March 12, 2003 I. SUMMARY TABLE Parameter Tolerance 1. Gross Functionality Passed 100 krad(si)