Computer Architecture (TT 2012)
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1 Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212
2 . Kroening: Computer Architecture (TT 212) 2
3 . Kroening: Computer Architecture (TT 212) 3
4 Introduction Emerging V&V Problem Advanced system attributes (on-board intelligence and adaptive control laws) will be required to accommodate emerging functional requirements. This will increase the size and complexity of control systems beyond the capability of current V&V practices. Typical Recent Commercial Aircraft Cost istribution Inter-System Communication Software & evelopment ependencies 2% Software Verification non-software 5% 3% Projected exponential increase in S/W size and complexity Verification will become an even larger challenge as systems become more highly integrated ISTRIBUTION STATEMENT A: Approved for Public Release; istribution Unlimited (Case Number: 88ABW ) 2. Kroening: Computer Architecture (TT 212) 4
5 Logic Gates Basic building block of digital circuitry Implement Boolean functions Gates have multiple inputs, usually one output Inputs/outputs are assigned a logical value or 1 Representation using voltage, for example: V voltage 1 3.3V voltage. Kroening: Computer Architecture (TT 212) 5
6 Abstract Switches x x Closed when x = 1 Closed when x = Idea: switch closed upper and lower port are connected. Kroening: Computer Architecture (TT 212) 6
7 Example: Inverter and NOR Inverter logical negation x x 1 1 (INV PIC) NOR disjunction with negation x y x y (NOR PIC). Kroening: Computer Architecture (TT 212) 7
8 Building an Inverter using Switches x y input output. Kroening: Computer Architecture (TT 212) 8
9 Building an Inverter using Switches open x y input output The 1 on the input closes the lower switch.. Kroening: Computer Architecture (TT 212)
10 Building an Inverter using Switches x y input output The on the input closes the upper switch.. Kroening: Computer Architecture (TT 212) 1
11 Building NOR using Switches x y inputs output z = x nor y. Kroening: Computer Architecture (TT 212) 11
12 Building NOR using Switches x y inputs output z = x nor y. Kroening: Computer Architecture (TT 212) 12
13 Building NOR using Switches x y inputs 2nd switch still open! output z = x nor y. Kroening: Computer Architecture (TT 212) 13
14 Building NOR using Switches x y inputs output z = x nor y. Kroening: Computer Architecture (TT 212) 14
15 Typical Implementations of Gates Examples: vacuum tube BJT: Bipolar Junction Transistor (used in TTL) FET: Field effect transistor (used in MOS) MOS = Metal Oxide Semiconductor CMOS: Complementary MOS. Kroening: Computer Architecture (TT 212) 15
16 NMOS source metal gate metal drain metal insulator SiO2 n doped n doped p doped substrate Implementation of a switch with doped silicon n/p-doping: excess of negative/positive charge carriers PMOS is dual to NMOS. Kroening: Computer Architecture (TT 212) 16
17 NMOS Open source n doped gate p doped substrate n doped drain insulator SiO 2 Voltage gate/source V: switch open (no current). Kroening: Computer Architecture (TT 212) 17
18 NMOS Closed source n doped gate n channel p doped substrate n doped drain insulator SiO 2 Voltage gate/source > V: switch closed (drain/source current possible). Kroening: Computer Architecture (TT 212) 18
19 Schematics rain rain Gate Gate Source NMOS Source PMOS. Kroening: Computer Architecture (TT 212) 1
20 CMOS Inverter V IN PMOS OUT IN is : PMOS closed, NMOS open OUT is 1 GN NMOS IN is 1: PMOS open, NMOS closed OUT is. Kroening: Computer Architecture (TT 212) 2
21 CMOS NOR V y x nor y x GN. Kroening: Computer Architecture (TT 212) 21
22 CMOS NAN V x y x nand y GN. Kroening: Computer Architecture (TT 212) 22
23 VLSI Prescott (24), nm process, 125 m. transistors on 122mm 2 Poulson (212): 32 nm process, 3.1 bn transistors on 544mm 2. Kroening: Computer Architecture (TT 212) 23
24 Flip-flops and Clocks So far: combinational circuitry Outputs are a function of the inputs But we would like to store data Flip-flops store data, controlled by a clock. Kroening: Computer Architecture (TT 212) 24
25 -Flip-Flop input (data) clock C state state negated most simplistic sequential building block: stores input for one clock period usually comes with (asynchronous) reset or set input signal. Kroening: Computer Architecture (TT 212) 25
26 Positive and Negative Edges raising falling C falling and rising clock edge. Kroening: Computer Architecture (TT 212) 26
27 -Flip-Flop with Positive Edge Triggering Transition table C Notation: the prime in means value in the next state positive edge, negative edge. Kroening: Computer Architecture (TT 212) 27
28 -Flip-Flop with Positive Edge Triggering C Changing only has an effect on the next (positive) clock edge!. Kroening: Computer Architecture (TT 212) 28
29 A High-level, Simplified View inputs combinational logic outputs current state registers next state. Kroening: Computer Architecture (TT 212) 2
30 Timing Analysis How much can we crank up the clock?. Kroening: Computer Architecture (TT 212) 3
31 Timing Analysis How much can we crank up the clock? What happens if we overdo it?. Kroening: Computer Architecture (TT 212) 3
32 Timing Requirements of a -Flip-Flop t w t phl clk t plh t s t h t s t h Input stable during setup phase t s before the edge Input stable during hold phase t h after the edge Output is stable after propagation phase t plh or t phl, resp., after the edge minimal clock period (width) t w. Kroening: Computer Architecture (TT 212) 31
33 Maximal Clock Frequency setup + hold time + propagation delay of the flip-flops + delay of the combinational circuitry (longest path!) = cycle time The maximal clock frequency is the inverse of the cycle time. Kroening: Computer Architecture (TT 212) 32
34 Example Component t p t s AN 7 ns - NAN 6 ns - OR 6 ns - Component t p t s NOR 5 ns - XOR ns - -Flipflop 11 ns 3 ns. Kroening: Computer Architecture (TT 212) 33
35 Example Component t p t s AN 7 ns - NAN 6 ns - OR 6 ns - Component t p t s NOR 5 ns - XOR ns - -Flipflop 11 ns 3 ns. Kroening: Computer Architecture (TT 212) 33
36 Example Component t p t s AN 7 ns - NAN 6 ns - OR 6 ns - Component t p t s NOR 5 ns - XOR ns - -Flipflop 11 ns 3 ns. Kroening: Computer Architecture (TT 212) 33
37 Example 3 ns Setup + hold time + 11 ns propagation elay of the flip-flops + 27 ns longest path = 41 ns cycle time Maximum clock frequency: 1 41ns Hz 24.4 MHz. Kroening: Computer Architecture (TT 212) 34
38 Pipelining : How can we increase the clock frequency? (will please marketing department) Reminder: the clock frequency is determined by the longest path between two -flip-flops.. Kroening: Computer Architecture (TT 212) 35
39 Pipelining : How can we increase the clock frequency? (will please marketing department) Reminder: the clock frequency is determined by the longest path between two -flip-flops. Idea: put a -flip-flop into that path!. Kroening: Computer Architecture (TT 212) 35
40 Example Pipelining Kroening: Computer Architecture (TT 212) 36
41 Example Pipelining Kroening: Computer Architecture (TT 212) 36
42 Example Pipelining Kroening: Computer Architecture (TT 212) 36
43 Example Pipelining 3 ns setup + hold time + 11 ns propagation delay of the flip-flops + 18 ns longest path = 32 ns cycle time Maximum clock frequency: 1 32ns 3125 Hz 31.3 MHz. Kroening: Computer Architecture (TT 212) 37
44 The Multi-Core Story. Kroening: Computer Architecture (TT 212) 38
45 The Multi-Core Story Increasing the clock speed requires raising voltage, with manifold increase in power! oubling the gate count doubles the power consumption Scaling micro-processors is easier by replicating CPU cores CPUs with 1 cores are around. Kroening: Computer Architecture (TT 212) 38
46 15 Static Current Frequency Source: AM. Kroening: Computer Architecture (TT 212) 3
47 Tilera Tile-GX1. Kroening: Computer Architecture (TT 212) 4
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