Advanced Digital Design
|
|
- Laureen Morrison
- 5 years ago
- Views:
Transcription
1 Advanced Digital Design The Need for a Design Style by A. Steininger Vienna University of Technology
2 Outline Skew versus consistency The need for a design style Hazards, Glitches & Runts Lecture "Advanced Digital Design" A. Steininger / TU Vienna 2
3 Design: Boolean Logic unambiguous functional description combinational logic: truth table sequential logic: state diagram technology agnostic temporal relations are not relevant (just sequence) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 3
4 Implementation: Physics There is a signal delay in all transistors through all interconnect This signal delay cannot be eliminated is indeterministic Lecture "Advanced Digital Design" A. Steininger / TU Vienna 4
5 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. (20cm/ns) Charging effects Charging of a capacitance with limited current takes time. ( t τ = RC) Charge movement Movement/diffusion of charges in semiconductor has limited speed. (0,1mm/s) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 5
6 Can we predict Delay? Gate Delay logic depth (<=optimization & mapping) data dependent delay (dynamic!) Interconnect Delay geometry (lengths, capacitances) vias, switches crosstalk (dynamic!) PVT Variations Process variations supply Voltage Temperature Lecture "Advanced Digital Design" A. Steininger / TU Vienna 6
7 Skew Prediction? Signal delay is difficult to predict, it even varies with operating conditions & data. The delays along two individual signal paths will never be the exactly the same. The (maximum) difference among two or more signal paths of interest termed skew is even more difficult to predict.?? Lecture "Advanced Digital Design" A. Steininger / TU Vienna 7
8 Skew and Consistency Data consistency When individual data items are interpreted together, these must belong to the same context they must be temporally correlated x- and y-coordinates of a moving object bits of a data word Skew distorts temporal correlation Lecture "Advanced Digital Design" A. Steininger / TU Vienna 8
9 Consistency an Example sending Delay receiving Skew receiving Lecture "Advanced Digital Design" A. Steininger / TU Vienna 9
10 Consistency & Glitches A 01 T & Y = A A 0 0 Everything OK for the steady state A dynamic analysis reveals glitches! Lecture "Advanced Digital Design" A. Steininger / TU Vienna 10
11 Pulse & Glitch Pulse: transition followed by opposite one positive : negative: PW Pulse width PW: time distance between these transitions Glitch: spurious pulse, usually undesired Lecture "Advanced Digital Design" A. Steininger / TU Vienna 11
12 Danger of a Glitch Glitch becomes dangerous when converted from spurious to steady state by using the transition (control signal) or by capturing its value (data signal) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 12
13 Types of Delay Pure delay (transport delay) simple time shift of all transitions pulses of any width are transported Inertial delay (component delay) transition only made if still required after delay pulses shorter than the delay are suppressed pure pure = inertial inertial Lecture "Advanced Digital Design" A. Steininger / TU Vienna 13
14 Delay types in Reality Pure delay much related to speed-of-light delay typical for wires with small RC increasing relevance for newer technology Inertial Delay much related to RC delay typical for gates (& wires with high RC) considered more relevant in practice Lecture "Advanced Digital Design" A. Steininger / TU Vienna 14
15 Runt Pulses when decreasing width PW of pulse applied to real circuit, large PW => pulse definitely recognized small PW => pulse definitely ignored (circuit s inertial delay) for some PW in between output will be very short and not reach full amplitude RUNT pulse VDD VSS a runt will be marginally recognized (may or may not) by subsequent inputs Lecture "Advanced Digital Design" A. Steininger / TU Vienna 15
16 Design: Boolean Logic unambiguous functional description combinational logic: truth table sequential logic: state diagram technology agnostic temporal relations are not relevant (just sequence) cannot be expressed! Lecture "Advanced Digital Design" A. Steininger / TU Vienna 16
17 The Consequences Boolean Logic describes I/O-mapping without consideration of time This implies continuously consistent inputs Skew inevitably causes inconsistency at the inputs and hence invalid dynamic outputs A B C F A glitches & runts Lecture "Advanced Digital Design" A. Steininger / TU Vienna 17
18 Why not avoid Skew? Just change a single bit at a time, then skew does not take effect Skew A Data permanently consistent ( Huffman Circuits ) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 18
19 Still glitches 1 X & K 1 Y 0 1 Z W & L >=1 A Glitch! single transition & M Forks turn single transitions into multiple ones! Lecture "Advanced Digital Design" A. Steininger / TU Vienna 19
20 Some First Conclusions Boolean Logic is a powerful method for functional description, but it does not take care of timing issues Timing issues are relevant, their ignorance leads to glitches, runts and inconsistent data We need a some form of discipline when designing a real circuit It makes sense to investigate further into glitches Lecture "Advanced Digital Design" A. Steininger / TU Vienna 20
21 Combinational Hazard Potential for glitches to occur in a circuit, depending on relative path delays Glitch is a manifestation of a hazard in a physical implementation of the circuit Actual manifestation may depend on input patterns actual delay values ( PVT variations) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 21
22 Types of Comb. Hazards static 1: input change retains output at 1, but negative glitch occurs static 0: same for output 0 and positive glitch dynamic: glitch occurs prior to desired output change Lecture "Advanced Digital Design" A. Steininger / TU Vienna 22
23 Static 0 Hazard Fundamental circuit structure: A 1 & Y = A A 0 fork inversion on one lane reconvergent into AND gate Lecture "Advanced Digital Design" A. Steininger / TU Vienna 23
24 Static 1 Hazard Fundamental circuit structure: 1 A >=1 Y = A A 1 fork inversion on one lane reconvergent into OR gate Lecture "Advanced Digital Design" A. Steininger / TU Vienna 24
25 Eliminating SC Hazards 1 A 1 & Y 2 How to choose delay constraints? no solution for constant delays solvable for edge-dependent delay: : 1 > 2 : 1 < 2 Lecture "Advanced Digital Design" A. Steininger / TU Vienna 25
26 Delay constraints Absolute timing contraints: keep skew between different paths within a certain limit generally not achievable Relative timing constraints: keep one path slower than the other generally possible, particularly in combination with input restrictions Lecture "Advanced Digital Design" A. Steininger / TU Vienna 26
27 Detection in Schematics A B C D 1 & 1 & >=1 >=1 & Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 27
28 Detection in Equation Y = [(C D) (B D)] (A B C) assign input values until B and B remains: A = 0; C = 0; D = 1 (enabling condition, need not exist) Y = B B static 0 hazard Lecture "Advanced Digital Design" A. Steininger / TU Vienna 28
29 Detection in KV-Diagram C A B static 1 hazards D remedy: redundant term static 0 hazards use KV for Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 29
30 Another Example YZ Y WX W Z YZ Y WX W Z X X F = (X Y Z) ( W Z) (W Y) F = (X Y Z) ( W Z) (W Y) (Y Z) ( W X Y) (W X Z) A Lecture "Advanced Digital Design" A. Steininger / TU Vienna 30
31 Systematic Approach define a notation to describe all scenarios of interest 9-valued logic study propagation extended truth table identify critical input scenarios satisfyability problem Lecture "Advanced Digital Design" A. Steininger / TU Vienna 31
32 9-valued logic 1 stable high 0 stable low rising edge falling edge S1 static-1-hazard S0 static-0-hazard D+ dynamic hazard, rising edge D- dynamic hazard, falling edge * any value at all ordering: S0 > 0, S1 > 1, D- >, D+ > Lecture "Advanced Digital Design" A. Steininger / TU Vienna 32
33 Truth Table AND & 0 1 S1 S0 D+ D- * 0 1 S1 S0 D+ D- * Lecture "Advanced Digital Design" A. Steininger / TU Vienna 33
34 Truth Table AND & 0 1 S1 S0 D+ D- * S1 S0 D+ D- * 0 S0 D- S0 S0 D- * 0 S0 D+ S0 D+ S0 * S1 0 S1 D- D+ S1 S0 D+ D- * S0 0 S0 S0 S0 S0 S0 S0 S0 * D+ 0 D+ S0 D+ D+ S0 D+ S0 * D- 0 D- D- S0 D- S0 S0 D- * * 0 * * * * * * * * Lecture "Advanced Digital Design" A. Steininger / TU Vienna 34
35 Propagation Analysis 1 A 1 & S0 Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 35
36 Single Input Change (SIC) So far: glitch due to single input signal changing Watch out for reconvergent paths: Fork: put single transition on concurring paths Join: recombine the two transitions, whose temporal relation has been distracted by skew If we allow more input signals to change we do not need the fork by moving the relative position of the inputs we gain even more freedom in arranging adverse timing conditions Lecture "Advanced Digital Design" A. Steininger / TU Vienna 36
37 Multiple-input change A B C D 1 & 1 & >=1 >=1 & Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 37
38 MIC Detection in Equ. Y = [(C D) (B D)] (A B C) assign input values for A and B: A = 1; B = 0 Y = C D static 0 hazard: Lecture "Advanced Digital Design" A. Steininger / TU Vienna 38
39 MIC Detect in KV-Diag. C A B There is a shortest path leading over other logic value D 1 functional hazard cannot be eliminated Lecture "Advanced Digital Design" A. Steininger / TU Vienna 39
40 Handling Static Hazards Elimination add terms (in sum-of-products implem.) not always possible for MIC Defeating disallow enabling conditions disallow critical transition(s) restriction of operation add timing constraints needs to be asymmetric Filtering (i.e. adding inertial delay) limited effect only, slows down circuit Lecture "Advanced Digital Design" A. Steininger / TU Vienna 40
41 Dynamic Comb. Hazard Fundamental circuit structure: glitch producer (010) 1 & A >=1 edge producer Lecture "Advanced Digital Design" A. Steininger / TU Vienna 41
42 Dynamic Comb. Hazard Fundamental circuit structure (dual): glitch producer (101) A 1 >=1 & edge producer Lecture "Advanced Digital Design" A. Steininger / TU Vienna 42
43 Dynamic combin hazards & A >=1 safe if 1 < 2 or 3 < 1 (no glitch) (edge masks glitch) safe if 1 > 2 or 3 > 1 all safe if 1 > 2, 3 or 1 < 2, 3 Lecture "Advanced Digital Design" A. Steininger / TU Vienna 43
44 Extension to MIC 1 & A >=1 A B C 1 & >=1 Lecture "Advanced Digital Design" A. Steininger / TU Vienna 44
45 Dynamic Hazards? A B C D 1 & 1 & >=1 >=1 & Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 45
46 Handling Dynamic Hazards Elimination not always possible for MIC Defeating relative constraints sufficient! in complex circuits unclear if constraining always possible: constraints may be contradicting BUT not all input patterns occur disallow enabling patterns disallow critical transitions Filtering Lecture "Advanced Digital Design" A. Steininger / TU Vienna 46
47 What about real HW? Example AOI gate: A & A B B C >=1 z C z Switching involves 2 transistors per input even more delay path combinations (p-stack, n-stack) may lead to tristate, short, glitch, proper cell layout is crucial! C A B Lecture "Advanced Digital Design" A. Steininger / TU Vienna 47
48 So why a Design Stlye? Skew is inevitable and unpredictable It causes inconsistent transient states Their logic evaluation causes runts & glitches These are harmful if converted to stable states There are methods to detect and prevent glitches; those are far from perfect Specific precautions are needed, as Boolean Logic does not help here we need some discipline, a design style Lecture "Advanced Digital Design" A. Steininger / TU Vienna 48
49 Without a Design Style combinational gates may, due to race conditions, receive contradictory signals simultaneously on different inputs, hence create glitch or runt pulses that may be converted into erroneous stable states or even cause metastability in storage loops. These glitches, runts and/or manifestations of metastability may propagate, and they may be subject to Byzantine interpretation, causing further erroneous states. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 49
Advanced Digital Design
Advanced Digital Design Introduction & Motivation by A. Steininger and M. Delvai Vienna University of Technology Outline Challenges in Digital Design The Role of Time in the Design The Fundamental Design
More informationAdvanced Digital Design
Advanced Digital Design The Synchronous Design Paradigm A. Steininger Vienna University of Technology Outline The Need for a Design Style The ideal Method Requirements The Fundamental Problem Timed Communication
More information14:332:231 DIGITAL LOGIC DESIGN. Gate Delays
4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all 23 Lecture #8: Timing Hazards Gate Delays hen the input to a logic gate is changed, the output will not
More informationINF3430 Clock and Synchronization
INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability
More informationMicrocircuit Electrical Issues
Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the
More informationTheory of Logic Circuits. Laboratory manual. Exercise 4
Zakład Mikroinformatyki i Teorii Automatów Cyfrowych Theory of Logic Circuits Laboratory manual Exercise 4 Asynchronous sequential logic circuits 2008 Krzysztof Cyran, Piotr Czekalski (edt.) 1. Introduction
More informationTiming analysis can be done right after synthesis. But it can only be accurately done when layout is available
Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate
More informationLecture 10. Circuit Pitfalls
Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski
More informationChapter 2 Combinational Circuits
Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,
More informationLecture 9: Clocking for High Performance Processors
Lecture 9: Clocking for High Performance Processors Computer Systems Lab Stanford University horowitz@stanford.edu Copyright 2001 Mark Horowitz EE371 Lecture 9-1 Horowitz Overview Reading Bailey Stojanovic
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More informationSynthesis of Combinational Logic
Synthesis of ombinational Logic 6.4 Gates F = xor Handouts: Lecture Slides, PS3, Lab2 6.4 - Spring 2 2/2/ L5 Logic Synthesis Review: K-map Minimization ) opy truth table into K-Map 2) Identify subcubes,
More informationA Survey of the Low Power Design Techniques at the Circuit Level
A Survey of the Low Power Design Techniques at the Circuit Level Hari Krishna B Assistant Professor, Department of Electronics and Communication Engineering, Vagdevi Engineering College, Warangal, India
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationNotes. 1. Midterm 1 Thursday February 24 in class.
Notes 1. Midterm 1 Thursday February 24 in class. Covers through text Sec. 4.3, topics of HW 4. GSIs will review material in discussion sections prior to the exam. No books at the exam, no cell phones,
More informationUNIT-III ASYNCHRONOUS SEQUENTIAL CIRCUITS TWO MARKS 1. What are secondary variables? -present state variables in asynchronous sequential circuits 2. What are excitation variables? -next state variables
More informationAdvanced Digital Design
Advanced Digital Design Limits of Synchonous Design by A. Steininger and M. Delvai Vienna University of Technology recall Previous Conclusion The purpose of a design style is to provide information for
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More informationUNIT-III GATE LEVEL DESIGN
UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms
More informationbus waveforms transport delta and simulation
bus waveforms transport delta and simulation Time Modelling and Data Flow Descriptions Modeling time in VHDL Different models of time delay Specify timing requirement Data flow descriptions Signal resolution
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
More informationECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics
ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit
Outline EES 5 - omponents and esign Techniques for igital Systems Lec 2 - Timing avid uller Electrical Engineering and omputer Sciences University of alifornia, erkeley Performance Limits of Synchronous
More informationEXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation)
EXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation) PURPOSE The purpose of this experiment is to introduce you to schematic capture and logic simulation. Primarily, you
More informationIJMIE Volume 2, Issue 3 ISSN:
IJMIE Volume 2, Issue 3 ISSN: 2249-0558 VLSI DESIGN OF LOW POWER HIGH SPEED DOMINO LOGIC Ms. Rakhi R. Agrawal* Dr. S. A. Ladhake** Abstract: Simple to implement, low cost designs in CMOS Domino logic are
More informationTopic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection
NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought
More information74F50729 Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
INTEGRATED CIRCUITS Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics 1990 Sep 14 IC15 Data Handbook FEATURES Metastable immune characteristics
More informationHAZARDS AND PULSE MODE SEQUENTIAL CIRCUITS
Chapter 19 HAZARDS AND PULSE MODE SEQUENTIAL CIRCUITS Ch19L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 1 Lesson 5 Dynamic Hazards, Essential Hazards and Pulse mode sequential
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers Friday s class will be a lecture rather
More informationPROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS
PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high
More informationThe Digital Abstraction
The Digital Abstraction 1. Making bits concrete 2. What makes a good bit 3. Getting bits under contract Handouts: Lecture Slides L02 - Digital Abstraction 1 Concrete encoding of information To this point
More information74F5074 Synchronizing dual D-type flip-flop/clock driver
INTEGRATED CIRCUITS Synchronizing dual D-type flip-flop/clock driver 1990 Sep 14 IC15 Data Handbook FEATURES Metastable immune characteristics Output skew guaranteed less than 1.5ns High source current
More informationLecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM
Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey
More informationSupply Voltage Supervisor TL77xx Series. Author: Eilhard Haseloff
Supply Voltage Supervisor TL77xx Series Author: Eilhard Haseloff Literature Number: SLVAE04 March 1997 i IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to
More informationVLSI Design I; A. Milenkovic 1
CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization Spring 2018 Timing Analysis Lecture 11: 1 Announcements Lab report guidelines are uploaded on CMS As part of the assignment for Lab 3 report Lab 4(A) prelab
More informationApplication and Analysis of Output Prediction Logic to a 16-bit Carry Look Ahead Adder
Application and Analysis of Output Prediction Logic to a 16-bit Carry Look Ahead Adder Lukasz Szafaryn University of Virginia Department of Computer Science lgs9a@cs.virginia.edu 1. ABSTRACT In this work,
More informationHigh-speed Serial Interface
High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications
More informationBASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows
Unit 3 BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows 1.Specification (problem definition) 2.Schematic(gate level design) (equivalence check) 3.Layout (equivalence
More informationThe Digital Abstraction
The Digital Abstraction 1. Making bits concrete 2. What makes a good bit 3. Getting bits under contract 1 1 0 1 1 0 0 0 0 0 1 Handouts: Lecture Slides, Problem Set #1 L02 - Digital Abstraction 1 Concrete
More informationInverting input R 2. R 1 Output
nalogue Electronics 8: Feedback and Op mps Last lecture we introduced diodes and transistors and an outline of the semiconductor physics was given to understand them on a fundamental level. We use transistors
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationCMOS Transistor and Circuits. Jan 2015 CMOS Transistor 1
CMOS Transistor and Circuits Jan 2015 CMOS Transistor 1 Latchup in CMOS Circuits Jan 2015 CMOS Transistor 2 Parasitic bipolar transistors are formed by substrate and source / drain devices Latchup occurs
More information! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
More informationIn this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems.
1 In this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems. The important concepts are related to setup and hold times of registers
More information1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as
BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered
More informationImplications of Slow or Floating CMOS Inputs
Implications of Slow or Floating CMOS Inputs SCBA4 13 1 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service
More informationGuaranteeing Silicon Performance with FPGA Timing Models
white paper Intel FPGA Guaranteeing Silicon Performance with FPGA Timing Models Authors Minh Mac Member of Technical Staff, Technical Services Intel Corporation Chris Wysocki Senior Manager, Software Englineering
More information6.004 Computation Structures Spring 2009
MIT OpenCourseWare http://ocw.mit.edu 6.004 Computation Structures Spring 009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. The Digital Abstraction
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers 1 General Table Lookup Synthesis A B 00
More informationPropagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationPropagation Delay, Circuit Timing & Adder Design
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationSURVEY AND EVALUATION OF LOW-POWER FULL-ADDER CELLS
SURVEY ND EVLUTION OF LOW-POWER FULL-DDER CELLS hmed Sayed and Hussain l-saad Department of Electrical & Computer Engineering University of California Davis, C, U.S.. STRCT In this paper, we survey various
More informationReading. Lecture 17: MOS transistors digital. Context. Digital techniques:
Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward
More informationModule -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
More informationNovel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology
Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology 1 Mahesha NB #1 #1 Lecturer Department of Electronics & Communication Engineering, Rai Technology University nbmahesh512@gmail.com
More informationIntegrated Circuits -- Timing Behavior of Gates
Integrated Circuits -- Timing ehavior of Gates Page 1 Gates Have Non-Linear Input/Output ehavior V cc V out 0V V in V cc Plotting Vout vs. Vin shows non-linear voltage behavior Page 2 Gates lso Don t React
More informationNano-Arch online. Quantum-dot Cellular Automata (QCA)
Nano-Arch online Quantum-dot Cellular Automata (QCA) 1 Introduction In this chapter you will learn about a promising future nanotechnology for computing. It takes great advantage of a physical effect:
More informationCHAPTER 6 DIGITAL INSTRUMENTS
CHAPTER 6 DIGITAL INSTRUMENTS 1 LECTURE CONTENTS 6.1 Logic Gates 6.2 Digital Instruments 6.3 Analog to Digital Converter 6.4 Electronic Counter 6.6 Digital Multimeters 2 6.1 Logic Gates 3 AND Gate The
More informationEE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 7. Clocked and self-resetting logic I
EE E6930 Advanced Digital Integrated Circuits Spring, 2002 Lecture 7. Clocked and self-resetting logic I References CBF, Chapter 8 DP, Section 4.3.3.1-4.3.3.4 Bernstein, High-speed CMOS design styles,
More informationAssociate In Applied Science In Electronics Engineering Technology Expiration Date:
PROGRESS RECORD Study your lessons in the order listed below. Associate In Applied Science In Electronics Engineering Technology Expiration Date: 1 2330A Current and Voltage 2 2330B Controlling Current
More informationINTEGRATED CIRCUITS. 74F786 4-bit asynchronous bus arbiter. Product specification Feb 14. IC15 Data Handbook
INTEGRATED CIRCUITS 1991 Feb 14 IC15 Data Handbook FEATURES Arbitrates between 4 asynchronous inputs Separate grant output for each input Common output enable On board 4 input AND gate Metastable free
More informationEE434 ASIC & Digital Systems
EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Spring 2015 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Lecture 4 More on CMOS Gates Ref: Textbook chapter
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Teaser. Pass Transistor Logic. Identify Function.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 1, 2018 Combination Logic: Pass Transistor Logic, and Performance 2 Pass Transistor
More informationChapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,
More informationChapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1
Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar
More informationThe Effect of Threshold Voltages on the Soft Error Rate. - V Degalahal, N Rajaram, N Vijaykrishnan, Y Xie, MJ Irwin
The Effect of Threshold Voltages on the Soft Error Rate - V Degalahal, N Rajaram, N Vijaykrishnan, Y Xie, MJ Irwin Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation
More informationModule 4: Combinational Logic Glitches and Hazards
Module 4: Combinational Logic Glitches and Hazards Wakerly: Chapter 4 (part 3) : ECEN 3233 r. Keith. Teague Spring 23 23 TIME RESPONSE in Combinational Networks emphasis on timing behavior of circuits
More informationBasic Logic Circuits
Basic Logic Circuits Required knowledge Measurement of static characteristics of nonlinear circuits. Measurement of current consumption. Measurement of dynamic properties of electrical circuits. Definitions
More informationZero Steady State Current Power-on-Reset Circuit with Brown-Out Detector
Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector Sanjay Kumar Wadhwa 1, G.K. Siddhartha 2, Anand Gaurav 3 Freescale Semiconductor India Pvt. Ltd. 1 sanjay.wadhwa@freescale.com,
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationECE 172 Digital Systems. Chapter 2 Digital Hardware. Herbert G. Mayer, PSU Status 6/30/2018
ECE 172 Digital Systems Chapter 2 Digital Hardware Herbert G. Mayer, PSU Status 6/30/2018 1 Syllabus l Term Sharing l Standard Forms l Hazards l Decoders l PLA vs. PAL l PROM l Bibliography 2 Product Term
More informationPower-Area trade-off for Different CMOS Design Technologies
Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Previously: Two XOR Gates. Pass Transistor Logic. Cascaded Pass Gates
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 2, 2017 Combination Logic: Pass Transistor Logic, and Performance 2 Previously:
More informationLecture #2 Solving the Interconnect Problems in VLSI
Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology
More informationIn this experiment you will study the characteristics of a CMOS NAND gate.
Introduction Be sure to print a copy of Experiment #12 and bring it with you to lab. There will not be any experiment copies available in the lab. Also bring graph paper (cm cm is best). Purpose In this
More informationLecture 9: Cell Design Issues
Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the
More informationIntroduction to CMOS VLSI Design (E158) Lecture 9: Cell Design
Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
More informationEC O4 403 DIGITAL ELECTRONICS
EC O4 403 DIGITAL ELECTRONICS Asynchronous Sequential Circuits - II 6/3/2010 P. Suresh Nair AMIE, ME(AE), (PhD) AP & Head, ECE Department DEPT. OF ELECTONICS AND COMMUNICATION MEA ENGINEERING COLLEGE Page2
More informationECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh
ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh NMOS-to-PMOS ratio,pmos are made β times larger than NMOS Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing
More informationUnderstanding and Minimizing Ground Bounce
Fairchild Semiconductor Application Note June 1989 Revised February 2003 Understanding and Minimizing Ground Bounce As system designers begin to use high performance logic families to increase system performance,
More informationIntroduction to CMOS VLSI Design (E158) Lecture 5: Logic
Harris Introduction to CMOS VLSI Design (E158) Lecture 5: Logic David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture 5 1
More informationFault Tolerance in VLSI Systems
Fault Tolerance in VLSI Systems Overview Opportunities presented by VLSI Problems presented by VLSI Redundancy techniques in VLSI design environment Duplication with complementary logic Self-checking logic
More informationName: Class: Date: 1. As more electronic systems have been designed using digital technology, devices have become smaller and less powerful.
Name: Class: Date: DE Midterm Review 2 True/False Indicate whether the statement is true or false. 1. As more electronic systems have been designed using digital technology, devices have become smaller
More information2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.
2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion
More informationEE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Lecture 13: Timing revisited
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 13: Timing revisited Announcements Homework 2 due today Quiz #2 on Monday Midterm project report due next Wednesday 2 1 Outline Last lecture
More informationLow-Power Digital CMOS Design: A Survey
Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with
More informationLecture 15 Analysis of Combinational Circuits
Lecture 15 Analysis of Combinational Circuits Designing Combinational Logic Circuits A logic circuit having 3 inputs, A, B, C will have its output HIGH only when a majority of the inputs are HIGH. Step
More informationCOMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
More informationModule-1: Logic Families Characteristics and Types. Table of Content
1 Module-1: Logic Families Characteristics and Types Table of Content 1.1 Introduction 1.2 Logic families 1.3 Positive and Negative logic 1.4 Types of logic families 1.5 Characteristics of logic families
More informationComputer-Based Project in VLSI Design Co 3/7
Computer-Based Project in VLSI Design Co 3/7 As outlined in an earlier section, the target design represents a Manchester encoder/decoder. It comprises the following elements: A ring oscillator module,
More informationTowards PVT-Tolerant Glitch-Free Operation in FPGAs
Towards PVT-Tolerant Glitch-Free Operation in FPGAs Safeen Huda and Jason H. Anderson ECE Department, University of Toronto, Canada 24 th ACM/SIGDA International Symposium on FPGAs February 22, 2016 Motivation
More information2014 Paper E2.1: Digital Electronics II
2014 Paper E2.1: Digital Electronics II Answer ALL questions. There are THREE questions on the paper. Question ONE counts for 40% of the marks, other questions 30% Time allowed: 2 hours (Not to be removed
More informationPHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag
PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationLecture 1. Tinoosh Mohsenin
Lecture 1 Tinoosh Mohsenin Today Administrative items Syllabus and course overview Digital systems and optimization overview 2 Course Communication Email Urgent announcements Web page http://www.csee.umbc.edu/~tinoosh/cmpe650/
More informationDesign Analysis of 1-bit Comparator using 45nm Technology
Design Analysis of 1-bit Comparator using 45nm Technology Pardeep Sharma 1, Rajesh Mehra 2 1,2 Department of Electronics and Communication Engineering, National Institute for Technical Teachers Training
More information