Advanced Digital Design

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1 Advanced Digital Design The Need for a Design Style by A. Steininger Vienna University of Technology

2 Outline Skew versus consistency The need for a design style Hazards, Glitches & Runts Lecture "Advanced Digital Design" A. Steininger / TU Vienna 2

3 Design: Boolean Logic unambiguous functional description combinational logic: truth table sequential logic: state diagram technology agnostic temporal relations are not relevant (just sequence) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 3

4 Implementation: Physics There is a signal delay in all transistors through all interconnect This signal delay cannot be eliminated is indeterministic Lecture "Advanced Digital Design" A. Steininger / TU Vienna 4

5 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. (20cm/ns) Charging effects Charging of a capacitance with limited current takes time. ( t τ = RC) Charge movement Movement/diffusion of charges in semiconductor has limited speed. (0,1mm/s) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 5

6 Can we predict Delay? Gate Delay logic depth (<=optimization & mapping) data dependent delay (dynamic!) Interconnect Delay geometry (lengths, capacitances) vias, switches crosstalk (dynamic!) PVT Variations Process variations supply Voltage Temperature Lecture "Advanced Digital Design" A. Steininger / TU Vienna 6

7 Skew Prediction? Signal delay is difficult to predict, it even varies with operating conditions & data. The delays along two individual signal paths will never be the exactly the same. The (maximum) difference among two or more signal paths of interest termed skew is even more difficult to predict.?? Lecture "Advanced Digital Design" A. Steininger / TU Vienna 7

8 Skew and Consistency Data consistency When individual data items are interpreted together, these must belong to the same context they must be temporally correlated x- and y-coordinates of a moving object bits of a data word Skew distorts temporal correlation Lecture "Advanced Digital Design" A. Steininger / TU Vienna 8

9 Consistency an Example sending Delay receiving Skew receiving Lecture "Advanced Digital Design" A. Steininger / TU Vienna 9

10 Consistency & Glitches A 01 T & Y = A A 0 0 Everything OK for the steady state A dynamic analysis reveals glitches! Lecture "Advanced Digital Design" A. Steininger / TU Vienna 10

11 Pulse & Glitch Pulse: transition followed by opposite one positive : negative: PW Pulse width PW: time distance between these transitions Glitch: spurious pulse, usually undesired Lecture "Advanced Digital Design" A. Steininger / TU Vienna 11

12 Danger of a Glitch Glitch becomes dangerous when converted from spurious to steady state by using the transition (control signal) or by capturing its value (data signal) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 12

13 Types of Delay Pure delay (transport delay) simple time shift of all transitions pulses of any width are transported Inertial delay (component delay) transition only made if still required after delay pulses shorter than the delay are suppressed pure pure = inertial inertial Lecture "Advanced Digital Design" A. Steininger / TU Vienna 13

14 Delay types in Reality Pure delay much related to speed-of-light delay typical for wires with small RC increasing relevance for newer technology Inertial Delay much related to RC delay typical for gates (& wires with high RC) considered more relevant in practice Lecture "Advanced Digital Design" A. Steininger / TU Vienna 14

15 Runt Pulses when decreasing width PW of pulse applied to real circuit, large PW => pulse definitely recognized small PW => pulse definitely ignored (circuit s inertial delay) for some PW in between output will be very short and not reach full amplitude RUNT pulse VDD VSS a runt will be marginally recognized (may or may not) by subsequent inputs Lecture "Advanced Digital Design" A. Steininger / TU Vienna 15

16 Design: Boolean Logic unambiguous functional description combinational logic: truth table sequential logic: state diagram technology agnostic temporal relations are not relevant (just sequence) cannot be expressed! Lecture "Advanced Digital Design" A. Steininger / TU Vienna 16

17 The Consequences Boolean Logic describes I/O-mapping without consideration of time This implies continuously consistent inputs Skew inevitably causes inconsistency at the inputs and hence invalid dynamic outputs A B C F A glitches & runts Lecture "Advanced Digital Design" A. Steininger / TU Vienna 17

18 Why not avoid Skew? Just change a single bit at a time, then skew does not take effect Skew A Data permanently consistent ( Huffman Circuits ) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 18

19 Still glitches 1 X & K 1 Y 0 1 Z W & L >=1 A Glitch! single transition & M Forks turn single transitions into multiple ones! Lecture "Advanced Digital Design" A. Steininger / TU Vienna 19

20 Some First Conclusions Boolean Logic is a powerful method for functional description, but it does not take care of timing issues Timing issues are relevant, their ignorance leads to glitches, runts and inconsistent data We need a some form of discipline when designing a real circuit It makes sense to investigate further into glitches Lecture "Advanced Digital Design" A. Steininger / TU Vienna 20

21 Combinational Hazard Potential for glitches to occur in a circuit, depending on relative path delays Glitch is a manifestation of a hazard in a physical implementation of the circuit Actual manifestation may depend on input patterns actual delay values ( PVT variations) Lecture "Advanced Digital Design" A. Steininger / TU Vienna 21

22 Types of Comb. Hazards static 1: input change retains output at 1, but negative glitch occurs static 0: same for output 0 and positive glitch dynamic: glitch occurs prior to desired output change Lecture "Advanced Digital Design" A. Steininger / TU Vienna 22

23 Static 0 Hazard Fundamental circuit structure: A 1 & Y = A A 0 fork inversion on one lane reconvergent into AND gate Lecture "Advanced Digital Design" A. Steininger / TU Vienna 23

24 Static 1 Hazard Fundamental circuit structure: 1 A >=1 Y = A A 1 fork inversion on one lane reconvergent into OR gate Lecture "Advanced Digital Design" A. Steininger / TU Vienna 24

25 Eliminating SC Hazards 1 A 1 & Y 2 How to choose delay constraints? no solution for constant delays solvable for edge-dependent delay: : 1 > 2 : 1 < 2 Lecture "Advanced Digital Design" A. Steininger / TU Vienna 25

26 Delay constraints Absolute timing contraints: keep skew between different paths within a certain limit generally not achievable Relative timing constraints: keep one path slower than the other generally possible, particularly in combination with input restrictions Lecture "Advanced Digital Design" A. Steininger / TU Vienna 26

27 Detection in Schematics A B C D 1 & 1 & >=1 >=1 & Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 27

28 Detection in Equation Y = [(C D) (B D)] (A B C) assign input values until B and B remains: A = 0; C = 0; D = 1 (enabling condition, need not exist) Y = B B static 0 hazard Lecture "Advanced Digital Design" A. Steininger / TU Vienna 28

29 Detection in KV-Diagram C A B static 1 hazards D remedy: redundant term static 0 hazards use KV for Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 29

30 Another Example YZ Y WX W Z YZ Y WX W Z X X F = (X Y Z) ( W Z) (W Y) F = (X Y Z) ( W Z) (W Y) (Y Z) ( W X Y) (W X Z) A Lecture "Advanced Digital Design" A. Steininger / TU Vienna 30

31 Systematic Approach define a notation to describe all scenarios of interest 9-valued logic study propagation extended truth table identify critical input scenarios satisfyability problem Lecture "Advanced Digital Design" A. Steininger / TU Vienna 31

32 9-valued logic 1 stable high 0 stable low rising edge falling edge S1 static-1-hazard S0 static-0-hazard D+ dynamic hazard, rising edge D- dynamic hazard, falling edge * any value at all ordering: S0 > 0, S1 > 1, D- >, D+ > Lecture "Advanced Digital Design" A. Steininger / TU Vienna 32

33 Truth Table AND & 0 1 S1 S0 D+ D- * 0 1 S1 S0 D+ D- * Lecture "Advanced Digital Design" A. Steininger / TU Vienna 33

34 Truth Table AND & 0 1 S1 S0 D+ D- * S1 S0 D+ D- * 0 S0 D- S0 S0 D- * 0 S0 D+ S0 D+ S0 * S1 0 S1 D- D+ S1 S0 D+ D- * S0 0 S0 S0 S0 S0 S0 S0 S0 * D+ 0 D+ S0 D+ D+ S0 D+ S0 * D- 0 D- D- S0 D- S0 S0 D- * * 0 * * * * * * * * Lecture "Advanced Digital Design" A. Steininger / TU Vienna 34

35 Propagation Analysis 1 A 1 & S0 Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 35

36 Single Input Change (SIC) So far: glitch due to single input signal changing Watch out for reconvergent paths: Fork: put single transition on concurring paths Join: recombine the two transitions, whose temporal relation has been distracted by skew If we allow more input signals to change we do not need the fork by moving the relative position of the inputs we gain even more freedom in arranging adverse timing conditions Lecture "Advanced Digital Design" A. Steininger / TU Vienna 36

37 Multiple-input change A B C D 1 & 1 & >=1 >=1 & Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 37

38 MIC Detection in Equ. Y = [(C D) (B D)] (A B C) assign input values for A and B: A = 1; B = 0 Y = C D static 0 hazard: Lecture "Advanced Digital Design" A. Steininger / TU Vienna 38

39 MIC Detect in KV-Diag. C A B There is a shortest path leading over other logic value D 1 functional hazard cannot be eliminated Lecture "Advanced Digital Design" A. Steininger / TU Vienna 39

40 Handling Static Hazards Elimination add terms (in sum-of-products implem.) not always possible for MIC Defeating disallow enabling conditions disallow critical transition(s) restriction of operation add timing constraints needs to be asymmetric Filtering (i.e. adding inertial delay) limited effect only, slows down circuit Lecture "Advanced Digital Design" A. Steininger / TU Vienna 40

41 Dynamic Comb. Hazard Fundamental circuit structure: glitch producer (010) 1 & A >=1 edge producer Lecture "Advanced Digital Design" A. Steininger / TU Vienna 41

42 Dynamic Comb. Hazard Fundamental circuit structure (dual): glitch producer (101) A 1 >=1 & edge producer Lecture "Advanced Digital Design" A. Steininger / TU Vienna 42

43 Dynamic combin hazards & A >=1 safe if 1 < 2 or 3 < 1 (no glitch) (edge masks glitch) safe if 1 > 2 or 3 > 1 all safe if 1 > 2, 3 or 1 < 2, 3 Lecture "Advanced Digital Design" A. Steininger / TU Vienna 43

44 Extension to MIC 1 & A >=1 A B C 1 & >=1 Lecture "Advanced Digital Design" A. Steininger / TU Vienna 44

45 Dynamic Hazards? A B C D 1 & 1 & >=1 >=1 & Y Lecture "Advanced Digital Design" A. Steininger / TU Vienna 45

46 Handling Dynamic Hazards Elimination not always possible for MIC Defeating relative constraints sufficient! in complex circuits unclear if constraining always possible: constraints may be contradicting BUT not all input patterns occur disallow enabling patterns disallow critical transitions Filtering Lecture "Advanced Digital Design" A. Steininger / TU Vienna 46

47 What about real HW? Example AOI gate: A & A B B C >=1 z C z Switching involves 2 transistors per input even more delay path combinations (p-stack, n-stack) may lead to tristate, short, glitch, proper cell layout is crucial! C A B Lecture "Advanced Digital Design" A. Steininger / TU Vienna 47

48 So why a Design Stlye? Skew is inevitable and unpredictable It causes inconsistent transient states Their logic evaluation causes runts & glitches These are harmful if converted to stable states There are methods to detect and prevent glitches; those are far from perfect Specific precautions are needed, as Boolean Logic does not help here we need some discipline, a design style Lecture "Advanced Digital Design" A. Steininger / TU Vienna 48

49 Without a Design Style combinational gates may, due to race conditions, receive contradictory signals simultaneously on different inputs, hence create glitch or runt pulses that may be converted into erroneous stable states or even cause metastability in storage loops. These glitches, runts and/or manifestations of metastability may propagate, and they may be subject to Byzantine interpretation, causing further erroneous states. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 49

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