EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Lecture 13: Timing revisited

Transcription

1 EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 13: Timing revisited Announcements Homework 2 due today Quiz #2 on Monday Midterm project report due next Wednesday 2 1

2 Outline Last lecture ECC in SRAM SRAM scaling options This lecture Back to timing Latch-based timing Variability and timing 3 4. Design for performance A. Timing 2

3 Flip-Flop Parameters D Q D PW m T H T SU Q T CQ Delays can be different for rising and falling data transitions 5 Latch Parameters D Q Unger and Tan Trans. on Comp. 10/86 D PW m T H T SU Q T CQ T DQ Delays can be different for rising and falling data transitions 6 3

4 Example Clock System Courtesy of IEEE Press, New York Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) - t JS Long-term - t JL Variation of the pulse width for level-sensitive clocking 8 4

5 Clock Skew and Jitter 1 t SK 2 t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin, if jitter is from the source Distribution-induced jitter affects both 9 Clock Uncertainties 4 Power Supply Devices 2 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty 10 5

6 Clock Constraints in Edge-Triggered Systems Courtesy of IEEE Press, New York Latch timing t DQ D Q When data arrives to transparent latch Latch is a soft barrier t CQ When data arrives to closed latch Data has to be re-launched 12 6

7 Single-Phase Clock with Latches Latch Unger and Tan Trans. on Comp. 10/86 Logic T skl T skl T skt T skt In Rabaey Chapter 10: T sk T skl T skt PW t CY 13 Preventing Late Arrivals t CY PW T SU Data must arrive T CQ T LM T SU T SU PW T DQ TLM T SU 14 7

8 Preventing Late Arrivals t CY Tskl Tskt TSU TCQM PW, max T TDQM LM Or: tcy TCQM TLM TSU Tskl Tskt PW t T T CY DQM LM 15 Preventing Premature Arrivals PW T H T CQ T Lm Two cases, reduce to one: TLm Tskl Tskt TH PW TCQm 16 8

9 Single-Latch Timing Summary Bounds on logic delay: Latch t CY Tskl Tskt TSU TCQM PW, max T TDQM TLm Tskl Tskt TH PW TCQm LM Logic Solutions: 1) Balance logic delays 2) Locally generated short PW 17 Latch-Based Design L1 latch is transparent when = 0 L2 latch is transparent when = 1 L1 Latch Logic L2 Latch Logic 18 9

10 Latch-Based Timing As long as transitions are within the assertion period of the latch, no impact of position of clock edges 19 Latch Design and Hold Times 20 10

11 Latch-Based Timing Longest path l T 2T T T CY DQM LHM LLM Independent of skew Short paths TCLLm TSK TH TCQm TCLHm TSK TH TCQm Same as register-based design but holds for both clock edges 21 Latch-Based Timing Static logic Skew L1 Latch Logic L2 Latch L1 latch L2 latch Logic Long path Can tolerate skew! Short path 22 11

12 Soft-Edge Properties of Latches Slack passing logical partition uses left over time (slack) from the previous partition Time borrowing logical partition utilizes a portion of time allotted to the next partition Makes most impact in unbalanced pipelines Bernstein et al, Chapter 8, Chandrakasan, Chap 11 (by Partovi) 23 Slack-Passing and Cycle Borrowing For N stage pipeline, overall logic delay should be < N Tcl 24 12

13 4. Design for performance B. Statistical timing Pictorial view of setup and hold tests Actual early AT Early RAT 0 or more switching(s) allowed Actual late AT Late RAT Data must be stable Hold time Latest clock arrival time Early slack Data must be stable Late Setup time slack Earliest clock arrival time (next cycle) ICCAD '07 Tutorial Chandu Visweswariah 26 13

14 Handling of across-chip variation Each gate has a range of delay: [lb, ub] The lower bound is used for early timing The upper bound is used for late timing This is called an early/late split Static timing obtains bounds on timing slacks Timing is sperformed as one forward pass and one backward pass Setup test Hold test Launching late path Launching early path LF CF LF CF Capturing early path ICCAD '07 Tutorial Capturing late path Chandu Visweswariah 27 How is the early/late split computed? The best way is to take known effects into account during characterization of library cells History effect, simultaneous switching, pre-charging of internal nodes, etc. This drives separate characterization for early and late; this is the most accurate method Failing that, the most common method is derating factors Example: Late delay = library delay * 1.05 Early delay = library delay * 0.95 The IBM way of achieving derating is LCD factors (Linear Combination of Delay) (FC=fast chip, SC=slow chip, see next page) Late delay = L * FC_delay + L * NOM_delay + L * SC_delay Early delay = E * FC_delay + E * NOM_delay + E * SC_delay Across-chip variation is therefore assumed to be a fixed proportion of chipto-chip variation for each cell type ICCAD '07 Tutorial Chandu Visweswariah 28 14

15 IBM delay modeling* At a given corner late delay = intrinsic + systematic + random early delay = intrinsic systematic random Intrinsic: Chip means Systematic ACV Random ACV *P. S. Zuchowski, ICCAD 04 Early Late Early Late 29 ICCAD '07 Tutorial Chandu Visweswariah Traditional timing corners Intra-chip variation Intra-chip variation Fast chip early Fast chip late Slow chip early Slow chip late Chip-to-chip variation Fast chip Slow chip ICCAD '07 Tutorial Chandu Visweswariah 30 15

16 The problem with an early/late split The early/late split is very useful Allows bounds during delay modeling Any unknown or hard-to-model effect can be swept under the rug of an early/late split But, it has problems Additional pessimism (which may be desirable) Unnecessary pessimism (which is never desirable) Setup test Launching late path LF CF This physically common portion can t be both fast and slow at the same time ICCAD '07 Tutorial Capturing early path Chandu Visweswariah 31 Additional pessimism: Clock tree view FP1 and FP2 FP3 LF 1 LF 2 LF 3 Comb. CF Comb. Comb. ICCAD '07 Tutorial Chandu Visweswariah 32 16

17 How to have less pessimism? Common path pessimism removal Account for correlations Credit for statistical averaging of random 33 Statistical timing Deterministic a + c + MAX Statistical b a + c + MAX ICCAD '07 Tutorial b Chandu Visweswariah 34 17

18 The problem of correlations There are many reasons for correlations Chip-to-chip variations are perfectly correlated within a single chip Same circuit types Same device families Same metal levels Same voltage islands Same regions of the chip Dependence on common sources of variation Reconvergent fanout Etc. In a reasonable-sized chip, there may be 100 million timing quantities, so we don t handle correlations in the classical way Not by storing and manipulating a 100M x 100M covariance matrix 35 Canonical form a0 a1 X 1 a2 X 2 an X n a n 1 R a Constant (nominal value) Sensitivities Deviation of global sources of variation from nominal values All timing quantities are parameterized by the sources of variation Correlation can be judged on-demand by inspection Independently random uncertainty 36 18

19 Statistical timing basics Represent all timing quantities in canonical form Delays, slews, guard times, ATs, RATs, slacks, PLL adjusts, constraints, CPPR adjusts Propagate ATs forward through the timing graph Addition of two canonical forms is easy Max/min operations are also easy with the help of some analytic formulas Propagate RATs backward through the timing graph Subtraction of two canonical forms is easy Use statistical max/min operations Slack is simply the difference between AT and RAT Since this is available in canonical form, we get sensitivities of circuit performance to sources of variation for free These can be used to ensure a robust design 37 Statistical max operation *C. E. Clark, The greatest of a finite set of random variables, OR Journal, March-April 1961, pp **M. Cain, The moment-generating function of the minimum of bivariate normal random variables, American Statistician, May 94, 48(2) 38 19

20 1 Unified view of correlations Correlation Coefficient Independently random part D a 0 a X a X i i r R Spatially correlated part: within-chip distancerelated correlation Globally correlated part: chip-to-chip, wafer-to-wafer, batch-tobatch variation 0 Distance ICCAD '07 Tutorial Chandu Visweswariah Spatial correlation vs. early/late split LF 28 1 LF LF CF early clock Dependence on common virtual variables cancels out at the timing test ICCAD '07 Tutorial Chandu Visweswariah 40 20

21 Next Lecture Latches and flip-flops 41 21