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1 Microelectronics Journal 43 (12) Contents lists available at SciVerse ScienceDirect Microelectronics Journal journal homepage: Utilizing interdependent timing constraints to enhance robustness in synchronous circuits E. Salman a,n, E.G. Friedman b a Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY 11794, USA b Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA article info Article history: Received 24 July 11 Received in revised form 15 November 11 Accepted 16 November 11 Available online 3 December 11 Keywords: Delay uncertainty Variations Setup-hold time interdependence Constraint characterization abstract Interdependent setup-hold times are exploited during the design process to improve the robustness of a circuit. Considering this interdependence only during static timing analysis (STA), as demonstrated in the previous work, is insufficient to fully exploit the capabilities offered by interdependence. This result is due to the strong dependence of STA results on the specific circuit, cell library, and operating frequency. Interdependence is evaluated in this paper for several technologies to determine the overall reduction in delay uncertainty rather than improvements in STA. Reducing delay uncertainty produces a more robust synchronous circuit. The increasing efficacy of interdependence in deeply scaled technologies is also demonstrated by investigating the effect of technology scaling on interdependent timing constraints. & 11 Elsevier Ltd. All rights reserved. 1. Introduction Cell library characterization is a critical step in static timing analyses (STA) of large scale integrated circuits [1,2]. Since an STA tool relies on the data described in these libraries to analyze the timing characteristics of a circuit, the overall accuracy of STA is strongly dependent upon the accuracy of cell library characterization. The setup and hold times, i.e., timing constraints, of a sequential cell play a critical role in the timing analysis process since these timing constraints are used to determine whether a circuit can properly operate at the required clock frequency. Previous work has shown that the setup-hold times and clock-to-q delay of a sequential cell are interdependent [3,4]. An independent characterization process may produce either optimistic or overly pessimistic STA results. Both cases should be avoided as the optimistic case can cause a circuit to fail whereas the pessimistic case unnecessarily degrades circuit speed. One of the challenges in interdependent characterization of timing constraints is computational complexity since each sequential cell in a library should be extensively simulated to obtain the clock-to-q delay surface [3]. The computational efficiency of interdependent setup-hold time characterization has been improved through state transition [5,6]. Interdependent n Corresponding author. Tel.: þ ; fax: þ addresses: emre@ece.sunysb.edu (E. Salman), friedman@ece.rochester.edu (E.G. Friedman). setup-hold times have also been exploited in statistical static timing analysis (SSTA) processes [7]. While the need for interdependent characterization and using these interdependent timing constraints within the STA process have been well understood [3 7], the significance of interdependence in advanced technologies and the scaling characteristics of interdependent timing constraints have not been investigated. A disadvantage of relying only on STA is the inability to accurately evaluate the significance of interdependence. Specifically, the results presented in [3] strongly depend upon the specific circuit and clock frequency. For example, while interdependence can significantly reduce timing violations in one circuit, interdependence may not be as efficient in another circuit with the same technology, producing inconsistent results. A different approach is proposed in this paper where the ability of the interdependence to tolerate variations [8,9] and reduce delay uncertainty (thereby enhance robustness) is investigated rather than improving timing analysis. This approach provides a more complete understanding of the efficacy of interdependence. Furthermore, the evolution of interdependence with process technology is also investigated to determine the effects of scaling on these interdependent timing constraints. The result has practical importance to understand whether the additional complexity required to characterize interdependent timing constraints is worth the effort in deep submicrometer technologies. The rest of the paper is organized as follows. Background material reviewing the timing characteristics of a circuit and setup-hold interdependence is provided in Section 2. The problem /$ - see front matter & 11 Elsevier Ltd. All rights reserved. doi:1.116/j.mejo

2 1 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) is formulated in Section 3. A procedure to reduce delay uncertainty and compensate for variations is described in Section 4. A case study is presented in Section 5 to evaluate the significance of setup-hold interdependence to compensate for power supply and threshold voltage variations for four technology generations. Finally, the paper is concluded in Section Background The timing characteristics of synchronous circuits are reviewed in Section 2.1. Interdependent setup-hold times are summarized in Section Timing characteristics of synchronous circuits A simple synchronous digital circuit consisting of two sequentiallyadjacent registers with a combinational circuit between these registers is shown in Fig. 1. Two inequalities should be satisfied for this circuit to function properly. Referring to Fig. 1, the first inequality is T Cf þt CP ZT Ci þt D þt S, ð1þ where T Ci and T Cf are the delay for the clock signals to arrive, respectively, at the initial and final registers. Note that T Ci and T Cf are also referred to as, respectively, the delay of the clock launch path and clock capture path. T CP is the clock period, T D is the data path delay consisting of the clock-to-q delay of the initial register, logic delay of the combinational circuit, and the interconnect delay. T S is the setup T Ci Initial register D C Q Interconnect T D Combinational circuit T Cf Interconnect Final register Fig. 1. Simple synchronous circuit consisting of a combinational logic and two registers. D C Q time of the final register. Note that (1) determines the maximum speed of the circuit, making this inequality important for the critical paths within a circuit. The second inequality that needs to be satisfied is T Ci þt D ZT Cf þt H, ð2þ where T H is the hold time of the final register. This inequality guarantees that no race condition exists, i.e., the data are not latched within the final register during the same clock edge. Note that (2) is relatively more important for those timing paths where the data path delay is sufficiently small, such as a shift register or counter Interdependent setup-hold times Inequalities (1) and (2) require a difference called a skew to be larger than or equal to a number called a timing constraint. These inequalities, therefore, can be rewritten as Setup skewzt S, ð3þ Hold skewzt H, where setup skew and hold skew are, respectively, Setup skew ¼ T Cf þt CP ðt Ci þt D Þ, Hold skew ¼ T Ci þt D T Cf : Note the important difference between setup-hold skews and setuphold times: setup and hold skews refer to any time difference between the data and clock signals whereas the setup and hold times refer to the minimum required time difference to reliably capture and store the data. Also note that the difference between the left and right hand sides of (3), i.e.,(setupskew T S )isreferredtoas setup slack. Similarly, (hold skew T H ) is referred to as hold slack. A negative slack therefore corresponds to a timing violation whereas a positive slack corresponds to available timing margin. Existing approaches to characterize the timing constraints of a register, i.e., setup and hold times in (1) and (2), assume these timing constraints are independent [1]. This independent characterization produces overly pessimistic results since the setuphold times are, in reality, interdependent [3]. An example of an interdependent setup-hold contour curve obtained from a clockto-q delay surface at a constant delay is illustrated in Fig. 2 [4]. ð4þ ð5þ ð6þ Hold Time 3 MSP REGION 1 MHP 1 Hold Skew 8 Setup Skew 1 REGION Setup Time Fig. 2. Interdependent setup-hold time characterization: (a) clock-to-q delay surface as a function of independently varying setup skew and hold skew and (b) the contour at 1% degraded clock-to-q delay.

3 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) In Fig. 2(a), the clock-to-q delay is obtained as a function of independently varying setup skew and hold skews. Those setup and hold skews corresponding to a specific per cent degradation in clock-to-q delay are extracted from this surface, representing a contour curve. Each (setup, hold) pair on this contour curve shown in Fig. 2(b) is a valid pair for the register. Multiple timing constraints therefore exist rather than a single setup and hold time. As indicated in Fig. 2(b), a small setup time can be obtained at the expense of a large hold time. Similarly, a small hold time can be obtained at the expense of a large setup time. For example, minimum setup pair (MSP) and minimum hold pair (MHP) refer, respectively, to a pair on the contour with the minimum setup time and minimum hold time. Also note that any pair in region 1 is also valid with additional pessimism, whereas any pair in region 2 is invalid, as the pairs in this region are optimistic. Previous work has primarily focused on the effect of interdependent setup-hold pairs on timing analysis [3,4,7] and characterization aspects of interdependence [5,6]. Considering only STA results, however, is insufficient to fully understand the capabilities of interdependence. Interdependent setup-hold times not only reduce pessimism in timing analysis, but also provide an opportunity to improve the tolerance of a circuit to process and environmental variations. Investigating interdependence from this perspective provides a more realistic understanding of interdependent timing constraints. Furthermore, the effect of technology scaling on interdependent setup-hold pairs is also investigated, demonstrating the increasing significance of interdependence in deeply scaled technologies. 3. Problem formulation The contour curve illustrated in Fig. 2(b) can be approximated as a linear line using two critical pairs: MSP and MHP. This approximation is further described in Section 4.1. An approximation of the contour using two critical pairs is illustrated in Fig. 3 where the pairs MSP and MHP are represented, respectively, as (T S,min, T H,max ) and (T S,max, T H,min ). According to (1) and (2) and referring to Fig. 1, the delay of the data path should satisfy T Cf þt H T Ci rt D, ð7þ T D rt Cf þt CP ðt Ci þt S Þ, where (7) and (8) determine, respectively, the lower and upper bounds of the data path delay. Characterization of the setup and hold times affects the design process by constraining the data path delay T D. The allowable T H, max (T S, min, T H, max ) T H, min T S, min Pessimistic pair (T S, max, T H, max ) (T S, max, T H, min ) T S, max Fig. 3. Linear approximation of the contour curve using two pairs: (T S,min, T H,max ) and (T S,max, T H,min ). ð8þ range of T D is minimized if the pessimistic pair (T S,max, T H,max )is used, causing the circuit to be overdesigned. Which specific (setup, hold) pair should be chosen to design the circuit is unclear even if the interdependence is known since multiple valid pairs are available. For example, if the pair (T S,min, T H,max ) is used, the lower bound constraint of the data path delay is difficult to satisfy since the hold time is large. Hence, the data path delay should be increased by inserting additional stages, dissipating unnecessary power. Alternatively, if the pair (T S,max, T H,min ) is used, the upper bound constraint on the data path delay is difficult to satisfy since the setup time is large. Consequently, the data path delay should be lowered by inserting an additional register to satisfy the target frequency, also causing unnecessary power consumption. Furthermore, both pairs (T S,min, T H,max ) and (T S,max, T H,min ) exhibit low tolerance to process and environmental variations since the range of valid setup times T S,max T S,min and hold times T H,max T H,min is not exploited. It is therefore important to determine the appropriate (setup time, hold time) pair during the design process that lowers power consumption, satisfies the required delay, and increases the robustness of the circuit to achieve a higher tolerance to process and environmental variations. This procedure exploits interdependence to reduce delay uncertainty, as described in the following section. 4. Reducing delay uncertainty A characterization technique to determine the critical pairs MSP and MHP is introduced in Section 4.1. A procedure to reduce delay uncertainty and compensate for variations is described in Section 4.2. The effect of variations on the interdependent characterization process is discussed in Section 4.3. The amount of compensation achieved by the proposed technique is determined in Section Obtaining linear setup-hold relationship The first step to reduce delay uncertainty is to obtain a relationship between setup-hold times of a register. A piecewise linear approximation of the setup-hold contour exhibits a tradeoff between computational complexity and the amount of pessimism. A two-point approximation is achieved in this work to demonstrate the effectiveness of setup-hold interdependence in reducing delay uncertainty, even with this relatively simple approximation. Note that this approximation is valid due to two reasons: (1) any point above the curve, i.e., in region 1, is a valid pair with some pessimism since the curve is convex, and (2) part of the curve between MSP and MHP represents a monotonically decreasing function. Additional points on the curve reduce pessimism at the expense of additional computational complexity. Note that both the convexity and monotonicity of the contour curve have been observed for each analysis, provided that an edge-triggered, master-slave type D flip flop is used as a register. The sizing and process technology do not change this characteristic. Note however that the evaluation of setup-hold relationship for different flip flop architectures and latches remains as future work. An efficient, two-point approximation technique is described in this section. Note that additional points require the generation of the entire clock-to-q delay surface, significantly increasing the computational time due to additional simulations. Furthermore, the number of linear equations characterizing the setup-hold relationship also increases. Referring to Fig. 3, the four points defining MSP and MHP, i.e., T S,min, T H,max, T H,min, and T S,max, are

4 122 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) Sweep Large hold skew Sweep setup skew Obtain T S, min T S, min Sweep Setup skew = T S, min Sweep hold skew Obtain T H, max Sweep Large setup skew Sweep hold skew Obtain T H, min Sweep TH, min Hold skew = T H, min Sweep setup skew Obtain T S, max Fig. 4. Efficiently obtaining the critical setup-hold pairs of a register without generating a three-dimensional clock-to-q delay surface: (a) T S,min, (b) T H,max, (c) T H,min, (d) T S,max. obtained as follows where the corresponding waveforms of the clock and data signals are illustrated in Fig. 4. Variation T S,min : the clock-to-q delay of a register is determined as a function of setup skew at a sufficiently high hold skew. The setup skew corresponding to a 1% degradation in delay is chosen as T S,min. T H,max : the clock-to-q delay of a register is determined as a function of hold skew at setup skew ¼ T S,min. The hold skew corresponding to a 1% degradation in delay is chosen as T H,max. T H,min : the clock-to-q delay of a register is determined as a function of hold skew at a sufficiently high setup skew. The hold skew corresponding to a 1% degradation in delay is chosen as T H,min. T S,max : the clock-to-q delay of a register is determined as a function of setup skew at holdskew ¼ T H,min. The setup skew corresponding to a 1% degradation in delay is chosen as T S,max. Increase in TD Additional slack in hold skew Increase T H Decrease T S to satisfy (8) Decrease in T D Additional slack in setup skew Increase T S Decrease T H to satisfy (7) The linear relationship between the setup and hold times can be represented by the critical pairs as T H ¼ f ðt S Þ or, equivalently, T S ¼ f 1 ðt H Þ Reduced delay uncertainty T H ¼ f ðt S Þ¼ T ST H,r T H,max T S,max þt H,min T S,min T S,r for T S,min ot S ot S,max, ð9þ Fig. 5. Flow diagram to reduce delay uncertainty by exploiting interdependent setup-hold times. where the range of valid setup times T S,r and hold times T H,r are, respectively, T S,r ¼ T S,max T S,min, ð1þ T H,r ¼ T H,max T H,min : 4.2. Procedure to reduce delay uncertainty ð11þ For a critical path, an increase in the delay of a data path DT D due to variations causes the frequency to be decreased to satisfy (8). This increase in the data path delay produces additional hold slack in (7). This additional slack in the hold skew can be exploited to increase the hold time in (7) by DT Hold where DT Hold ¼ DT D. An increase in the hold time enables a decrease in the setup time by DT S ¼ f 1 ðdt H Þ due to the interdependence, as illustrated in Fig. 3. The effect of the variation, i.e., the decrease in frequency, can therefore be compensated by exploiting a lower setup time. Similarly, for a timing path sensitive to a race condition, referred to as a short path, a decrease in the delay of the data path by DT D can cause a hold time violation. Since the delay of the data path is reduced, any additional setup slack in (8) can be exploited by increasing the setup time by DT S where DT S ¼ DT D. An increase in the setup time supports a decrease in the hold time by DT H ¼ f ðdt S Þ, potentially resolving the violation. The delay uncertainty due to a variation is therefore reduced by exploiting interdependent setup-hold times. This procedure is summarized in the flowchart depicted in Fig. 5. Note that the variation in the delay of the clock launch path DT Ci and clock capture path DT Cf is assumed in this approach to be equal. For those cases where this assumption is not accurate, the variation in the delay of the clock path may either enhance or degrade the delay uncertainty depending upon the sign of DT Cf DT Ci, as described in Section 4.4. Another consideration for this procedure is the effect of variations on the interdependent setup-hold characteristics. This variation in the critical setup-hold pairs is sufficiently low as compared to the range of valid setup times and hold times, enabling the proposed procedure. This behavior is further described in the following subsection.

5 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) Hold Time 5 3 V DD =1.2 V V DD =1.8 V V DD =1.32 V Setup time Fig. 6. Variation of interdependent setup-hold characteristics as a function of the power supply voltage for a 9 nm CMOS technology Setup-hold time characterization under variations Process and environmental variations can also affect the critical pairs of a register, i.e., T S,min, T H,max, T S,max, and T H,min. The effect of a variation on these critical pairs, however, is sufficiently small as compared to the range of valid setup times T S,r and hold times T H,r. This behavior is primarily due to a stronger dependence of the clock-to-q delay on the setup skew and hold skew when these skews are reduced [3]. For example, at a critical pair ðt S,min,T H,max Þ, the clock-to-q delay is primarily determined by T S,min, lowering the effect of process and environmental variations on this pair. Similarly, at a critical pair ðt S,max,T H,min Þ, T H,min has a relatively greater effect on the clock-to-q delay. To further illustrate this behavior, critical pairs are obtained for different power supply voltages in a 9 nm CMOS technology where the power noise is the source of the variation, as depicted in Fig. 6. The maximum variation in the power supply is assumed to be 1% of the nominal voltage. The variation in the critical pairs is compared with the range of valid setup and hold times. Specifically, the variation in the critical pairs caused by a 1% increase or decrease in the power supply voltage is listed, respectively, in Tables 1 and 2. As listed in these tables, T S,r and T H,r are sufficiently higher than the variation of the critical pairs, making interdependence an effective mechanism to reduce delay uncertainty Amount of compensation The compensation in delay variation (or the reduction in delay uncertainty) is dependent upon three primary factors: (a) the range of the valid setup times T S,r and hold times T H,r, (b) the specific (setup, hold) pair used in (7) and (8) to determine the data path delay, and (c) the effect of the variations on the clock launch and capture paths, i.e., the clock distribution network. If a register has a greater range of valid setup times and hold times, this register is more effective in reducing delay uncertainty. Note however that this type of register may exhibit other tradeoffs such as higher power consumption and clock-to-q delay. Evaluation of different register architectures for setup-hold interdependence remains as a future work. As described in Section 3, the specific (setup, hold) pair used to determine the data path delay can lower the power consumption while satisfying the target frequency and achieving a higher tolerance to variations. The middle point of the setup-hold line (T S,mid, T H,mid ) results in a highest tolerance since the setup and Table 1 Variation of the critical pairs due to a 1% decrease in the power supply voltage. Range of valid setup times is 139 ps. Critical points V DD ¼1.2 V V DD ¼1.8 V Variation T S,min T H,max T S,max T H,min T S,r T H,r Table 2 Variation of critical pairs due to a 1% increase in the power supply voltage. Range of valid hold times is 54 ps. Critical points V DD ¼1.2 V V DD ¼1.32 V Variation T S,min T H,max T S,max T H,min T S,r T H,r T H, max (T S, mid, T H, mid ) T H, min T S, min T S, max Fig. 7. A data path designed at the pair ðt S,mid,T H,mid Þ achieves the highest tolerance to variations. hold times exhibit the maximum flexibility to variations, as illustrated in Fig. 7. Note that in this case, the data path should be designed to ensure that the delay of the data path satisfies

6 124 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) both (7) and (8), specifically when the setup time and hold time are, respectively, T S,mid and T H,mid. This technique is analogous to clock skew optimization techniques proposed in the mid 199s where the circuit is designed at the middle of the clock skew range among possible skew values (referred to as the permissible range) to maximize the tolerance of a circuit to variations [11,12]. The amount of variation tolerated by this methodology is also dependent upon the variation in the delay of the clock launch path DT Ci and clock capture path DT Cf. Specifically, if DT Ci ¼ DT Cf, i.e., constant clock skew, these variations compensate. In this case, the variation in the delay of the clock paths does not affect the amount of tolerance. If however DT Ci 4DT Cf, less variation can be tolerated by a critical path since the delay of the clock launch path is increased, delaying the data signal from leaving the register. For a short path, however, additional variation can be tolerated. Alternatively, if DT Cf 4DT Ci, additional variation can be tolerated for a critical path since the clock launch path is relatively faster than the clock capture path. For a short path, however, less variation can be tolerated. The significance of interdependence in enhancing the robustness can also be understood by investigating the permissible range. The relationship between interdependent timing constraints and permissible range is described in the following section Permissible range and interdependence A permissible range has been defined that describes the valid range of clock skew T Ci T Cf [13,12]. Rearranging (7) and (8), the clock skew should satisfy T H T D rt Ci T Cf, ð12þ T Ci T Cf rt CP T D T S, ð13þ where the lower and upper bounds of the clock skew are determined, respectively, by (12) and (13). The permissible range T perr of the clock skew is determined by the difference between the upper and lower bounds of the clock skew T per ¼ T CP ðt S þt H Þ: ð14þ A methodology to tolerate skew variations by exploiting this permissible range has also been previously described [11]. According to (14), a smaller setup and hold time is desirable to increase the permissible range. Assuming that the circuit is designed at the middle of the permissible range, a higher range provides increased tolerance to variations. Interdependent timing constraints provide additional flexibility to modify the permissible range. Specifically, the lower and upper bounds of the clock skew change depending upon the specific (setup, hold) pair, as illustrated in Fig. 8. For example, if the pair ðt S,min,T H,max Þ is used, the permissible range shifts to the right since both bounds increase. In this case, the upper bound of (T, T ) (T, T ) Race condition Race condition Race condition Permissible range Permissible range Permissible range period limitation period limitation period limitation (T, T ) Fig. 8. Exploiting interdependent setup and hold times within a permissible range of the clock skew. A shift in the permissible range is achieved. This shift is dependent upon the specific (setup, hold) pair, providing additional flexibility to tolerate variations, thereby enhancing robustness. the permissible range is greater. Alternatively, if the pair ðt S,max,T H,min Þ is used, the permissible range shifts to the left since both bounds decrease, as shown in Fig. 8. In this case, the lower bound of the permissible range is smaller. The interdependence of the setup and hold times therefore provides additional flexibility in exploiting the permissible range to tolerate variations. skew scheduling in the presence of interdependent setup-hold times remains as a future work. 5. Case study The efficacy of setup-hold time interdependence to compensate power supply and threshold voltage variations is evaluated in this section. Note that power supply noise and threshold voltage variations are considered here as an example to demonstrate the significance and utility of the setup-hold interdependence [14]. Other factors that introduce delay uncertainty such as temperature variations can also be considered to evaluate the significance of setup-hold interdependence [15]. Four CMOS technology generations are considered: 18 nm, 9 nm, 65 nm, and 45 nm. An industrial model is used for the 18 nm, 9 nm, and 65 nm CMOS technologies. For the 45 nm CMOS technology, a predictive model is used [16,17]. Two clock frequencies are considered for each technology based on the data published in [18], as illustrated in Fig. 9. Higher frequencies represent the upper bound on the frequency while the lower frequencies represent the lower bound on the frequency. The interdependent setup-hold time characteristics for each technology is described in Section 5.1. The dependence of these characteristics on process technology is also discussed. The variation in the delay caused by the power noise and threshold voltage variations is quantified as a function of technology in Section 5.2. Finally, the efficacy of setup-hold time interdependence in tolerating this delay variation is evaluated in Section Interdependent T S vs T H relationship A master-slave type, rising edge triggered register is used to illustrate the T S vs. T H relationship for each technology node. The register has been simulated to obtain the critical setup-hold pairs, where the signal transition times are assumed to be 1% of the clock period. The T S vs. T H relationship for each technology is Frequency (GHz) Lower frequencies Higher frequencies Fig. 9. Target clock frequency for each technology node. Higher frequencies represent the upper bound of the frequency while the lower frequencies represent the lower bound of the frequency.

7 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) Hold time nm 9 nm 65 nm 45 nm Table 3 Power supply voltage, clock-to-q delay, and critical points T S,min, T H,max, T S,max, T H,min, T S,r, and T H,r for each technology. CMOS technology (nm) V DD (V) -to-q delay T S,min T H,max T S,max T H,min T S,r T H,r Setup time Fig. 1. Interdependent setup-hold time characteristics for four technologies. illustrated in Fig. 1. Each line can be represented as 18 nm : T H ¼ :386T S þ72:839 for 41rT S r18, ð15þ 9 nm : T H ¼ :494T S þ65:32 for 33rT S r125, ð16þ 65 nm : T H ¼ :269T S þ33:255 for 25:8rT S r11, ð17þ 45 nm : T H ¼ :123T S þ16:2 for 15:4rT S r98, ð18þ where each range is in picoseconds. The range of valid setup times T S,r ¼ T S,max T S,min and range of valid hold times T H,r ¼ T H,max T H,min scale with technology, as shown in Fig. 1. These critical points, clock-to-q delay of the register, and power supply voltage are listed in Table 3 for each CMOS technology. Note the behavior of T S,r ¼ T S,max T S,min (range of valid setup times) as a function of technology. The ratio of the range of valid setup times to the clock period (T S,r =T CP ) increases as the technology advances, as illustrated in Fig. 11. Specifically, for the 45 nm CMOS technology, the range of valid setup times is approximately % of the clock period at lower frequencies. At higher frequencies, this ratio increases to 35%. The interdependence of the setup-hold times is therefore more able to tolerate variations in deep submicrometer technologies, where the difference between the maximum and minimum setup time is a significant fraction of the clock period Delay variation due to power noise and threshold voltage variations The effect of power supply variations, i.e., power noise, and threshold voltage variations on delay is evaluated in this section. These variations are compared with the range of valid setup times T S,r and hold times T H,r, thereby determining the ability to exploit this interdependence to reduce delay uncertainty. The clock period corresponding to each technology is determined from Fig. 9. A critical path is designed for each technology to evaluate the efficacy of exploiting the interdependence relationship in compensating for a drop in the power supply voltage and an increase in the threshold voltage. A combinational circuit is inserted between the initial and final register until the delay of a data path satisfies (8). A short path can also be generated by abutting the registers. This short path is designed to evaluate the efficacy of exploiting the interdependence relationship in compensating for an increase Ratio of the T S,r to T CP Lower frequencies Higher frequencies Fig. 11. Ratio of the range of valid setup times T S,r to the clock period T CP. 8 Increase in data path delay T D for higher frequencies Increase in data path delay T D for lower frequencies Valid range of setup times T S,r Fig. 12. Comparison of the increase in the delay of a critical data path with T S,r to evaluate the efficacy of exploiting the interdependence relationship. A 1% decrease in the power supply voltage is assumed. in the power supply voltage and a decrease in the threshold voltage since both factors reduce the delay of the data path. These long and short paths are simulated with SPICE, where the power supply voltage and threshold voltage are independently varied by 1%. Specifically, for a long path, the power supply is decreased by 1% and the threshold voltage is increased by 1%. Alternatively, for a short path, the power supply is increased by 1% whereas the threshold voltage is decreased by 1%. The corresponding variation in the delay of the data path,

8 126 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) including clock-to-q delay, is determined by SPICE simulations for each technology. For a long path, delay variations due to power supply noise and threshold voltage fluctuations are compared with the range of valid setup times T S,r, respectively, in Figs. 12 and 13. Similarly, for a short path, delay variations are compared with the range of valid hold times T H,r, as illustrated in Fig. 14. These figures help evaluating the efficacy of exploiting the interdependence relationship, as described in the following section Compensation of delay variations As illustrated in Fig. 12, the interdependence relationship can be used to compensate for delay variations induced for power supply noise since the range of valid setup times is higher than the increase in the data path delay. The exception is the long path in 18 nm CMOS technology operating at MHz. At this Increase in data path delay T D for higher frequencies Increase in data path delay T D for lower frequencies Valid range of setup times T S,r Fig. 13. Comparison of the increase in the delay of a critical data path with T S,r to evaluate the efficacy of exploiting the interdependence relationship. A 1% increase in the threshold voltage is assumed Decrease in data path delay T D due to power variations Decrease in data path delay T due to threshold D voltage variations Valid range of hold times T H,r Fig. 14. Comparison of the decrease in the delay of a short path with T H,r to evaluate the efficacy of exploiting the interdependence relationship. Two cases are analyzed: (1) a 1% increase in the power supply voltage is assumed, (2) a 1% decrease in the threshold voltage is assumed. frequency, the delay of the data path is relatively large, causing a higher absolute variation in the delay. If threshold voltage variations are considered, the range of valid setup times is higher than the delay variations for each technology and clock frequency, as depicted in Fig. 13. This characteristic is due to a stronger dependence of delay on power supply voltage as compared to threshold voltage. According to both Figs. 12 and 13, the difference between the range of valid setup times and variation in delay is larger at higher frequencies since the delay of the data path is lower. Exploiting the interdependence relationship is therefore more effective in reducing the delay uncertainty of a critical path operating at higher frequencies. Also note that the absolute variation in delay due to both power supply noise and threshold voltage fluctuations somewhat saturates beyond the 13 nm technology node. This behavior is primarily due to the use of multicore processors where the increase in clock frequency is relatively low, as illustrated in Fig. 9. For a short path, the range of valid hold times is larger than the decrease in data path delay for each technology, as illustrated in Fig. 14. This characteristic is valid for both power supply and threshold voltage variations. The difference between these two values, however, decreases for more deeply scaled technologies. For a short path, therefore, the interdependence relationship is more effective in reducing delay uncertainty in older technologies. This behavior is due to the significant decrease in the range of valid hold times with scaled technologies. The procedure described in Section 4 has been performed on both long and short data paths. Note that these data paths are designed at the middle point ðt S,mid,T H,mid Þ of the interdependent setup-hold line. For example, for the 9 nm CMOS circuit operating at 3.2 GHz, the delay of the worst case data path increases by 23.7 ps due to a drop in power supply voltage. The hold time of 26.3 ps is increased by 23.7 ps, producing a new hold time of 5 ps. Since 5 ps is larger than the maximum hold time at this technology, the hold time is increased to 49 ps. An increase in the hold time enables a decrease in the setup time from 79 ps to 33 ps, tolerating 46 ps of delay uncertainty. Note that this delay uncertainty is larger than the initial variation of 23.7 ps, achieving about 1% delay compensation in the critical path. Similarly, for a short path, the decrease in the delay of the data path due to a 1% increase in the power supply voltage is 8.1 ps. The setup time can therefore be increased from 79 ps to 87.1 ps. The corresponding hold time is therefore reduced from 26.3 ps to 22.3 ps, as determined by (16), tolerating 4 ps of delay uncertainty. Since the variation in the delay of the data path is 8.1 ps, interdependence can compensate approximately 5% of the delay uncertainty of a short path. The results of this procedure for other technology nodes are listed in Tables 4 and 5 for, respectively, a worst case (long) data path and a short path. Table 4 Compensation of delay uncertainty caused by power noise for a critical data path. Technology (mm) Critical data path ðt S1,T H1 Þ Frequency (GHz) DT D ðt S2,T H2 Þ 18 (11.5, (41, 57) 1 3.2) (41, 57) (79, 26.3) (33, 49) (33, 49) (67.9, 14.9) (25.8, 26.3) (25.8, 26.3) (56.7, 9.2) (15.4, 14.3) (15.4, 14.3) 8.1 Compensation (%)

9 E. Salman, E.G. Friedman / Microelectronics Journal 43 (12) Table 5 Compensation of delay uncertainty caused by power noise for a short path. Technology (mm) Short path ðt S1,T H1 Þ DT D ðt S2,T H2 Þ 18 (11.5, 3.2) 17 (127.5, 23.6) (79, 26.3) 8.1 (87.1, 22.3) 5 65 (67.9, 14.9) 5.9 (73.8, 13.4) (56.7, 9.2) 2.8 (59.5, 8.9) 1.7 Compensation (%) Table 6 Compensation of delay uncertainty caused by threshold voltage variations for a critical data path. Technology (mm) Critical data path ðt S1,T H1 Þ Frequency (GHz) DT D ðt S2,T H2 Þ 18 (11.5, 3.2) (41, 57) (41, 57) (79, 26.3) (45.3, 42.6) (33, 49) 1 65 (67.9, 14.9) (25.8, 26.3) (25.8, 26.3) 1 45 (56.7, 9.2) (15.4, 14.3) (15.4, 14.3) 1 Compensation (%) Table 7 Compensation of delay uncertainty caused by threshold voltage variations for a short path. Technology (mm) Short path ðt S1,T H1 Þ DT D ðt S2,T H2 Þ 18 (11.5, 3.2) 13 (123.5, 25.2) (79, 26.3) 5.9 (84.9, 23.4) (67.9, 14.9) 4.3 (72.2, 13.8) (56.7, 9.2) 2.8 (59.5, 8.9) 1.7 Compensation (%) As listed in Table 4, delay uncertainty caused by power supply noise in a critical data path can be compensated by up to 1% at higher frequencies. At lower frequencies, more than 8% compensation is achieved in the more deeply scaled technologies. Alternatively, as listed in Table 5, for a short path, the compensation is lower due to the relatively smaller slope of the function T H ¼ f ðt S Þ as compared to T S ¼ f 1 ðt H Þ, as illustrated in Fig. 1. The same procedure is also applied to threshold voltage variations. Delay variations due to uncertainty in the threshold voltage and the amount of compensation for long and short paths are listed, respectively, in Tables 6 and 7. For long paths, higher compensation is possible since the delay exhibits a relatively weaker dependence on threshold voltage as compared to power supply voltage. For short paths, compensation of the delay uncertainty caused by power supply and threshold voltage is comparable since the delay variations are sufficiently close in both cases. 6. Conclusions The efficacy of interdependence in reducing delay uncertainty (therefore enhancing robustness) is investigated for four CMOS technologies. The proposed approach provides enhanced understanding of the capabilities provided by setup-hold interdependence, thereby overcoming the limitations of only considering static timing analysis results. The dependence of interdependence on technology scaling is also investigated. A case study is presented where the efficacy of setup-hold interdependence in reducing delay uncertainty due to power supply noise and threshold voltage variations is demonstrated. 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