Variability in Sub-100nm SRAM Designs
|
|
- Timothy Hoover
- 6 years ago
- Views:
Transcription
1 Variability in Sub-100nm SRAM Designs Ray Heald & Ping Wang Sun Microsystems Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 1
2 Outline Background: Quick review of what is varying SRAM cell variability analysis SNM Write trip voltage Read current Sense amplifier analysis Combined sense amplifier and memory array analysis SRAM timing circuits Conclusions Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 2
3 Threshold Voltage, V T, Variability in High Performance Processes Table from ITRS Roadmap 2001[1] L (nm) V t (mv) V t (mv) V t /V t 4.7% 5.8% 8.2% 9.3% 10.7% 16% Fewer dopant atoms makes V T control very difficult. 1/(Area) 0.5 dependence means more variation for the smallest transistors. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 3
4 Line Edge Roughness Becoming Variability Issue Transistor widths and lengths vary due to optical and etch limitations. Smallest transistors will have more variation with less total length or width for averaging. "LER (Line Edge Roughness) may become dominant for 32 nm channel length transistors." Croon, et. al. [2]. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 4
5 SRAM Sensitivity Most sensitive because: Row Addr Column Addr Row decoder Column 0 Column n Bit Bit Bit Bit M M M M M M M M M Column precharge Column mux Sense amps Write buffers R/W Dout Din Word m Word 0 Small signal analog levels are used together with logic level signals. The smallest viable transistors are used to minimize cell array area. Time available for sensing a memory cell's state is usually less than that necessary to achieve full logic level swing during read operation. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 5
6 SRAM Evaluation Needs Managing SRAM variability requires analysis and characterization of the SRAM memory cell and other critical circuitry. The remainder of this talk will examine: Memory cell evaluation, Sense amplifier offset evaluation, Combined memory cell and SA limitations and RAM timing circuitry. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 6
7 Memory Cell Needs Primary: Weakest cell is stable during worst case read operation. Write trip voltage is in reasonable range with worst case cell and voltage offsets. Usually low V cc and low temperature (with V T at its maximum) is most difficult. Minimum read current is enough for worst case read (including off cells bit leakage). Secondary: Standby current (array power). Off cell bit line current. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 7
8 Cell Stability: Static Noise Margin (SNM) Stability of SRAM cells is usually expressed as static noise margin (SNM): The maximum static noise source which can be tolerated without loss of state. Worst case SNM is during read operation with transfer gate (xsfr) conducting cell read current through memory cell's conducting NMOS pull down transistor (drive). Once sufficient to use Beta ratio W/L-drive:W/L-xsfr. Today with need to maximize margins, Monte Carlo simulation using statistical models is required. Expect SNM is most sensitive to drive and xsfr transistor with the PMOS sensitivity being least significant. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 8
9 Typical 6T Cell SNM Maximize A B SNM All simulations use U. C. Berkeley BPTM BSIM4 65 nm model [3]. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 9
10 SNM Simulation Background Good introduction of SNM simulation methods in Seevinck, et. al. [4] including equivalent circuits to rotate axis for Spice measurement. (See also: Bhavnagarwala, et.al.) Use cell inverter curves with the second curve mirrored about the 45 degree line through the origin. SNM is the side of the largest square which can be constructed between the two curves. Memory cell variations with process best analyzed separately from mismatch variations for large arrays. First quickly review normal distribution. Then examine process variations. Mismatch variations will follow. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 10
11 Normal Distribution Refresher Standard Normal (or Gaussian) Distribution: Density function p(x) = 1/(2 ) 0.5 * exp[(-x 2 )/2] - < x < mean = 0, standard deviation, = 1. Distribution function P(x) = - x p(z)dz probability z x. Distribution function of n identical units which must all work P n (x) = [P(x)] n. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 11
12 SNM Simulation: Process Process variations limited by foundry practices and standards. Usually wafers beyond a 2-3 sigma process window are rejected. Monte Carlo simulation with process variables for SNMmin(process) gives a more realistic result than process corner simulation. Better coverage of the process range. Avoids impossible corners such as P-fast ( T ox-min ) together with N-slow (T ox-max ). SNMmin(process)=SNM(mean) N (process)* (process) e. g. SNM = mv, = 15.6 mv and N = 3, then SNMmin = * 15.6 = 76.3 mv Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 12
13 SNM Varying V Tn & V Tp for all Xstrs Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 13
14 V T Variations Applied to Individual Transistors Pull-up V T ± 30 mv Driver V T ± 30 mv Xsfr V T ± 30 mv Dvr, xsfr & up xstrs V T ± 30 mv Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 14
15 SNM Variation with Temperature 100C, 125C and 175C SNM plots Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 15
16 SNM Simulation: Mismatch Note SNM squares not equal when mismatch is included. Hence, SNM = min [ SNM-A, SNM-B ]. Mismatch statistical variations cause a few of many identical circuits to fail on a die. A large circuit-pass sigma range and/or repair is needed to limit the yield loss. With process variations, fabrication specifications determine the range. For mismatch, the number of identical SRAM cells (or other sensitive circuit block) and expected electrical yield to specifications determine the appropriate sigma value. For large RAM blocks > 5 tolerance may be needed. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 16
17 Local Channel Length Variations Pull-up L ± 3 nm Driver L ± 3 nm Xsfr L ± 3 nm Dvr, xsfr & up xstrs L ± 3 nm Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 17
18 The Sigma Story Process variables are typically assumed to vary 3 unless otherwise stated in fabrication documentation. Why is 3 not sufficient for all statistical analysis? Gaussian statistics gives 99.73% of the distribution in the 3 range. Hence 2.7 in each 1,000 are outside the 3 range. SNM, I read and many other parameters only cause failure at one edge of range or 1.35 fail per 1,000. A 4MB cache usually contains almost 38 million memory cells. One unstable or unwritable cell in 38 million requires = 5.44 (low SNM or V trip edge only). Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 18
19 The Sigma Story-2 Mismatch variations for large arrays must be acceptable to 5 or beyond to achieve reasonable yield. Note statistical models of a new process are likely to be even more uncertain than the typical and corner models which may have been used previously. Simulations usually give a distribution of results close to a normal curve, so can use normal distribution functions. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 19
20 SNM Mismatch Example Say SNM(mean) = mv, (SNM-mis) = 9.2 mv, and we require that no more than 1 cell in 3.5 million to have a SNM < SNM(min). Then we are requiring that N (SNM-mis) = 5, which results in SNM(min) = 77.1 mv. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 20
21 Write Trip Voltage, V trip Write trip voltage is primarily determined by V T of the NMOS xsfr transistor on the side being pulled low. Need the trip voltage far enough from the V cc or V ss that no combination of offsets and noise can cause a write failure. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 21
22 Write Trip Voltage Example Usually with a symmetric 6T memory cell V trip < V cc /2. Hence, worst case V ss offset plus noise, DV ss, gives V trip lower bound. As with SNM, the process variation range is fixed by fabrication specification while mismatch variation tolerance is determined by the number of cells or circuits used and the acceptable yield loss increase. Vtrip (mean) N (trip-mis) * (trip-mis) > DV ss Example: DV ss = 150 mv, V trip (mean) = 410 m, V and (trip-mis) = 44 mv, then N (trip-mis) = This is about 1 in 5.8E08. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 22
23 Write Trip Voltage Example-2 Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 23
24 Cell Read Current While SNM and V trip evaluate cell functionality, the cell read current, I read, is a major component in determining array access time. SRAM 6T cell current is set by the series stack of NMOS transfer transistor and NMOS pull down transistor. The PMOS transistor is only a leakage path (source-drain and gate). I read Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 24
25 Cell Read Current Example With Iread (mean) and read (mis) from simulations: I read (min-mis) = I read (mean) N (I read -mis) * read (mis) Example: Iread (mean) = 100 ma, (I read -mis) = 6 ma, and I read (min) = 70 ma to meet timing. Then N (I read -mis) = 5 (1 cell in 3.5 million). For this set of read current parameters, a reasonable yield of a 4Mb array would require redundancy for replacing low Iread cells as well as non-functioning cells. Test & repair procedures must be capable of detecting and replacing these weak cells. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 25
26 Read Current with Repair Repair of the slowest 3-5 cells can significantly improve the yield to a fixed access time. Beyond a few cells the improvement is much more limited. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 26
27 Sense Amplifier, SA Sense amplifier: Converts the small signals from a memory cell (perhaps < 100 mv) to logic levels. Most involve carefully matched transistors designed to minimize I d and V T mismatches. Variations with sub 100 nm significant to array yield. Differential SA: Most rely on careful matching of NMOS differential pair. The V T mismatch is critical so all best historic layout matching practices feasible are used. Layout differential pair (usually at least NMOS) exactly the same (including current direction: 50% split best). Match all other layout as exact as practical & check with 1/2 design rule offset of each layer in all directions. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 27
28 Sense Amplifier-2 Current mode SA: Less sensitive to V T mismatch but sensitive to I d mismatch. Skewed inverter: Memory cell current gives a very slow voltage slew rate. Inverter trip point is much more sensitive than when used for standard logic. All sense amplifier types need statistical simulation with full number of bit line cells to determine effective SA input offset of the design. Verify that circuit timing with statistically weak cell can overcome this offset. New article: B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier, IEEE Journal of Solid-State Circuits, vol. 39, pp , July Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 28
29 Sense Amplifier Example Example: Drain fed differential SA. Critical mismatch is for NMOS differential pair just turning on when V in > V T (mismatch) [5]. Monte Carlo simulation is used with the fail condition measured as a function of DV in at SA-on time, sae. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 29
30 Sense Amplifier Example-2 Fail condition: Wrong output latched or correct output with inherent noise > maximum allowed is observed. sae : Unlikely that the time when SAE=V cc /2 is a good representation of sae. Most likely to be a time when SAE is just greater than V T. sae is likely to change with SAE slew rate. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 30
31 Sense Amplifier Example-3 Assume the circuit electrical yield is limited by high side bump with V bump < 200 mv required. Mismatch simulation is done with lowest FO and fast process corner for worst case bump. Assume: Large array using 20,000 identical sense amplifiers, DV in = 3 mv and (SA-mis) = 12.5 mv. Require likelihood of SA bump beyond limit ~1%. This is 1 fail in 2 million, satisfied by N (SA-mis) = 4.9. Then DV in (min) = * 4.9 = mv. Finally: verify that statistically weak cell meets timing with this offset. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 31
32 Critical Path Timing Yield to Max. Delay Involves both memory cell and sense amplifier variations. V min determined for a typical cell's critical path > mv [using SA example's result]. How must this be adjusted to allow the low I read to cause a mv differential in the maximum delay T max (I = 100 ma and (I) = 6 ma as before)? For I read (min-mis) = I read (mean) 5 * (I read -mis) Then DV in (min) = DV in (mean) * (SA-mis) / {I read (min-mis) / I read (mean)}. So DV in (min) = DV in (mean) * (SA-mis) / {1-5 * (I read -mis) / I read (mean)} = 90.5 mv. Note this is a worst case analysis with statistical limiting. The combined statistical analysis is best but adds simulation time. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 32
33 SRAM Timing Circuits-1 Reference memory cells, rows, and columns used for timing control are subject to the same statistical variations as the normal circuitry. Column 0 Column n Bit Bit Bit Bit M M M Row Addr Row decoder M M M M M M Word m Word 0 Column Addr Column precharge Column mux Sense amps Write buffers R/W Dout Din Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 33
34 SRAM Timing Circuits-2 The probability that a single reference is more than 2 away from the expected average is 4.5%. For a cell current reference, the number of cells used must be enough to a get good statistical mean. For a timing reference, the loading and exact structure of delay elements are still critical & must include the correct metal to device gate plus diffusion area ratio for good tracking. Good references are becoming more difficult with larger percent statistical variations in the 90 and 65 nm processes. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 34
35 SRAM Timing Circuits-3 Clock based timing: With single cycle throughput, only two of the three of usual critical timing signals can be timed from a clock edge. The third critical signal must be self-timed or coupled to a less accurate reference such as a DLL. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 35
36 Concluding Remarks Variation in device characteristics is becoming an acute problem for SRAM design. Circuit wide process variations of 2 to 3 are typical and will not decrease with future technologies. Within the die, local mismatch parameter variations are not decreasing as quickly as the parameters themselves. Meanwhile, the number of SRAM cells and other circuit blocks which must work on a chip is growing rapidly. Traditional mean and corner simulations must be supplemented with a number of statistical simulations to assure circuits will work and yield at the expected speed and reliability. Repair of slow cells must be made possible by design. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 36
37 Acknowledgments & Discussion Thanks to the Device Group at UC Berkeley for the very useful Berkeley Predictive Technology Model, BPTM, used in all simulations. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, New paradigm of predictive MOSFET and interconnect modeling for early circuit design, Proc. of IEEE CICC, pp , Jun Discussion: Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 37
38 References [1] Semiconductor Industry Association (SIA), International Roadmap for Semiconductors 2001 edition, Austin Tx; International SEMITECH, Available: [2] J. Croon, et. al., "Line Edge Roughness Characterization, Modeling and Impact on Device Behavior," IEDM, Dec [3] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, pp , Jun [4] E. Seevinck Sr., F. List, J. Lohstroh; Static-noise margin analysis of MOS SRAM cells, IEEE Journal of Solid-State Circuits, vol. 22, pp , Oct [5] A. Hajimiri, R. Heald, "Design Issues in Cross-Coupled Inverter Sense Amplifier," ISCAS Dig. of Technical Papers, May Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 38
39 Other Related Articles-1 A. Bhavnagarwala, X. Tang, J. Meindl; The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE Journal of Solid-State Circuits, vol. 36, pp , April K. Bowman, B. Austin, J. Eble, X. Tang, J. Meindl; A physical alpha-power law MOSFET model, IEEE Journal of Solid-State Circuits, vol. 34, pp , October K. Bowman, S. Duvall, J. Meindl; Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol. 37, pp , February K. Bowman, X. Tang, J. Eble, J. Meindl; Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance, IEEE Journal of Solid-State Circuits, vol. 35, pp , August D. Burnett, K. Erington, C. Subramanian, K. Baker; Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits, Proc. Symp. VLSI Tech., pp , June J. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, H. Maes; An easy-to-use mismatch model for the MOS transistor, IEEE Journal of Solid-State Circuits, vol. 37, pp , August P. Drennan, C. McAndrew; A comprehensive MOSFET mismatch model, Proc. IEDM, pp , J. Lohstroh, E. Seevinck, J. de Groot; Worst-case static noise margin criteria for logic circuits and their mathematical equivalence, IEEE Journal of Solid-State Circuits, vol. 18, pp , December Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 39
40 Other Related Articles-2 J. Meindl, V. De, D. S. Wills, J.. Eble, X. Tang, J. Davis, B. Austin, A. Bhavnagarwala; The impact of stochastic dopant and interconnect distributions on gigascale integration, IEEE International Solid-State Circuits Conference, vol. XL, pp , February Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, Review and future prospects of low-power RAM circuits, IBM Journal of Research and Development, vol. 47, no. 5/6, pp , September/November C. Michael, M. Ismail; Statistical modeling of device mismatch for analog MOS integrated circuits, IEEE Journal of Solid-State Circuits, vol. 27, pp , February P. A. Stolk, F. P. Widdershoven, D. B. M. Klaassen; Modeling statistical dopant fluctuations in MOS transistors, IEEE Trans. Electron Devices, vol. 45, pp , Sept X. Tang, V. De, J. D. Meindl; Intrinsic MOSFET parameter fluctuations due to random dopant placement, IEEE Trans. VLSI Syst., vol. 5, pp , Dec X. Tang, V. K. De, J. D. Meindl; MOSFET fluctuation limits on gigascale integration (GSI), 1998 Eur. Solid- State Device Research Conf. (ESSDERC'98), Bordeaux, France, pp , Sept B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier, IEEE Journal of Solid-State Circuits, vol. 39, pp , July S.-C. Wong, K.-H. Pan, D.-J. Ma; A CMOS mismatch model and scaling effects, IEEE Electron Device Lett., vol. 18, pp , June Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 40
Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore
Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic
More informationRECENT technology trends have lead to an increase in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1581 Noise Analysis Methodology for Partially Depleted SOI Circuits Mini Nanua and David Blaauw Abstract In partially depleted silicon-on-insulator
More informationGlasgow eprints Service
Cheng, B. and Roy, S. and Asenov, A. (2004) The impact of random doping effects on CMOS SRAM cell. In, 30th European Solid-State Circuits Conference (ESSCIRC 2004)., 21-23 September 2004, pages pp. 219-222,
More informationLow Transistor Variability The Key to Energy Efficient ICs
Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.
More informationPrepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology
Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology OUTLINE Understanding Fabrication Imperfections Layout of MOS Transistor Matching Theory and Mismatches Device Matching, Interdigitation
More informationLow-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering
Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance
More informationReducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-V t and Dual-T ox Assignment
Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-V t and Dual-T ox Assignment Behnam Amelifard Department of EE-Systems University of Southern California Los Angeles, CA (213)
More informationDesign of Low Power High Speed Fully Dynamic CMOS Latched Comparator
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 10, Issue 4 (April 2014), PP.01-06 Design of Low Power High Speed Fully Dynamic
More informationAnalysis of Low Power-High Speed Sense Amplifier in Submicron Technology
Voltage IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology Sunil
More informationRead/Write Stability Improvement of 8T Sram Cell Using Schmitt Trigger
International Journal of Scientific and Research Publications, Volume 5, Issue 2, February 2015 1 Read/Write Stability Improvement of 8T Sram Cell Using Schmitt Trigger Dr. A. Senthil Kumar *,I.Manju **,
More informationA Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS.
A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS. Abstract This paper presents a novel SRAM design for nanoscale CMOS. The new design addresses
More informationLow Power Design of Successive Approximation Registers
Low Power Design of Successive Approximation Registers Rabeeh Majidi ECE Department, Worcester Polytechnic Institute, Worcester MA USA rabeehm@ece.wpi.edu Abstract: This paper presents low power design
More informationStatic Random Access Memory - SRAM Dr. Lynn Fuller Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Static Random Access Memory - SRAM Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Email:
More informationPROCESS and environment parameter variations in scaled
1078 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006 Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits Ranjith Kumar
More informationDesign and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2
Design and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2 1 ME, Dept. Of Electronics And Telecommunication,PREC, Maharashtra, India 2 Associate Professor,
More informationAtypical op amp consists of a differential input stage,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 915 Low-Voltage Class Buffers with Quiescent Current Control Fan You, S. H. K. Embabi, and Edgar Sánchez-Sinencio Abstract This paper presents
More informationDesign and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm
Journal of Computer and Communications, 2015, 3, 164-168 Published Online November 2015 in SciRes. http://www.scirp.org/journal/jcc http://dx.doi.org/10.4236/jcc.2015.311026 Design and Implement of Low
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 24: Peripheral Memory Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationSeparation of Effects of Statistical Impurity Number Fluctuations and Position Distribution on V th Fluctuations in Scaled MOSFETs
1838 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 10, OCTOBER 2000 Separation of Effects of Statistical Impurity Number Fluctuations and Position Distribution on V th Fluctuations in Scaled MOSFETs
More informationEffect of W/L Ratio on SRAM Cell SNM for High-Speed Application
Effect of W/L Ratio on SRAM Cell SNM for High-Speed Application Akhilesh Goyal 1, Abhishek Tomar 2, Aman Goyal 3 1PG Scholar, Department Of Electronics and communication, SRCEM Banmore, Gwalior, India
More informationDesign and Analysis of Hybrid Current/Voltage CMOS SRAM Sense Amplifier with Offset Cancellation Karishma Bajaj 1, Manjit Kaur 2, Gurmohan Singh 3 1
American International Journal of Research in Science, Technology, Engineering & Mathematics Available online at http://www.iasir.net ISSN (Print): 2328-3491, ISSN (Online): 2328-3580, ISSN (CD-ROM): 2328-3629
More informationA Read-Decoupled Gated-Ground SRAM Architecture for Low-Power Embedded Memories
A Read-Decoupled Gated-Ground SRAM Architecture for Low-Power Embedded Memories Wasim Hussain A Thesis In The Department of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements
More informationFinFET-based Design for Robust Nanoscale SRAM
FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng
More informationDIGITALLY controlled and area-efficient calibration circuits
246 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 5, MAY 2005 A Low-Voltage 10-Bit CMOS DAC in 0.01-mm 2 Die Area Brandon Greenley, Raymond Veith, Dong-Young Chang, and Un-Ku
More informationECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
More informationA Low-Power SRAM Design Using Quiet-Bitline Architecture
A Low-Power SRAM Design Using uiet-bitline Architecture Shin-Pao Cheng Shi-Yu Huang Electrical Engineering Department National Tsing-Hua University, Taiwan Abstract This paper presents a low-power SRAM
More informationLow Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique
Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique M.Padmaja 1, N.V.Maheswara Rao 2 Post Graduate Scholar, Gayatri Vidya Parishad College of Engineering for Women, Affiliated to JNTU,
More informationECEN 720 High-Speed Links Circuits and Systems
1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.
More informationLow-Power and Process Variation Tolerant Memories in sub-90nm Technologies
Low-Power and Process Variation Tolerant Memories in sub-9nm Technologies Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, and Kaushik Roy Dept. of ECE, Purdue University, West Lafayette, IN, @ecn.purdue.edu
More informationPROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS
PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high
More informationSRAM Read-Assist Scheme for Low Power High Performance Applications
SRAM Read-Assist Scheme for Low Power High Performance Applications Ali Valaee A Thesis In the Department of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements for
More informationSCALING power supply has become popular in lowpower
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 59, NO. 1, JANUARY 2012 55 Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
More informationAS THE semiconductor process is scaled down, the thickness
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 7, JULY 2005 361 A New Schmitt Trigger Circuit in a 0.13-m 1/2.5-V CMOS Process to Receive 3.3-V Input Signals Shih-Lun Chen,
More informationDesign and Implementation of High Speed Sense Amplifier for Sram
American-Eurasian Journal of Scientific Research 12 (6): 320-326, 2017 ISSN 1818-6785 IDOSI Publications, 2017 DOI: 10.5829/idosi.aejsr.2017.320.326 Design and Implementation of High Speed Sense Amplifier
More informationSUB-THRESHOLD digital circuit design has emerged as
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006 1673 Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS Benton H. Calhoun, Member, IEEE, and Anantha P. Chandrakasan, Fellow,
More informationSelf-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM
Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, and, Kaushik Roy School of Electrical and Computer Engineering,
More informationA Novel Technique to Reduce Write Delay of SRAM Architectures
A Novel Technique to Reduce Write Delay of SRAM Architectures SWAPNIL VATS AND R.K. CHAUHAN * Department of Electronics and Communication Engineering M.M.M. Engineering College, Gorahpur-73 010, U.P. INDIA
More informationMANY integrated circuit applications require a unique
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008 69 A Digital 1.6 pj/bit Chip Identification Circuit Using Process Variations Ying Su, Jeremy Holleman, Student Member, IEEE, and Brian
More informationDESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM
DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM 1 Mitali Agarwal, 2 Taru Tevatia 1 Research Scholar, 2 Associate Professor 1 Department of Electronics & Communication
More informationFigure 1 Typical block diagram of a high speed voltage comparator.
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 6, Ver. I (Nov. - Dec. 2016), PP 58-63 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Design of Low Power Efficient
More informationTrends and Challenges in VLSI Technology Scaling Towards 100nm
Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends
More information45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random
45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11 Process-induced Variability I: Random Random Variability Sources and Characterization Comparisons of Different MOSFET
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationA High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting Jonggab Kil Intel Corporation 1900 Prairie City Road Folsom, CA 95630 +1-916-356-9968 jonggab.kil@intel.com
More informationAnalyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates
Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates Seyab Khan Said Hamdioui Abstract Bias Temperature Instability (BTI) and parameter variations are threats to reliability
More informationDr. Ralf Sommer. Munich, March 8th, 2006 COM BTS DAT DF AMF. Presenter Dept Titel presentation Date Page 1
DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations in Digital, Analog and Mixed-Signal Circuit Design DATE 06 Munich, March 8th, 2006 Presenter
More informationIntellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM
Intellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM V. Karthikeyan 1 1 Department of ECE, SVSCE, Coimbatore, Tamilnadu, India, Karthick77keyan@gmail.com
More informationInternational Journal of Modern Trends in Engineering and Research
International Journal of Modern Trends in Engineering and Research www.ijmter.com e-issn No.:2349-9745, Date: 28-30 April, 2016 Temperaments in the Design of Low-voltage Low-power Double Tail Comparator
More informationClass-AB Low-Voltage CMOS Unity-Gain Buffers
Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of
More informationSTATISTICAL DESIGN AND YIELD ENHANCEMENT OF LOW VOLTAGE CMOS ANALOG VLSI CIRCUITS
STATISTICAL DESIGN AND YIELD ENHANCEMENT OF LOW VOLTAGE CMOS ANALOG VLSI CIRCUITS Istanbul Technical University Electronics and Communications Engineering Department Tuna B. Tarim Prof. Dr. Hakan Kuntman
More informationSleepy Keeper Approach for Power Performance Tuning in VLSI Design
International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 6, Number 1 (2013), pp. 17-28 International Research Publication House http://www.irphouse.com Sleepy Keeper Approach
More informationMemory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities
Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for
More informationAll Digital on Chip Process Sensor Using Ratioed Inverter Based Ring Oscillator
All Digital on Chip Process Sensor Using Ratioed Inverter Based Ring Oscillator 1 G. Rajesh, 2 G. Guru Prakash, 3 M.Yachendra, 4 O.Venka babu, 5 Mr. G. Kiran Kumar 1,2,3,4 Final year, B. Tech, Department
More informationSRAM cell design has to cope with a stringent constraint
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 2577 Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies Evelyn Grossar, Michele Stucchi, Karen Maex,
More informationSUBTHRESHOLD logic circuits are becoming increasingly
518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008 A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing Tae-Hyoung Kim, Student Member, IEEE,
More informationFOR contemporary memories, array structures and periphery
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005 515 A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories Chiu-Chiao Chung, Hongchin Lin, Member, IEEE, and Yen-Tai Lin Abstract
More informationProcess and Environmental Variation Impacts on ASIC Timing
Process and Environmental Variation Impacts on ASIC Timing Paul S. Zuchowski, Peter A. Habitz, Jerry D. Hayes, Jeffery H. Oppold IBM Microelectronics Division Essex Junction, Vermont 05452, USA Introduction
More informationDigital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation
Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation by Adam Neale A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree
More informationLecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM
Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationCMOS System-on-a-Chip Voltage Scaling beyond 50nm Abstract Circuit and Device Models Introduction
CMOS System-on-a-Chip Voltage Scaling beyond 50nm Azeez J Bhavnagarwala, Blanca Austin, Ashok Kapoor and James D Meindl Microelectronics Rserch. Cntr. and School of Elec. and Comp. Engr., Georgia Institute
More informationReducing Transistor Variability For High Performance Low Power Chips
Reducing Transistor Variability For High Performance Low Power Chips HOT Chips 24 Dr Robert Rogenmoser Senior Vice President Product Development & Engineering 1 HotChips 2012 Copyright 2011 SuVolta, Inc.
More informationBICMOS Technology and Fabrication
12-1 BICMOS Technology and Fabrication 12-2 Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with
More informationIntroduction to VLSI ASIC Design and Technology
Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics
More information12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders
12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders Mr.Devanaboina Ramu, M.tech Dept. of Electronics and Communication Engineering Sri Vasavi Institute of
More informationSUCCESSIVE approximation register (SAR) analog-todigital
426 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 62, NO. 5, MAY 2015 A Novel Hybrid Radix-/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity Manzur Rahman, Arindam
More informationAn Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS Technology
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 10 March 2016 ISSN (online): 2349-6010 An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS
More informationReliability and Energy Dissipation in Ultra Deep Submicron Designs
Reliability and Energy Dissipation in Ultra Deep Submicron Designs 5/19/2005 page 1 Reliability and Energy Dissipation in Ultra Deep Submicron Designs Frank Sill 31 th March 2005 5/19/2005 page 2 Outline
More informationCMOS Process Variations: A Critical Operation Point Hypothesis
CMOS Process Variations: A Critical Operation Point Hypothesis Janak H. Patel Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign jhpatel@uiuc.edu Computer Systems
More informationECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment
1 ECEN 720 High-Speed Links: Circuits and Systems Lab3 Transmitter Circuits Objective To learn fundamentals of transmitter and receiver circuits. Introduction Transmitters are used to pass data stream
More informationIN NANOSCALE CMOS devices, the random variations in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 9, SEPTEMBER 2005 1787 Estimation of Delay Variations due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits Hamid Mahmoodi, Student Member, IEEE,
More informationTHE power/ground line noise due to the parasitic inductance
260 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 Noise Suppression Scheme for Gigabit-Scale and Gigabyte/s Data-Rate LSI s Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe,
More informationCHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS
70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor
More informationDesign of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders B. Madhuri Dr.R. Prabhakar, M.Tech, Ph.D. bmadhusingh16@gmail.com rpr612@gmail.com M.Tech (VLSI&Embedded System Design) Vice
More informationVariability-Aware Design of Static Random Access Memory Bit-Cell
Variability-Aware Design of Static Random Access Memory Bit-Cell by Vasudha Gupta A thesis presented to the University of Waterloo in fulfilment of the thesis requirement for the degree of Master of Applied
More informationKurukshetra University, Kurukshetra, India
Volume 3, Issue 8, August 2013 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Reliability Aware
More informationSingle Ended Static Random Access Memory for Low-V dd, High-Speed Embedded Systems
Single Ended Static Random Access Memory for Low-V dd, High-Speed Embedded Systems Jawar Singh, Jimson Mathew, Saraju P. Mohanty and Dhiraj K. Pradhan Department of Computer Science, University of Bristol,
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 6: RX Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Prelab due now Exam
More informationFinFET-Based SRAM Design
FinFET-Based SRAM Design Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolić Department of Electrical Engineering and Computer Sciences, University of California, Berkeley,
More informationHigh Voltage Operational Amplifiers in SOI Technology
High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper
More informationLecture 11: Clocking
High Speed CMOS VLSI Design Lecture 11: Clocking (c) 1997 David Harris 1.0 Introduction We have seen that generating and distributing clocks with little skew is essential to high speed circuit design.
More informationLow Power, Area Efficient FinFET Circuit Design
Low Power, Area Efficient FinFET Circuit Design Michael C. Wang, Princeton University Abstract FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate
More informationECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier
ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier Objective Design, simulate and test a two-stage operational amplifier Introduction Operational amplifiers (opamp) are essential components of
More informationEFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s
EFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s B.Padmavathi, ME (VLSI Design), Anand Institute of Higher Technology, Chennai, India krishypadma@gmail.com Abstract In electronics, a comparator
More informationDesign and Implementation of less quiescent current, less dropout LDO Regulator in 90nm Technology Madhukumar A S #1, M.
Design and Implementation of less quiescent current, less dropout LDO Regulator in 90nm Technology Madhukumar A S #1, M.Nagabhushan #2 #1 M.Tech student, Dept. of ECE. M.S.R.I.T, Bangalore, INDIA #2 Asst.
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationLSI Design Flow Development for Advanced Technology
LSI Design Flow Development for Advanced Technology Atsushi Tsuchiya LSIs that adopt advanced technologies, as represented by imaging LSIs, now contain 30 million or more logic gates and the scale is beginning
More informationRF-CMOS Performance Trends
1776 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001 RF-CMOS Performance Trends Pierre H. Woerlee, Mathijs J. Knitel, Ronald van Langevelde, Member, IEEE, Dirk B. M. Klaassen, Luuk F.
More informationCHAPTER 3 NEW SLEEPY- PASS GATE
56 CHAPTER 3 NEW SLEEPY- PASS GATE 3.1 INTRODUCTION A circuit level design technique is presented in this chapter to reduce the overall leakage power in conventional CMOS cells. The new leakage po leepy-
More informationLeakage Current Modeling in PD SOI Circuits
Leakage Current Modeling in PD SOI Circuits Mini Nanua David Blaauw Chanhee Oh Sun MicroSystems University of Michigan Nascentric Inc. mini.nanua@sun.com blaauw@umich.edu chanhee.oh@nascentric.com Abstract
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 5, May ISSN
International Journal of Scientific & Engineering Research, Volume 4, Issue 5, May-2013 2190 Biquad Infinite Impulse Response Filter Using High Efficiency Charge Recovery Logic K.Surya 1, K.Chinnusamy
More informationDesign of a Low Voltage low Power Double tail comparator in 180nm cmos Technology
Research Paper American Journal of Engineering Research (AJER) e-issn : 2320-0847 p-issn : 2320-0936 Volume-3, Issue-9, pp-15-19 www.ajer.org Open Access Design of a Low Voltage low Power Double tail comparator
More informationSubthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance
Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance Muralidharan Venkatasubramanian Auburn University vmn0001@auburn.edu Vishwani D. Agrawal Auburn University vagrawal@eng.auburn.edu
More informationAccomplishment and Timing Presentation: Clock Generation of CMOS in VLSI
Accomplishment and Timing Presentation: Clock Generation of CMOS in VLSI Assistant Professor, E Mail: manoj.jvwu@gmail.com Department of Electronics and Communication Engineering Baldev Ram Mirdha Institute
More informationSTATISTICAL MODELING FOR COMPUTER-AIDED DESIGN OF MOS VLSI CIRCUITS
STATISTICAL MODELING FOR COMPUTER-AIDED DESIGN OF MOS VLSI CIRCUITS THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor Related titles:
More informationA High Performance IDDQ Testable Cache for Scaled CMOS Technologies
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies Swarup Bhunia, Hai Li and Kaushik Roy Purdue University, 1285 EE Building, West Lafayette, IN 4796 {bhunias, hl, kaushik}@ecn.purdue.edu
More informationDFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers Muhammad Nummer and Manoj Sachdev University of Waterloo, Ontario, Canada mnummer@vlsi.uwaterloo.ca, msachdev@ece.uwaterloo.ca
More informationDESIGN AND STATISTICAL ANALYSIS (MONTECARLO) OF LOW-POWER AND HIGH STABLE PROPOSED SRAM CELL STRUCTURE
DESIGN AND STATISTICAL ANALYSIS (MONTECARLO) OF LOW-POWER AND HIGH STABLE PROPOSED SRAM CELL STRUCTURE A Thesis Submitted in Partial Fulfilment of the Requirements for the Award of the Degree of Master
More informationStudy of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology
109 Study of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology V.S.Raju Mandapati 1, Nishanth P V 2 and Roy Paily 3 1 Dept of Electronics and Communication Engineering Indian Institute
More informationLeakage Power Reduction by Using Sleep Methods
www.ijecs.in International Journal Of Engineering And Computer Science ISSN:2319-7242 Volume 2 Issue 9 September 2013 Page No. 2842-2847 Leakage Power Reduction by Using Sleep Methods Vinay Kumar Madasu
More information