Study of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology

Transcription

1 109 Study of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology V.S.Raju Mandapati 1, Nishanth P V 2 and Roy Paily 3 1 Dept of Electronics and Communication Engineering Indian Institute of Technology, Guwahati, Assam Dept of Electronics and Communication Engineering Indian Institute of Technology, Guwahati, Assam Dept of Electronics and Communication Engineering Indian Institute of Technology, Guwahati, Assam Abstract As Integrated Circuit(IC) technologies scale to 90nm and beyond, process variations become increasingly critical and make it continuously more challenging to create a reliable and a robust circuit design. The classical differential amplifier can designed to be robust to inter-die variation, but it is extremely sensitive to device mismatches. In this paper the effect of the transistor mismatches on the performance of Classical Differential Amplifier (CDA) is studied. Three different circuit modifications are investigated to mitigate the mismatch effects and comparative analysis of each circuit is given. The simulation is carried out using PTM High Performance 32nm Metal Gate / High-K / Strained-Si technology with Hspice. Keywords: Analog circuit design, Transistor mismatch, 32 nm CMOS Technology, Differential Amplifier, Common Mode Feedback. 1. Introduction The unending demand on speed, complexity, circuit density and power consumption posed by many advanced applications leads to steady down scaling of CMOS technologies. With the downsizing of CMOS technology, the circuit performance is largely increased in terms of speed and power while analog figure of merit, such as transistor gain and output swing are degraded. The reliable circuit design at nano scale is really a challenging task because of large process variations and device mismatches [1], [2], [3]. The International Technology Roadmap for Semiconductors (ITRS) in their recent updates posed many challenges especially for below 32 nm concerning with fluctuations and statistical process variations. One have less than 30 dopants in a typical 32 nm technology node device and the random fluctuations dopants are a major concern. The process variations include random dopant fluctuations (RDF), gate thickness variations and line-edge roughness (LER) [4], [5]. The well-known Pelgrom model has demonstrated that the size dependence mismatch is proportional to the inverse of the square-root of the area [6], [7], [8], i.e., where the proportionally constant A VT characterizes the matching performance of technology. Using this law, it is seen that the accuracy of a MOSFET can be increased by increasing its width or length. However, an increase in the width of a MOSFET results in a larger current and thus power dissipation. Most analog circuit designs (e.g differential pair, switched-capacitor amplifier etc.) are ratio-based [9]; namely, their behaviors depends on the ratio between two analog device sizes and not on their absolute sizes. These analog circuits can be designed to be robust to inter-die variations, but they are extremely sensitive to device mismatches [2]. The influence of process variations on the Halo MOSFETs, its implications on the analog circuit performance and effect of transistor mismatch on fully differential Operational Tran conductance Amplifier (OTA) has been studied earlier [10], [11]. The LER remains typically in the order of 5 nm, almost independently of the type of lithography used for research or production [12] and this corresponds to about 15% variation in device dimensions at 32nm technology. Such kind of variations in device sizes will affect adversely the device performance and this paper discusses the effect of (1)

2 110 transistor s aspect ratio mismatch on the performance of classical differential amplifier (CDA) topology at 32 nm technology. The differential pair is among the most important circuit inventions, dating back to the vacuum tube era. As technology progresses, its importance had been realized with both bipolar and MOS transistors. Offering many useful properties, differential operation has become the dominant choice in today s high-performance analog and mixed-signal circuits. We also have investigated how much device dimension mismatch a classical differential pair between signal or load transistors can tolerate. With appropriate feedback circuits, it is possible to mitigate the adverse effects of device mismatch to some extent. Three different circuit modifications such as source degenerated resistive feedback, splitting of signal transistors and common mode feedback are studied to mitigate the mismatch effects and comparative analysis of each circuit is given. However these techniques will introduce degradation in some performance parameters. Therefore, we also have introduced current cancelation techniques using cross-coupled pair of transistors to reduce the degradation in the circuit performance. The analysis and effect of transistor mismatch is presented in section 2. The circuit modifications and simulation results are given in section 3 and section 4 concludes the paper. 2. Study of Transistor Mismatch In CMOS Differential Amplifier The most common design approach of a differential amplifier is to have MOS transistors operated in strongly inverted region as they provide the most important advantage of better frequency response compared to the subthreshold-operated MOS differential amplifiers. The objective of the differential amplifier is to amplify only the difference between two voltages regardless of common mode value. Two important characteristics of a differential amplifier are CMRR and offset voltage. For an ideal differential amplifier, the common mode gain should be zero and thus CMMR should be infinite, also the input offset voltage should be zero. For CMOS differential amplifiers, the effect of mismatch on dc performance is most conveniently represented by the input offset voltage. It represents the input-referred effect of all the component mismatches within the amplifier on its dc performance [13], [14], [15]. The input offset voltage V OS is equal to the value of differential input voltage V ID that must be applied to the input to drive the differential output voltage V OD to zero. The classical differential amplifier with mirror load is shown in Fig.1. The n-channel MOSFETs M1 and M2 forms the differential pair, M3 and M4 acts as a mirror load and it is biased with current sink. The current sink is implemented using M5 and M6. The designed (W/L) ratios are indicated in brackets. All the transistors are set to operate in saturation region by biasing different nodes using appropriate dc potentials. The sensitivity of each node dc potential with respect to device mismatch is investigated. The dc signals of the amplifier be V in+ = V I1, V in- = V I2, V o = V O1 and V m = V M. The V I1, V I2 are differential input voltages and V o1, V M are output and mirrored node voltages. Let V ID be V I1 - V I2. The KVL around the input loop gives. the gate-source voltage can be written as (2) (3) For output dc differential voltage V OD = V 01 -V M to be zero, with a constraint that voltage drop across both load transistors be equal, then input offset voltage can be written as The mismatch between any two nominally matched circuit parameters is usually small compared with the absolute value of the parameters. The approximate equation of the offset voltage V OS is given in equation (4). By defining the difference & average of all the parameters, such as I D & I D, W/L & W/L, V t & V t and by substituting all the difference & average values in above equation (4), The above analysis is carried by assuming long channel equation. For a 15% mismatch in aspect ratio results in an offset value of -21mV. Typically, the variations will be larger in short channel devices. The MOS transistors M2 and M4 will have same current. Therefore, In equation (6),,, are constant, defined by technology and input bias voltage. The dependence of output node voltage with the aspect ratio of M2, M4 is known. (4) (5)

3 111 The variation of node voltage directly results from the variation in aspect ratio. The mirrored node is a shortcircuited node between gate and drain of M3 so it attains a constant value because of interdependence between i D3 and V SG3. The MOS transistors M3, M4 will acts as current mirror. Therefore, the ratio of i D3 and i D4 for (W/L) 3 = (W/L) 4 is given in equation (7). (7) Figure 3. Output signal swing and THD variation as a function of transistor mismatch percentage Figure 1. Differential Amplifier The classical differential amplifier is biased with tail current sink M5 for high CMRR and PSRR. It keeps the total current constant irrespective of both branch mismatches. The aspect ratio mismatch results in an unequal current through M1 and M2. As the total current through M5 is constant, the difference in current through branch will be mirrored to output node. The dependence of output node voltage with the currents of both branches is known from equation (7). Figure 2. DC Gain and Bandwidth variation as a function of transistor mismatch percentage Using Hspice, a simple mirror load differential amplifier is designed at 32nm for optimum area occupancy and performance in terms of dc gain, unity gain bandwidth and power dissipation at a load capacitance of 5pF are evaluated. Though the mismatch of each and every transistor is studied, it has been seen that the signal transistor mismatch affect the circuit performance appreciably and therefore in this paper we have focused on signal transistor mismatches. Henceforth, whenever mismatch is mentioned, unless otherwise specified, we mean the transistor width mismatch. The dc gain, 3-dB bandwidth, output swing and total harmonic variation (THD) with respect to transistor mismatch is shown in Fig. 2 and Fig. 3 respectively. The transconductance is reduced as mismatch is increased and therefore the DC gain is affected. The Unity Gain bandwidth (UGB) is not affected much with mismatches and the bandwidth is increased corresponding to the decrease in dc gain. The decrease in dc gain also causes the peak-to peak amplitude to decrease as the mismatch is increased. The THD is increased initially because the mismatch drifts the operating point thereby reducing the maximum swing possible. The high gain and lower swing at 0.5% mismatch yields worst case THD. As the mismatch increases further, the gain is reduced and thereby the THD is reduced. We have investigated how much device dimension mismatch a classical differential pair between signal or load transistors can tolerate. One of the transistors leave saturation region when the width mismatch of signal transistors is exceeded beyond 16% under fixed biasing conditions. 3. Mitigation of Mismatch Effects Using Different Modified Circuits It has been already demonstrated that the output node dc voltage of the classical single-ended differential

4 112 amplifier is very sensitive to transistor mismatch and some transistors leave saturation when the width mismatch of signal transistors is exceeded beyond 16% under fixed biasing conditions. Three different circuit modifications such as source degenerated resistive feedback, splitting of signal transistors and common mode feedback are designed to mitigate the mismatch effects and comparative analysis of each circuit is given. Each design is carried out using similar biasing conditions and the performance parameter such as DC gain, 3-dB bandwidth, output swing and total harmonic variation (THD) with respect to transistor mismatch is studied. 3.1 Source degenerated resistive feedback The classical differential amplifier with degenerated resistive feedback is shown in Fig. 4. The resistor R S acts as degenerated resistive feedback. Generally for high gain amplifiers the value of g m will be in ms, so the value of R S should be in kω. The effect of feedback is significant when the desensitivity factor g m1,2 R S is greater than unity. The degenerative resistors create a negative feedback and it makes sure that current in both branches to be the same for a constant gate voltage irrespective of variation in the aspect ratio of signal transistors M1 and M2 By applying KVL at input signal transistors of Fig. 4 (8) By differentiating above equation with respect to gives We can rewrite the equation (7) as By replacing we get (10) (12) (11) From the above equation (10) we can clearly state that the both branch currents will be equal due to negative feedback for any variation in the aspect ratio of input transistors. In practice, placing high value of degenerative resistor pushes tail transistor into linear region of operation for cases where signal transistor mismatch exceeds 17.5%. Therefore, the degenerative resistive feedback will not provide sufficient insensitivity to node potentials for appreciable aspect ratio variations. However, it is typically used to increase the differential input range of the amplifier. The output swing of the amplifier is also degraded due to voltage drop across the source resistors and the corresponding plots will be discussed later in Fig.6&7 when all circuit topologies are compared. 3.2 Splitting of signal transistors In classical differential amplifier the output node voltage drifts for a smaller value of mismatch and pushes either M2 or M4 into linear region of operation. The classical differential amplifier with splitting of signal transistors is shown in Fig. 5. The signal transistors M1 and M2 are split into M1, M7 and M2, M8 respectively. The motivation for transistor splitting is based on the random nature of mismatch and therefore is on the assumption that transistor with reduced mismatch can mitigate the effect of a higher mismatched transistor. The splitting is carried out keeping the total device dimensions and thereby the circuit performance the same. For the split circuit, the dependence of node potentials with aspect ratios is given in equation (13). Figure 4. Differential amplifier with degenerated resistive feedback (13) By replacing we get (9) The random nature of device mismatch may favor splitting of transistors however, the overall mismatch increases as the transistor sizes are reduced and therefore it has been seen that the performance of this topology is same as that of mirror load differential amplifier. Each

5 113 signal transistor has tolerated up to 16% mismatch and the corresponding plots are shown in Fig. 6 & 7 where all circuit topologies are compared. Figure 5. Fully Differential amplifier with multiple signal transistors Figure 6. Output Swing variation of differential amplifier, differential amplifier with source degenerative resistor and differential amplifier with split transistor. Figure 7. THD variation of differential amplifier, differential amplifier with source degenerative resistor and differential amplifier with split transistor. even for a small variation in aspect ratio. To balance out the large output node drift, we have employed resistive common-mode feedback (CMFB) shown in Fig. 8. The resistors R f1 & R f2 act as common-mode feedback paths. This feedback circuit is expected to keep all the transistors in saturation for a wide range of aspect ratio variations of any transistors. The acceptable range of variation depends upon the value of the feedback resistors and the resistors will influence the gain of the circuitry. The gain is given in equation (12) and by assuming R f1 = R f2 = R f. (14) By using value of 40k one can tolerance up to 50% mismatch in the aspect ratio of either signal or load transistors. Nevertheless, with value of 40k, the gain of the circuit is very low. The DC gain and DC Common Mode Rejection Ratio (CMRR) with respect to % of mismatch is shown in Fig. 9 and 10. Compared to CDA, for circuit with CMFB the gain remains constant for a wide range of signal transistor mismatch. However, the gain for circuit with CMFB reduced by 28dB compared to CDA. Similar trend is observed for CMRR also. The CDA and split circuit yielded similar performance for output signal swing and THD. The output signal swing is degraded for source resistance case due to additional drop across the resistor. The THD is increased initially because the mismatch drifts the operating point thereby reducing the maximum swing possible. The high gain and lower swing at 0.5% mismatch yields worst case THD for all cases. 3.3 Common-mode resistive feedback It is observed in CDA that only a very small variation in voltage at the mirrored node is resulted for a wide range of device aspect ratio mismatch, whereas voltage at output node is drifted largely Figure 8. Fully Differential amplifier with resistive common-mode feedback

6 114 Table 1. Performance of differential amplifiers with different topologies at 32nm Parameters Units Fig.1 #1 Fig.4 #2 Fig.5 #3 Fig.8 #4 DC gain db dB B W khz UGB MHz P.M degrees L.D.R Volts(V) DC CMRR db DC PSRR db Power µwatts o/p signal swing m Volts T.H.D % #1 - CDA, #2 - Differential with source resistor, #3- Split Transistors, #4 CMFB Topology positive feedback affects adversely the amplifier stability. The condition required for adequate negative phase shift is given in equation (15). Fig. 10 DC CMRR variation of differential amplifier with and without CMFB The performance variations of all the above topologies with respect to transistor mismatch is summarized in Table 1. The linear differential range (LDR) of CDA is increased for circuit with source resistor. However its unity gain bandwidth and output signal swing are reduced. The circuit which effectively tolerate mismatch is CDA with CMFB, however gain and UGB with CMFB is degraded. Figure 11. Fully-Differential amplifier with resistive feedback and crosscoupled load. Figure 9. DC gain variation of a differential amplifier with and without CMFB In summary, the performance parameters such as DC gain, output signal swing, UGB and LDR are largely degraded for the circuit modification suggested. The effect of transistor mismatch can be better mitigated up by using common mode resistive feedback. Though the gain and UGB are affected the performance parameters such as dc gain can be improved by using cross- coupled pair with current cancellation. The classical differential amplifier with resistive common-mode feedback and cross-coupled load is shown in Fig. 11. The resistor R f acts as commonmode feedback resistor, the cross-coupled pair transistors M7 & M8, provides a negative resistance load of the amplifier and enhances the gain depending on ratio g m7 and R f. High value of current cancellation results in (15) (16) The relation between node potentials and the aspect ratio s is given in equation (16). In this topology, the gate potential of M7 & M8 also varies and therefore cannot tolerate for wide range of aspect ratio variation. The performance improvements are summarized in Table-II. In each circuit, the biasing current is fixed and therefore the power remains the same. The DC gain is increased at the cost of bandwidth and unity gain bandwidth of both the

7 115 topologies remains constant. The CMRR as well as output signal swing also is increased in the modified circuit with cross-coupled transistors. Table II. Performance of differential amplifiers with CMFB and crosscoupled load at 32nm Parameters Units Fig.8 #1 Fig.11 #2 DC gain db dB B W khz UGB MHz P.M degrees L.D.R Volts(V) DC CMRR db DC PSRR db Power µwatts O/P signal swing m Volts T.H.D % #1 Differential amplifier with CMFB, #2 Differential amplifier with CMFB and cross-coupled load 4. Conclusions It was observed that in classical differential amplifier one cannot keep all the MOS transistors in saturation for signal transistor mismatches beyond 16% at fixed biasing condition with 32nm technology. Three different circuit modifications such as source degenerated resistive feedback, splitting of signal transistors and common mode feedback were studied to mitigate the mismatch effects and comparative analysis of each circuit was given. The common mode feedback amplifier can withstand a larger variation in aspect ratio as compared to its other counterparts. The effect of transistor mismatch can be mitigated up to 50% by using common mode resistive feedback though at the expense of gain and unity gain bandwidth. The degradation in the gain was reduced by using current cancelation technique using cross-coupled transistor pair Acknowledgments This work is carried using VLSI design softwares provided by Department of Information Technology (DIT), India through SMDP II project at IIT Guwahati. Authors would like to acknowledge Semiconductor Research Corporation for the financial support for the project staff to carry out this work. References [1] Lewyn,L.L;Ytterdal,T.;Wulff,C.;Martin,K.; Analog circuit design in nano scale CMOS technologies, in Proceedings of the IEEE, vol. 97, no. 10, Oct. 2009, pp [2] Lawrence T.Pileggi, Pittsburgh,PA(US);Xin Li, Pittsburgh, PA(US) Tunable integrated circuit design for nano-scale technologies, in Patent, Agents: Oppedahl Patent Law Firm LLC - SRC Assignees, Sept. 2005, pp [3] Y. C. Xin Li, Brian Taylor and L. T. Pileggi, Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization, in IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2007), no. 4-8, Dec. 2007, pp [4] N. G. G. D. N. Emad Hamadeha and M. Rahmana, Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics, in International Symposium on Semiconductor Device Research, 2005, Dec. 2005, p [5] K. Kuhn, CMOS transistor scaling past 32nm and implications on variation, in Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI, July 2010, p [6] W. S. Jeroen, A. Croon and H. E.Maes, Matching Properties of Deep Sub-Micron MOS Transistors, Springer, [7] Pelgrom,M.J.M.;Duinmayer,A.C.J.;Welbers,A.P.G; Match ing properties of MOS transistors, in IEEE Journal of, Solid-State Circuits, vol. 24, no. 5, Oct. 1989, pp [8] Pelgrom,M.J.M.; Tuinhout, H.P.;Vertregt,M.; Transistor matching in analog CMOS applications, in Technical Digest. of International Electron Devices Meeting, 1998 (IEDM 98), Dec. 1998, Vol. 2, pp [9] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill., [10] J. Silva-Martinez, Effect of the transistor mismatches on the performance of fully-differential OTAs, in IEEE International Symposium of Circuits and Systems, (ISCAS 94), 1994, Aug. 2002, Vol. 5, pp [11] S. G. K.Narasimhulu and V. Rao, The influence of process variation on the halo MOSFETs and its implications on the analog circuit performance, in Proceedings of 17 th International Conference on VLSI Design, 2004, Aug. 2004, pp [12] S. B. A. Asenov and A. Kaya, Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness, in IEEE Transactions on Electron Devices, July 2003, Vol. 50, no. 5, p [13] R. D. Middlebrook, Differential Amplifiers, John Wiley and Sons, New York., [14] L. J. Giacoletto, Differential Amplifiers, John Wiley and Sons, New York., [15] S. H. R. G. M. Paul R. Gray, Paul J. Hurst, Analysis and design of Analog Integrated Circuts, fourth edition. John Wiley and Sons, Inc., Bowman, M., Debray, S. K., and Peterson, L. L