Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies

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1 Low-Power and Process Variation Tolerant Memories in sub-9nm Technologies Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, and Kaushik Roy Dept. of ECE, Purdue University, West Lafayette, IN, Abstract Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-scale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, selfrepairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub- 9nm technologies. AXL V L = NL PL WL VDD V R = NR PR AXR I. INTRODUCTION /6/$2. 26 IEEE 55 BL Subthreshold leakage ( I ) sub Gate leakage ( I ) gd Junction leakage ( I ) jn Increasing inter-die and intra-die variation in process parameters, such as, channel length, threshold voltage etc., have emerged as a major challenge in circuit design in nanometer regime [-2]. The random intra-die variations in the process parameters can result in a mismatch in the strength between the neighboring transistors in an cell [2,3]. Due to the small geometry of the transistors used in cell, the primary source of the intra-die variation is the Vt variation due to Random Dopant Fluctuation. RDF induced Vt variations, can result in functional failures, namely, read, write, access and hold failures in an cell. These functional failures, collectively called parametric failures, reduce the memory yield (i.e. the number of non-faulty chips) [2, 3]. Moreover, the die-to-die variation in device parameter (say, threshold voltage) also has a strong impact on cell failures [4]. The different types of parametric failures increase at different inter-die process corners thereby further degrading the design yield. In particular, low-vt dies suffer mostly from the read and hold failures while high-vt dies suffer from access and write failures (described in detail in section-ii). Increase in cell area or use of higher redundancy can improve the cell robustness against intra-die variation [3]. However, higher cell area or large redundancy increases the leakage current (and hence power dissipation) in memory arrays. Further, the inter-die variation in device parameter (e.g. Vt) also results in a large leakage spread among the different dies []. Hence, techniques to simultaneously reduce parametric failures and leakage spread in array are necessary in nano-meter regime. In this paper, we show the opportunities of using postsilicon adaptive repair technique for designing low power and process variation tolerant in sub-9nm nodes. In particular, we present: A self-repairing which uses leakage monitor and body-bias to simultaneously improve parametric yield and reduce leakage spread. A self-adaptive source-bias scheme for reducing leakage in while maintaining hold failures under control. Our analysis shows that, post-silicon self-repair and self- Fig. : Cell storing at node R. adaptive techniques are essential for designing low-power and robust memories in nanometer nodes. II. PARAMETRIC FAILURES Increasing statistical variations in the process parameters (channel length (L), width (W), and transistor threshold voltage (Vt)) has emerged as a serious problem in the nanoscaled circuit design [2-4]. The inter-die parameter variations, coupled with the intrinsic on-die variation in Vt due to random dopant fluctuation, can result in failure of cells [3, 4]. A cell failure can occur due to: an increase in the cell access time (access failure), unstable read/write operations (read/write failure), or (c) failure in the data holding capability of the cell at a lower supply voltage (hold failure in the standby mode). A failure in any of the cells in a column (or row) of the memory will make that column (or row) faulty. If the number of faulty columns (or rows) in a memory chip is larger than the number of redundant columns (or rows), then the chip is considered to be faulty [3]. Hence, the failure probability of a cell is directly related to the yield of a memory chip. Consequently, estimation of the failure probability for a cell is necessary in the design phase to ensure a good yield. We have developed a method to predict the yield of a memory chip under inter-die variation of L, W and Vt by estimating the failure probability of the cell considering intra-die parameter variation [3]. The proposed method is used to optimize the design of cell (i.e. transistor sizes) and array (array organization and redundancy) to minimize the memory failure probability due to random intra-die variation [3]. Such a presilicon design level optimization helps to improve yield to a certain extent. However, due to constraints on memory area/leakage, design level optimization is not sufficient to improve yield under large variation. In the next two sections, we have used the developed estimation method to show the effectiveness of post-silicon self-repair and self-adaptive BR Authorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on April 3,2 at 22:53:6 EDT from IEEE Xplore. Restrictions apply.

2 5 Failure Region A Region B Region C Hold Access memory failure Overall cell failure Inter die Vt Shift [V] Write Read Fig. 2: Analysis of Self-repairing : cell and memory failure probability with inter-die Vt shift, effect of body-bias on cell failure, and (c) yield improvement with self-repairing technique (simulations in predictive 7nm technology [5]) techniques for yield enhancement and leakage reduction. number of dies in region A, B, and C are N A, N B and N C, respectively. Hence, yield can be obtained as [3, 4]: III. SELF-REPAIRING USING BODY BIAS PN A A + PN B B + PN C C NB In this section, we present a circuit technique which monitors Yield = = () the leakage of an array to detect the inter-die process N A+ NB + NC NA + NB + NC corner of memory chip, and applies proper body bias to reduce where, P A (~), P B (~), and P C (~) are the memory failure inter-die shift [4]. We show that through correct body biasing, probabilities in the region A, B and C. Hence, to improve yield, the parametric yield of can be improved significantly. N A and N C have to be reduced (in other words N B needs to be increased). This can be achieved by applying RBB to the dies in A. Effect of Inter-die Vt shift on Cell Failures region A thereby reducing their read and hold failure probability. A Vt shift toward low Vt process corners, due to inter-die Similarly, application of FBB to the chips in region C reduces variation, increases the read and the hold failures of s (Fig. their write and access failure probability. This effectively, 2a). This is because of the fact that, lowering the Vt of the cell increases the Vt(inter) window for region B (higher N B and transistors increases V READ and V TRIPRD, thereby increasing read lower N A & N C ) and improved parametric yield (Fig. 2c) [4]. failures [4]. The negative Vt shift increases the leakage through the transistor N L, thereby, increasing the hold failures. On the other hand, for arrays in the high-vt process corners, the probabilities of access failures and write failures are high (Fig. 2a) [4]. This is principally due to the reduction in the current drive of the access transistors. The hold failure also increases at the high Vt corners, as the trip-point of the inverter PR-NR increases with positive Vt shift. Hence, the overall cell failure increases both at low and high-vt corners and is minimum for arrays in the nominal corner (Fig. 2a). Consequently, the probability of memory failure is high at both low-vt and high-vt process corners (Fig.2b). B. Effect of Body-bias on Cell Failures Let us now discuss the effect of the body-bias (applied only to NMOS) on different types of failures. Application of reverse body-bias increases the Vt of the transistors which reduces V READ and increases V TRIPRD, resulting in a reduction in the read failure (Fig. 2b) [4]. The Vt increase due to RBB also reduces the leakage through the NMOS thereby reducing hold failures (Fig. 2b). However, increase in the Vt of the access transistors due to RBB increases the access and the write failures. On the other hand, application of FBB reduces the Vt of the access transistor which reduces both access and write failures. However, it increases the read (V READ increase and V TRIPRD reduces) and hold (leakage through NMOS increases) failures (Fig. 2b) [4]. x 3 The Cell is sized to have equal probablities for different failure events at ZBB.8 Overall Cell Write Failure Failure C. Application of Adaptive Body Bias to Enhance Yield From Fig. 2c, it can be observed that, above a certain Vt-shift (~mv) small changes in inter-die Vt results in a large memory failure probability (regions A and C). However, for chips with Vt in the window of -mv to mv (region B) the memory failure probability is negligible. Let us further assume that the Failure Access Failure Hold Failure Read Failure Body Bias [V] Yield [%] KB Self Reparing 256KB Self Reparing 5 64KB 4 with ZBB 3 256KB with ZBB Std. dev of inter die Vt distribution [V] D. Vt bining using Monitors To determine the correct body bias to apply to the chip for failure probability improvement, the inter-die process corner of a memory chip needs to be determined. The detection of the interdie Vt corner (in the presence of large intra-die Vt variation due to RDF) of a die can be achieved by monitoring the leakage of a large array (instead of monitoring the leakage of a single transistor or cell). distribution due to random within-die Vt variation of a cell from low inter-die Vt corner can overlap with that of a cell from high inter-die Vt corner (Fig. 3a). However, since leakage of a large array is the sum of the leakage of all the cells, the leakage distribution of the arrays (due to within-die Vt variation) from different inter-die corners are well separated (following Central Limit Theorem [6]). Hence, # of Occurance Vt inter = mv Vt inter = mv Vt inter = mv Cell [na] Fig. 3: Effect of random intra-die Vt variation at different interdie Vt corners: leakage distribution (due to intra-die variation) of an cell, leakage distribution (due to intra-die variation) of the KB array (predictive 7nm device [5]) 56 # of Occurances High Vt (c) Nominal Vt Memory Size = KB Temparature = 27C Vt Inter=mV Low Vt Vt Inter= mv Vt Inter=mV 2 3 Memory [µa] Authorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on April 3,2 at 22:53:6 EDT from IEEE Xplore. Restrictions apply.

3 Bypass Switch Calibrate Signal V DD Online Monitor V out V REF V REF2 Comparator # of Failures No-body-bias (256KB) Self-repairing (256KB) Array V body Body-Bias Generator Inter-Vt sigma (mv) Fig. 4: Self-repairing : block diagram, Reduction in number of failures in 256KB memory array leakage of an entire array can be used to detect the inter-die shift in Vt even under a large random intra-die variation (Fig. 3b) [4]. E. Self-Repairing using Monitoring In a Self-repairing using Monitor, the leakage (memory leakage) of the die is monitored using an online leakage monitor. The monitor generates an output voltage (Vout) that is proportional to the leakage of the array. The output of the leakage monitor is compared with the reference voltages corresponding to the different inter-die process corners. Based on the results of this comparison, the body bias generator applies the right body bias to the array. For example, if an die is in the low inter-die Vt corner, the output of the leakage monitor (Vout) will be greater than both the reference voltages (V REF and V REF2 ) and both comparators generate zero, resulting in application of a reverse body bias (RBB). To avoid any performance loss due to the voltage drop across the leakage monitor (which is in the supply path) it is bypassed in the regular mode of operation. The schematic of a self-repairing array is shown in Fig. 4a. Fig. 4b shows the reduction of number of failures in 256KB memory array shifted to different inter-die corners using self-repairing technique described above for 7nm predictive technology [5]. Fig. 2c shows that, the self-repairing improves parametric yield by 8-25%. F. Spread Reduction using Self-Repairing The total leakage of an cell in bulk silicon technology is composed of the subthreshold, the gate and the junction tunneling leakage [7]. Considering random intra-die variation in Vt, the leakage of different cells (L Cell ) in a memory can be modeled as independent Lognormal random variables [4]. Using the central limit theorem, the distribution of the overall memory leakage (L MEM ) (summation of leakage of all the cells, say N cell ) can be assumed to be Gaussian with mean (µ MEM ) and the standard deviation (σ MEM ) given by [6]: µ = N µ and σ = N σ (2) MEM Cell Cell MEM Cell Cell Hence, the probability that L MEM is less than a maximum allowable limit (L MAX ) is given by: LMAX µ MEM PLeakMEM = P[ LMEM < LMAX ] = Φ (3) σ MEM Considering the inter-die Vt variation, the ratio of the number of chips that meet the above leakage bound to the total number of chips (i.e. yield, L Yield )can be obtained as: N INTER LYield = PLeakMEM ( VtINTER ) NINTER INTER= (4) An increase in L Yield represents a design with a lower leakage spread. As shown in Fig. 3 inter-die shift in process parameters can significantly leakage of an die. Hence, inter-die variation increases the leakage spread and degrades L Success. Application of FBB increases subthreshold leakage of a cell, whereas, application of RBB reduces it [7]. On the other hand, application of RBB increases reverse junction tunneling leakage while FBB reduces it (Fig. 5a) [7]. The gate leakage of the cell is less sensitive to body bias (Fig. 5a) [7]. The application of selfrepairing technique also reduces the spread in the inter-die leakage spread. This is because of the fact that, application of RBB to the arrays in the low-vt corner reduces their subthreshold leakage, while FBB to the arrays in the high-vt corner increases Normalized Cell Current Junction Max FBB Maximum Bound Total Subthreshold Gate # of Occurance High Vt FBB Nom Vt ZBB Self repairing Low Vt RBB Yield (L Yield ) [%] ZBB Design Predictive 7nm device 64KB Array Self Repairing Body Bias [V] Mean Memory [A] Std. Dev of Inter Die Vt Shift [V] (c) Fig. 5: Self-repairing and leakage current (predictive 7nm device): effect of body bias on cell leakage, leakage spread with self-repairing, (c) leakage yield with self-repairing (64KB array). 57 Authorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on April 3,2 at 22:53:6 EDT from IEEE Xplore. Restrictions apply.

4 [V] P HF =.E -3 Memory size = 2KB (adaptive)[v] KB memory Vt inter [V] Fig. 6: Source biasing voltage for a target hold failure probability under inter-die variation the subthreshold leakage (Fig. 5b). Hence, self-repairing improves the number of chips that satisfy the given leakage bound (i.e. L Yield ) (Fig. 5c). Application of a very high forward bias or reverse bias may significantly increase the diode leakage or junction tunneling leakage, respectively. Hence, the maximum FBB and RBB that can be applied to a cell are bound by the effect of body-bias on the cell leakage. Calibrate EN DE counter N D/A Converter PULSE STOP VSB BIST Controller Register bank and counter address March Test Algorithms Cell Group data Fig. 7: Block diagram of the self-adaptive scheme for source-biasing for designing low-power. 58 P HF Vt inter [V] V = V (adaptive) SB SB = (opt).2 2KB Memory.2. Vt [V] inter..2 Fig. 8 Self-adaptive source bias scheme: Adaptive sourcebiasing voltage for different inter-die corners ( (opt)=.63), hold failure probability with inter-die variation for (opt) and (adaptive) IV. SELF-ADAPTIVE SOURCE-BIASING FOR LOW-POWER Source-biasing is an effective technique to reduce the leakage power of array in stand-by mode [8, 9]. In this technique, in the stand-by mode, voltage of the source line is increased to reduce the leakage currents. Since, inter-die variation modifies the leakage of an array shifted to different interdie corners different source-bias is required at different inter-die corner to keep the leakage power under control. In particular, for dies shifted to low-vt corners, a higher source bias will be more helpful as leakage is higher. On the other hand, for dies shifted to high-vt corner, a much lower source bias is sufficient as the leakage itself is very low []. On the other hand, under parameter variation, a non-zero source bias can increase hold-failure probability (as rail-to-rail supply reduces). Moreover, as shown in Fig. 2a, the hold-failure probability also changes with a change in inter-die process shift. In particular, a negative inter-die Vt shift increases the holdfailure probability significantly (higher leakage). A positive interdie Vt shift beyond a certain point also starts increasing the hold failures (higher trip-point of the inverter associated with the node storing ). Hence, to achieve a certain hold failure probability, different source bias is required at different inter-die corner [] (Fig. 6). The applicable bias is maximum at the nominal corner and reduces with both positive and negative inter-die shift []. Form the above discussion, it can be concluded that a fixed may not be used across all the chips to meet a target holdfailure probability. In general, must be increased to reduce the standby power as much as possible. However, the maximum at an inter-die corner is ultimately limited by the hold failures. Hence, a self-calibration scheme is required to reduce the number of dies failing due to excessive leakage (i.e. improve leakage yield) while keeping yield loss due to hold failures under control []. Fig. 7 shows the block diagram of a self-calibration system for adaptive source biasing. In an initial calibration cycle, it determines the value of source bias and subsequently uses this value during standby mode of the memory. The self-calibration system consists of a Built-in Self-Test (BIST) circuit to perform read and write operations on the memory array. The source bias is generated by converting a digital counter value to an analog voltage. The counter value is incremented by the BIST controller. The BIST maintains a register bank of size xnc (where NC is the number of columns in the memory array) to store the faulty column information. Each register corresponds to an entire column. The register bit is set to if a fault is detected in any row of that column. Another counter (inside the BIST) keeps track of the total number of registers with value. The counter value indicates the number of faulty columns in the array. The counter value greater than NRC for a particular, indicate that all redundant columns have been used. Therefore, the present can be considered as adaptive source bias value, (adaptive). Figure 8 shows the adaptive source bias value for a 2KB memory array (designed in predictive 7nm technology, 5% redundancy is assumed) shifted to different inter-die corner obtained using the self-adaptive scheme. In the absence of the self-adaptive scheme, we could apply (opt) (which is determined at the design level considering standby power and performance at the nominal interdie corner []) to all the dies. However, it can be observed from self-adaptive scheme widens the low hold Authorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on April 3,2 at 22:53:6 EDT from IEEE Xplore. Restrictions apply.

5 # of occurrences # of occurrences # of occurrence (adaptive) distribution due to intra die variation for all the chips at Vt inter = 2mV V [V] SB V [V] SB =V = (opt) = (adaptive) Yield (%) V 6 SB = V V = V (opt) SB SB 5 = (adaptive) σ Vtinter log(p standby ) Fig. 9: Effectiveness of self-adaptive source-bias: Distribution of Source-Bias in ASB Distribution of standby power with zero, (opt) and (adaptive) (memory) failure probability window, which helps improve yield under variation []. Statistical simulations in predictive 7nm technology [5] were performed to evaluate the effectiveness of the proposed technique. Fig. 9 shows the distribution of the source-bias voltage and the leakage considering both inter-die and intra-die variations. Inset of Fig. 9 shows that the variation in optimum source bias for different dies shifted to the same inter-die corner is negligible []. It is expected that, self-adaptive scheme will degrade the leakage yield compared to (opt) as for low-vt dies self-adaptive scheme uses a lower compared to (opt). However, simulation using predictive 7nm devices shows that, the difference between the leakage distribution due to selfadaptive scheme and (opt) is minimal []. Hence, the degradation in leakage yield due to the proposed self-adaptive scheme from the (opt) is negligible []. Compared to the zero source bias scheme, it achieves 7-25% improvement in leakage yield. Simultaneously, with self-adaptive source-bias number chips failing in hold mode reduced by 7-85% compared to with (opt). Compared to the zero source bias scheme, loss in hold yield in the proposed method is only -5%. Hence, the proposed self-adaptive source-bias scheme is suitable for low-power and robust design. V. CONCLUSION Technology scaling significant increases the leakage power and degrades parametric yield of. In this paper, we explored the possibilities of designing low-power and process variation tolerant in sub-9nm nodes. We proposed a selfrepairing which uses body bias to simultaneously reduce parametric failures and leakage spread in memory array. Next, we presented a self-adaptive source-biasing scheme to reduce standby power dissipation in while keeping hold failures under control. The significant yield improvement achieved using the proposed techniques, illustrates the need for self-repairing and Fig. Effectiveness of self-adaptive source-bias: yield with zero, (opt) and (adaptive) for different standard deviation of Vt inter ; hold yield with zero, (opt) and (adaptive) for different standard deviation of Vt inter self-adaptive systems for designing low-power and process variation tolerant memories in sub-9nm technology nodes. Acknowledgement: This research was partly supported by Gigascale System Research Center and Semiconductor Research Corp (#78.). VI. REFERENCE: [] S. Borkar, et. al, Design and reliability challenges in nanometer technologies, DAC, 24. [2] A. Bhavnagarwala, et. al., The impact of intrinsic device fluctuations on CMOS cell stability, IEEE JSSC, April 2. [3] S. Mukhopadhyay, et. al, Modeling of Failure and Statistical Design of Array for Yield Enhancement in Nano- Scaled CMOS, IEEE TCAD, Dec. 25. [4] S. Mukhopadhyay, et. al, Reliable and self-repairing sram in nano-scale technologies using leakage and delay monitoring, International Test Conference, pp , Nov, 25 [5] BPTM 7nm: Berkley Predictive Technology Model, [6] A. Papoulis,, Random Variables and Stochastic Process, McGraw-Hill, NY 99 [7] S. Mukhopadhyay, et. al., Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile, IEEE TCAD, March 25. [8] K. Roy et. al, current mechanisms and leakage reduction techniques in Deep-submicron CMOS Circuits, Proc. IEEE, 23. [9] H. Qin et. al, leakage suppression by minimizing standby supply voltage, ISQED, 24. [] S. Ghosh et. al, Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled, DAC, Authorized licensed use limited to: Intel Corporation via the Intel Library. Downloaded on April 3,2 at 22:53:6 EDT from IEEE Xplore. Restrictions apply.