Reducing Transistor Variability For High Performance Low Power Chips

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Alison Arnold
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1 Reducing Transistor Variability For High Performance Low Power Chips HOT Chips 24 Dr Robert Rogenmoser Senior Vice President Product Development & Engineering 1 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

2 Overview Transistor Variability Limits Chips Impact on Mobile System on Chip (SOC) Limited Low Power Design Techniques Where does Variability come from? New Transistor Alternatives to Reduce Variability Deeply Depleted Channel (DDC) technology Silicon Impact Outlook Taking advantage of Deeply Depleted Channel (DDC) in Mobile SOC 2 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

3 What is needed in Mobile System on Chip? MC (LP DD R) Fla sh CPU (1.5GHz) L2 (1MB) Crypto, Security GPU (500MHz) HD Video, H264, MPEG BT WiFi GPS 3G LTE RF PMU High Frequency Medium Frequency Lower Frequency Memory Multiple blocks with different performance requirements Integrated on the same die Different power modes would like to run at different supplies Multiple V T transistors used to control leakage Single chip solution requires analog integration Need co-design of architecture, circuits and transistor technology for best solution 3 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

4 Variability Limits Design & Architecture Limited benefit using voltage scaling (DVFS) Cannot overdrive much due to reliability and power restrictions Dynamically lowering voltage limited to mV Only lowering frequency leaves large leakage power Run to hold beats DVFS despite overhead Finicky SRAM memories High SRAM V MIN leaves no room for memory voltage scaling Many circuit tricks to improve V MIN and noise margins Design teams moved to dedicated power rail for SRAM Works for CPU difficult in GPU Impacts power network integrity more fluctuations Analog performance and area challenge Analog functions not getting smaller at next process node (still) New process node too costly for required performance Transistor variability limits chips 4 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

5 [#Transistors] Transistor Variation Source of Chip Variation Global/Systematic/Manufacturing Variation Shifts all the transistors similarly on the same wafer Longer/shorter transistor lengths More (or less) implant energy and dose Will result in speed/power distribution Intel/AMD Sell different speed bins Consumer Design to maximize yield Could be fixed with body biasing Too slow Local/Random Variation Small number of dopants in transistor channel Transistor next to each other vary widely Random Dopant Fluctuation (RDF) Apparent in threshold voltage mismatch (σv T ) Impacts speed, leakage, SRAM & Analog Industry solution: Remove RDF using Undoped Channel What is the right silicon roadmap going forward? Useable Yield Too hot 5 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Transistor Alternatives FinFET or TriGate Promises high

Doped channel to enable multi V T Source: GSS, Chipworks

channel benefits Good body effect, but lack of multi V T

Deeply Depleted Channel transistor Straight forward

good body effect Easy migration of existing IP Source:

6 Transistor Alternatives FinFET or TriGate Promises high drive current Manufacturing, cost, and IP challenge Doped channel to enable multi V T Source: GSS, Chipworks Textbook FinFET Intel TriGate FDSOI Showing off undoped channel benefits Good body effect, but lack of multi V T capability Restricted supply chain Source: IMEC DDC Deeply Depleted Channel transistor Straight forward insertion into Bulk Planar CMOS Multi V T capability and good body effect Easy migration of existing IP Source: Fujitsu 6 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Deeply Depleted Channel (DDC) Transistor 1 Undoped or very lightly doped region Significantly reduced transistor random variability sv T Lower leakage Better SRAM (I READ, lower V min & V ret )

7 Deeply Depleted Channel (DDC) Transistor 1 Undoped or very lightly doped region Significantly reduced transistor random variability sv T Lower leakage Better SRAM (I READ, lower V min & V ret ) Tighter corners Smaller area analog design Higher channel mobility (increased I eff, lower DIBL) Higher speed, improved voltage scaling 2 V T setting offset region Enables multiple threshold voltages 3 Screening region Strong body coefficient Bias bodies to tighten manufacturing distribution Body biasing to compensate for temperature and aging *Example implementation Benefits similar to FinFET in planar bulk CMOS 7 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

[#Transistors] [Leakage Power] Lower Transistor Variability Reduces Leakage High leakage tail dominates power 65nm Silicon SRAM V T High leakage tail High V T tail Slows down ICs 2.

8 [#Transistors] [Leakage Power] Lower Transistor Variability Reduces Leakage High leakage tail dominates power 65nm Silicon SRAM V T High leakage tail High V T tail Slows down ICs 2.7x higher power (Model using 85mV subv T slope) Transistor variability is reflected in threshold voltage (V T ) distribution Leakage current is exponentially dependent on V T Lower V T variability (sv T ) reduces number of leaky low V T devices Power dissipation is dominated by low V T edge of distribution Smaller sv T Less leakage power for digital and memory/sram 8 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Lower Transistor Variability Improves Speed 65nm Silicon Measurement (B) (A) (C) Nominal (TT) ring oscillator speed expected to be 400ps (A) Equivalent to having many similar critical paths in a chip

9 Lower Transistor Variability Improves Speed 65nm Silicon Measurement (B) (A) (C) Nominal (TT) ring oscillator speed expected to be 400ps (A) Equivalent to having many similar critical paths in a chip V T variation will randomly affect paths within the same die limiting speed to 470ps Undoped channel reduces variability and increase mobility (B) 25% faster mean, 30% faster tail due to tighter distribution To match performance lower V DD until tails have same speed (C) Large impact on power due square dependence P=CV 2 f +IV 9 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

10 Node 2 [V] Lower Variability Improves Transistor Matching SRAM memories built using 6-T SRAM cell Smallest transistors on every chip, worst V T mismatch Higher V DD is required to avoid failures Demonstrated SRAM to V min of 0.425V In analog circuits, matching is key Large transistors used to improve relative variability in current mirrors, differential pairs, etc. Better transistor matching allows for Area savings Higher performance Lower power Undoped channel improves R OUT higher gain Node 1 [V] Rout vs. Vds (a) DDC 65nm Silicon Measurement DDC Baseline 10 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Better Chips with Body Biasing Useable Yield Too slow Too hot FBB RBB Body Bias to fix systematic variation Speed-up (forward bias - FBB) slow parts Cool down (reverse bias - RBB) hot parts Increase

11 Better Chips with Body Biasing Useable Yield Too slow Too hot FBB RBB Body Bias to fix systematic variation Speed-up (forward bias - FBB) slow parts Cool down (reverse bias - RBB) hot parts Increase manufacturing yield Body bias enables multiple modes of operation Active minimize power at every performance Standby leakage reduction, testing, power gating TCAD prediction DDC provides 2-4x larger body factor 11 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

12 Power [μw] Baseline speed Half the Power at Matched Performance nm Silicon Measurement FF % power TT TT FF 200 SS 50% power SS Baseline Baseline norm. f DDC DDC w/ BB norm. f Frequency [MHz] Inverter ring-oscillators (RO) fabricated at process corners 1.2V V DD and 0.9V V DD For each corner, DDC RO is faster and lower power Using strong body coefficient to pull in corners Half the power (50% less power) while matching speed 12 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Tighter Manufacturing Corners w/ DDC Better process control leads to tighter corners Manufacturing flow further reduces layout effects 1 sigma tighter wafer to wafer and within wafer variation for

13 Tighter Manufacturing Corners w/ DDC Better process control leads to tighter corners Manufacturing flow further reduces layout effects 1 sigma tighter wafer to wafer and within wafer variation for DDC Less overdesign as max paths and min (hold) paths are closer Faster design closure earlier tapeout shorter TTM 65nm data POR 3s 2s V DD =1.2V 1s V DD =0.9V 65nm measured 13 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

14 Power (W) Voltage Scaling to 0.6V V DD 5.00E E-04 65nm Silicon Measurement Baseline TT FF 3.00E E E E+00-83% DDC Frequency (MHz) SS Achieve half the speed at 1/6 the V DD Use body bias to compensate for temperature and aging Critical for low V DD operation Enable workable design window avoid overdesign 14 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

15 Power (W) This is HotChips Go Faster! 5.00E E E E E-04 SS 65nm Silicon Measurement Baseline 0.00E+00 Frequency (MHz) Turbo Mode: DDC achieves over 50% 1.2V V DD All corners for DDC run at 580MHz vs 370MHz for baseline TT FF +56% DVFS Baseline DDC V DD 1.2V 0.6V 0.9V 1.05V 1.2V Speed Power DDC 15 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

16 28nm and Beyond (silicon calibrated SPICE simulations) Same performance at 0.75V V DD as baseline at 0.9V V DD 30% lower power Alternatively 25% faster at same voltage Even better when using body bias to pull in corners 16 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Applying DDC to Lower Variability in Mobile SOC M C (L PD DR ) Fla sh CPU (1.

Single thread performance critical Push frequency by temporarily raising voltage in turbo mode DVFS with body biasing becomes DVBFS GPU: High number

pixels/watt Lower frequency blocks In addition to high V T transistors also run at lower voltage and optimal body bias Whole chip: Use body bias to

17 Applying DDC to Lower Variability in Mobile SOC M C (L PD DR ) Fla sh CPU (1.5GHz) L2 (1MB) Crypto, Security GPU (500MHz) HD Video, H264, MPEG BT WiFi GPS 3G LTE RF PMU High Frequency Medium Frequency Low Frequency Memory CPU: Single thread performance critical Push frequency by temporarily raising voltage in turbo mode DVFS with body biasing becomes DVBFS GPU: High number of cores using small transistors Less overdesign due to lower delay variability Increase parallelism, lower voltage, body bias dynamically for more pixels/watt Lower frequency blocks In addition to high V T transistors also run at lower voltage and optimal body bias Whole chip: Use body bias to adjust for manufacturing variation Take advantage of improved memory and analog performance Lowering variability while compatible with existing bulk planar silicon IP 17 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

18 Conclusions Power reduction through migration no longer possible No next process node variability limits chips Semiconductor industry is looking for new transistor technology DDC provides performance kicker from 90nm to 20nm Straight forward integration into existing nodes Less variability, tighter corners, simple manufacturing steps Compatible with existing bulk planar CMOS silicon IP DDC brings back low power tools Large range DVFS Body biasing Low voltage operation Taking advantage of reduced variability DDC in design and architecture will lead to next level in mobile SOC 18 HotChips 2012 Copyright 2011 SuVolta, Inc. All rights reserved.

Low Transistor Variability The Key to Energy Efficient ICs

Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.