ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners.

Transcription

1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and Area Today Coping with Variation (from last time) Layout Transistors Gates Design rules Standard cells 2 Variation Margin for expected variation Must assume V th can be any value in range Speed assume V th slowest value Probability Distribution V TH I on,min =I on (V th,max ) I d,sat (V gs -V th ) 2 Variation See a range of parameters L: L min L max V th : V th,min V th,max Validate design at extremes Work for both V th,min and V th,max? Design for worst-case scenario 3 4 Also margin for Temperature Voltage Aging: end-of-life Margining 5 Process Corners Many effects independent Many parameters With N parameters, Look only at extreme ends (low, high) How many cases? Try to identify the {worst,best} set of parameters Slow corner of design space, fast corner Use corners to bracket behavior 6 1

2 Simple Corner Example Vthp 350mV 150mV 150mV Vthn 350mV What happens at various corners? 7 Process Corners Many effects independent Many parameters Try to identify the {worst,best} set of parameters E.g. Lump together things that make slow Vthn, Vthp, temperature, Voltage Try to reduce number of unique corners Slow corner of design space Use corners to bracket behavior 8 Range of Behavior Speed Binning Still get range of performances Any way to exploit the fact some are faster? Probability Distribution Delay 9 Probability Distribution Sell Premium Delay Sell nominal Sell cheap Discard 10 Transistor Layout Side view Perspective view 12 2

3 Layout NMOS Geometry Sizing & positioning of transistors Designer controls W,L t ox fixed for process Sometimes thick/ thin oxide flavors L W Top view Perspective view W S L G Top view NMOS Geometry D Color scheme Red: gate Green: source and drain areas (n type diffusion) 15 t ox Transistors built by depositing materials Constant rate of deposition (nm/min) Time controls t ox Oxides across entire chip deposited at same time Same time interval thickness is (roughly) constant Process engineer sets value to: Assure yield What does t ox control? Field strength V th, current Achieve Performance, minimize leakage 16 NMOS vs PMOS Mostly talked about NMOS so far PMOS: opposite in some sense NMOS built on p substrate, PMOS built on n substrate Name refers to bias/carriers when channel is inverted W S L G n well PMOS Geometry D Color scheme Red: gate Orange: source and drain areas (p type) Green: n well NMOS built on p wafer Must add n material to build PMOS Rabaey text, Fig

4 Fourth terminal Needed to set voltage around device PMOS: V b = V dd NMOS: V b = GND At right: PMOS (orange) with body contact (dark green) Body Contact Rotate All but PMOS Transistor 90 degrees 19 Interconnect Interconnect How to connect transistors Different layers of metal Intermediate layers Contact - metal to transistor Via - metal to metal How to connect transistors Different layers of metal Intermediate layers Contact - metal to transistor Via - metal to metal Interconnect Cross Section Masks Define areas want to see in layer Think of stencil for material deposition Use photoresist (PR) to form the stencil Expose PR through mask PR dissolves in exposed area Material is deposited Only sticks in area w/ dissolved PR ITRS

5 Masking Process Mask Silicon wafer Masking Process Mask Silicon wafer photoresist Goal: draw a shape on the substrate Simplest example: draw a rectangle First: deposit photoresist Masking Process Masking Process Remove mask and develop PR Exposed area dissolves This is positive photoresist Expose through mask UV light Masking Process Logic Gates Deposit metal through PR window Then dissolve remaining PR Why not just use mask? Masks are expensive Shine light through mask to etch PR Can reuse mask How to build complete inverter? Connect NMOS, PMOS using metal

6 Start with PMOS, NMOS transistors Space for interconnect Add body contacts Connect gates of transistors Add contacts to source, drain, gate, body Connect using metal (blue)

7 Design Rules Why not adjacent transistors? Plenty of empty space If area is money, pack in as much as possible Recall: processing imprecise Margin of error for process variation Design Rules Contract between process engineer & designer Minimum width/spacing Can be (often are) process specific Lambda rules: scalable design rules In terms of λ = 0.5 L min (L drawn ) Can migrate designs from similar process Limited scope: 45nm process!= 1µm λ 6λ 2λ 3λ 6λ Design Rules: Some Examples λ λ 2λ 1.5λ Legend n doping gate p doping contact metal 1 via metal 2 Layout Revisited How to decode circuit from layout? 40 Layout to Circuit 1. Identify transistors Layout to Circuit 2. Add wires Penn ESE370 Fall DeHon Townley & DeHon

8 Layout to Circuit Layout to Circuit 2. Add wires 2. Add wires Penn ESE370 Fall Townley (DeHon) & 43 Penn ESE370 Fall Townley (DeHon) & 44 Layout to Circuit Layout #2 (practice) 2. Add wires Penn ESE370 Fall Townley (DeHon) & Layout #2 (practice) How many transistors? PMOS? NMOS? How connected? PMOS, NMOS? Inputs connected? Outputs? What is it? 47 Standard Cells Lay out gates so that heights match Rows of adjacent cells Standardized sizes Motivation: automated place and route EDA tools convert HDL to layout 48 8

9 Standard Cell Area Admin inv nand3 Cell area All cells uniform height Width of channel determined by routing Identify the full custom and standard cell regions on 386DX die HW4 due Thursday Lecture on Friday Review on Sunday at 6pm Exam on Monday No class at noon that day Big Idea Layouts are physical realization of circuit Geometry tradeoff Can decrease spacing at the cost of yield Design rules Can go from circuit to layout or layout to circuit by inspection 51 9