Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

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1 EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback is important! Final covers all material covered in class. Precise overview to be posted on web-site. Review session schedule TBD. EE141 2

2 Project 2 Summary Variety of topologies and circuit styles Most projects focused on mix of static logic families Some very impressive presentations Refer to examples on web-site Grades Mean: 79.3 Median: 78.9 Sigma: 19 Max: 110 (3.868, static) (0.944, dynamic; 1.316, static) EE141 3 Sizing Optimization Stage V: LE=1, B=1 Stage Y: LE=2, B=1 Stage Z: LE=1 B=1 0.96u/0.48u A 0.48u 0.48u 2.4u/1.2u Pin0 Stage W: LE=1, B=4 2.88u/720n 960n 960n 3.84u/1.92u 16X Pin1 Pin2 Pin3 Pin4 Pin5 Pin6 Pin7 1.2u 0.96n Gin0 Gin1 Gin2 Gin3 Gin4 0.96n Gin5 Gin6 0.96n Gin7 16X Area Concern Stage X : LE=4/3, B=1 Manchester Sizing Size: LE = = Branching : 4 v = x = / / 5 8 FO = 16 PE = 16 4 = 2.8 w = y = z = 5.70 EE141 4

3 Layout Techniques INPUT BUFFER INPUT BUFFER Size : µm 2 (33.00µm x 38.34µm) FA0 FA1 FA2 FA3 OUTPUT BUFFER OUTPUT BUFFER FA7 FA6 FA5 FA4 INPUT BUFFER CLOCK CHAIN OUTPUT BUFFER OUTPUT BUFFER INPUT BUFFER Critical Path drawn in arrow Aspect Ratio = Routing Metal 1 Horizontal Line VDD, GND Metal 2: Vertical Line Metal 3: Clock Signals EE141 5 Memory

4 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM EE141 7 Read-Only Memory Cells 1 0 GND Diode ROM MOS ROM 1 MOS ROM 2 EE141 8

5 MOS NOR ROM Pull-up devices [0] [1] GND [2] GND [3] [0] [1] [2] [3] EE141 9 MOS NOR ROM Layout Cell (9.5λ x 7λ) Programming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion EE141 10

6 MOS NOR ROM Layout Cell (11λ x 7λ) Programming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion EE MOS NAND ROM Pull-up devices [0] [1] [2] [3] [0] [1] [2] [3] All word lines high by default with exception of selected row EE141 12

7 MOS NAND ROM Layout Cell (8λ x 7λ) Programming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion EE NAND ROM Layout Cell (5λ x 6λ) Programming using Implants Only Polysilicon Threshold-altering implant Metal1 on Diffusion EE141 14

8 Precharged MOS NOR ROM f pre Precharge devices [0] [1] GND [2] GND [3] [0] [1] [2] [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. EE Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM EE141 16

9 Non-Volatile Memories The Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + p Substrate t ox n +_ S Device cross-section Schematic symbol EE Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V - 5 V 0 V V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T. EE141 18

10 FLOTOX EEPROM Floating gate Source Gate Drain I nm n 1 Substrate p n 1 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic EE EEPROM Cell Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell EE141 20

11 Cross Sections of NVM Cells Flash Courtesy Intel EPROM EE Read-Write Memories (RAM) Static (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Dynamic (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single ended EE141 22

12 6-Transistor CMOS SRAM Cell M 2 M 4 Q M Q M 5 6 M 1 M 3 EE CMOS SRAM Analysis (Read) M 4 Q = 0 M 5 Q = 1 M 6 M 1 C bit C bit EE141 24

13 V o l t a g e r i s e [ V ] CMOS SRAM Analysis (Read) Voltage Rise (V) Cell Ratio (CR) EE CMOS SRAM Analysis (Write) M 4 Q = 0 M 6 M 5 Q = 1 M 1 = 1 = 0 EE141 26

14 CMOS SRAM Analysis (Write) EE T-SRAM Layout M2 M4 M 2 M 4 Q M Q M 5 6 Q Q M1 M3 M 1 M 3 GND M5 M6 EE141 28

15 Resistive Load SRAM Cell R L R L M 3 Q Q M 4 M 1 M 2 Static power dissipation -- Want R L large Bit lines precharged to to address t p problem EE Transistor DRAM Cell 1 2 W R W M 3 R M 1 X M 2 X - V T C S V T DV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V W -V Tn EE141 30

16 3T DRAM Layout GND W R R M3 M 3 M2 M 1 X M 2 C S W M1 EE Transistor DRAM Cell Write 1 Read 1 M 1 C S X GND 2 V T /2 V sensing DD /2 C Write: C S is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V V PRE = V BIT V PRE C S + C Voltage swing is small; typically around 250 mv. EE141 32

17 1T DRAM Cell Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses Polysilicon-Diffusion Capacitance Expensive in Area EE Micrograph of 1T DRAM EE141 34

18 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Transfer gate Isolation Storage electrode Trench Cell Stacked-capacitor Cell EE Perspectives

19 EE141 Summary Digital circuit designers will have jobs in Major challenges Cost Power consumption Robustness Complexity Some new circuit solutions and design methodologies are coming EE Technology Scaling Technology Node (nm) Integration Capacity (BT) Delay = CV/I scaling 0.7 ~0.7 >0.7 Delay scaling will slow down Energy/Logic Op scaling Bulk Planar CMOS Alternate, 3G etc Variability ILD (K) RC Delay Metal Layers >0.35 >0.5 >0.5 Energy scaling will slow down High Probability Low Probability Low Probability High Probability Medium High Very High ~3 <3 Reduce slowly towards to 1 layer per generation 1 Courtesy: R. Krishnamurthy (Intel) Internal University FCRP(MARCO) EE141 38

20 Research Roadmap EE Device Evolution EE141 40

21 25nm FinFET 25 nm MOS transistor (Folded Channel) EE Cost Mask cost in 90nm technology is over $1M Bugs are very expensive Design effort increases in DSM Cost of new tools Non-recurring costs dominate the price effectiveness of low-volume ASICs Need to have a product that can fit multiple applications, customers (flexibility) EE141 42

22 Power has become a Problem Power (Watts) KW 5KW 1.5KW 500W Pentium Pro Pentium Year Source: S. Borkar (Intel) Power delivery and dissipation will be prohibitive EE The Productivity Gap 10,000,000 10,000 Complexity Logic Transistor per Chip (M) 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. 58%/Yr. compounded Complexity growth rate x x x x x x x Today x 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity EE141 44

23 Some FPGA Examples Xilinx Spartan-3 Xilinx IQ EE The Architectural Tradeoff Game Flexibility Prog Mem µp Satellite Processor Prog Mem MAC Unit µp Addr Gen Prog Mem µp General Purpose µp Dedicated Logic Satellite Satellite Processor Processor Hardware Reconfigurable Processor Software Programmable DSP Direct Mapped Hardware Inefficiency EE141 46

24 The Challenge of the Next Decade The Deep Sub-Micron (DSM) Effect DSM 1/DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock Distribution Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. Everything looks a little different and there s a lot of them! EE EE141 48