EE 330 Lecture 12. Devices in Semiconductor Processes. Diodes

Transcription

1 EE 330 Lecture 12 Devices in Semiconductor Processes Diodes

2 Guest Lecture: Joshua Abbott Non Volatile Product Engineer Micron Technology NAND Memory: Operation, Testing and Challenges

3 Intro to Flash Memory Design Josh Abbott (ISU BSEE 14) NVE Product Engineering Micron Technology EE330 Iowa State University 9/21/2015 September 23, 2016

4 Agenda o Types of Memory o Flash Memory Cells o Program, Erase, Read Operations o 2D to 3D NAND o Basic Device Physics o Technical Issues with 3D NAND o o September 23, 2016

5 Micron s Core Memory Technologies Types of Semiconductor Memory Volatile Non-Volatile DRAM NAND Flash NOR Flash Volatile loses data when power is removed (within milliseconds) Non-volatile retains data when power is removed (for years) September 23, 2016

6 Leading-Edge Technology Status DRAM 1Xnm DRAM NAND 3D NAND Package Technology Hybrid Memory Cube New Memory Technology 3D X-point Images are not to scale September 23, 2016

7 Flash Memory Cell Single FET with dual gate Electrically isolated floating gate is the storage element Electrons added to or removed from the floating gate shift the V t of the cell to store a 1 or a 0 Two types: NAND and NOR NAND Better array efficiency, lower cost per die for mass-storage NOR Faster read/write speeds for code storage and execution

8 NAND vs NOR Physical Comparison NAND Serial layout Source Drain NOR Parallel layout Drain Gate Source Drain

9 Basic NAND Flash Operation The operation of the NAND Flash cell depends on two basic electrical concepts: Capacitive division Fowler-Nordheim tunneling

10 Capacitive Division If you have capacitors in series, a voltage applied to one node will be distributed across the intermediate nodes V 2 = V 1 * C 1 / (C 1 +C 2 )

11 Fowler-Nordheim Tunneling By setting up a large potential difference across an insulator, you can decrease the effective width of the energy barrier, and increase the probability that an electron will tunnel through the insulator. - + e e e e e e e e e Semiconductor Insulator Semiconductor

12 Store a 0 to a cell NAND Flash Operation Program Inject electrons onto floating gate through F-N tunneling 20V Floating Control gate Floating gate 0V N+ N+ p-well N-well p-sub Program 0 0V 0V

13 Store a 1 to a cell NAND Flash Operation Erase Remove electrons from the floating gate through F-N tunneling 0V Floating Control gate e- e- e- e- e- e- Floating N+ N+ p-well N-well p-sub Erase 0V 20V

14 NAND Flash Operation Read By storing electrons on the floating gate, we can change the effective threshold voltage (V T ) FET conducts current if V GS > V T To read the cell, apply a voltage (VRead) to the rowline (V T < V Read ) => Current, logic 1 Bitline (V T > V Read ) => No current, logic 0 Rowline V Read Floating Gate

15 NAND Read Operation 1 0 SGD WL WL WL WL 5V 5V 5V 0V 5V Vc c 3V -3V 1V -1V 1. Precharge bitline and unselected wordlines 2. Drive selected wordline and connect string to bitline 3. Sense current WL 5V 2V WL 5V -2 SGS 5V

16 Vt Distributions Single-Level Cell (SLC) Number of Bits 1 0 Multi-Level Cell (MLC) Number of Bits LP Can be extended further to 3 bits per cell (TLC) with 8 distinct states

17 The NAND String Notice that it has n doping on the source and drain that is repeated across a horizontal plane. September 23, 2016 Micron Confidential

18 Channel \ Pillar Moving to 3D NAND Change to the Channel Elimination of Pwell/Atub Loss of LDD (Lightly Doped Drain) Pillar Vertical Stacking of Cell s Device Physics Change 1. With n- LDD (2D) n p n Low Vt-ldd 2. No LDD, P-type channel p High Vt-ldd 3. No LDD, N-type thin channel Si Substrate (Pwell/Atub) Si Substrate n Low Vt-ldd September 23, 2016

19 Channel \ Pillar How does the Channel Conduct with No LDD? With All E fields the channel can be formed in the pillar and thus conduct effectively. Fringe Fields allow for E Field to activate area between cells. Si Substrate 2 1 September 23, 2016 Micron Confidential

20 Channel \ Pillar Challenges with the Channel Erase Verify Example Fringe Fields are to weak to create channel in the space between Cells. AKA, my Space Vt is too high to activate with 1V. The result is a nonconductive channel even though my Vt s of my cell s are lower than the Gate Voltage. Assume the cell is erased <0V Vt Si Substrate 2 2 September 23, 2016 Micron Confidential

21 What goes into designing a Flash Core memory array Lots of other circuitry: September 23, 2016 memory chip? Sense amplifiers and digital registers to read and store the contents of the memory array Command and address decoders to select which location to read/write, and which operation to perform Bandgap reference to generate a voltage reference that is stable across temperature and supply voltage Charge pumps to generate voltages above or below the supply voltages for the chip Voltage regulators to regulate the precise voltages required to read/write the array Thermometer to adjust voltages as needed vs. temperature DACs and ADCs for converting internal signals between analog and digital domains Current sources/mirrors to be used for providing reference currents to key circuits throughout the chip Microcontroller and digital control logic to control the read/write algorithms for the array I/O drivers for communicating with the outside world High speed datapath for sending data back and forth between the Chip I/Os and memory array

22 Questions? September 23, Micron Technology, Inc. 24

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24 Review from Last Lecture

25 Review from Last Lecture

26 Review from Last Lecture Silicon Dopants in Semiconductor Processes B (Boron) widely used a dopant for creating p-type regions P (Phosphorus) widely used a dopant for creating n-type regions (bulk doping, diffuses fast) As (Arsenic) widely used a dopant for creating n-type regions (Active region doping, diffuses slower)

27 Diodes (pn junctions) Depletion region created that is ionized but void of carriers

28 pn Junctions Physical Boundary Separating n-type and p-type regions If doping levels identical, depletion region extends equally into n-type and p-type regions

29 pn Junctions Physical Boundary Separating n-type and p-type regions Extends farther into p-type region if p-doping lower than n-doping

30 pn Junctions Physical Boundary Separating n-type and p-type regions Extends farther into n-type region if n-doping lower than p-doping

31 pn Junctions I D V D Positive voltages across the p to n junction are referred to forward bias Negative voltages across the p to n junction are referred to reverse bias As forward bias increases, depletion region thins and current starts to flow Current grows very rapidly as forward bias increases Current is very small under revere bias

32 pn Junctions Anode I D Anode V D Cathode Cathode Circuit Symbol

33 pn Junctions As forward bias increases, depletion region thins and current starts to flow Current grows very rapidly as forward bias increases V D I D Anode Cathode D Simple Diode Model: V =0 I >0 I =0 V <0 D I D D D V D Simple model often referred to as the Ideal diode model

34 pn Junctions I D Simple Diode Model: I D V D V D pn junction serves as a rectifier passing current in one direction and blocking it In the other direction

35 Rectifier Application: D 1 V OUT Simple Diode Model: I D V IN 1K V D V IN =V M sinωt V M V IN t V OUT V M t

36 I-V characteristics of pn junction Improved Diode Model: (signal or rectifier diode) I d I S in the 10fA to 100fA range V d kt V= t q Diode Equation I D Vd V t I e 1 S What is V t at room temp? V t is about 26mV at room temp k= (24) JK -1 q = (40) C k/q= VK -1 Diode equation due to William Schockley, inventor of BJT In 1919, William Henry Eccles coined the term diode In 1940, Russell Ohl stumbled upon the p-n junction diode

37 I-V characteristics of pn junction Improved Diode Model: (signal or rectifier diode) Diode Characteristics 0.01 V d I d Id (amps) Vd (volts) Diode Equation Under reverse bias (V d <0), Under forward bias (V d >0), I D Vd V t I e 1 S Simplification of Diode Equation: I D I S V V D Se I I d t I S in the 10fA to 100fA range kt V= t q k= (24) JK -1 q = (40) C k/q= VK -1 V t is about 26mV at room temp Simplification essentially identical model except for V d very close to 0 Diode Equation or forward bias simplification is unwieldy to work with analytically

38 I-V characteristics of pn junction Improved Diode Model: Diode Equation Simplification of Diode Equation: I D Under reverse bias, Under forward bias, (signal or rectifier diode) Vd V t I e 1 S I D I S I I D S e V V d t I S often in the 10fA to 100fA range I S proportional to junction area V t is about 26mV at room temp How much error is introduced using the simplification for V d > 0.5V? Vd Vt I S e 1 ISe Vd I Vt e 1 S Vd V t e How much error is introduced using the simplification for V d < - 0.5V? e Simplification almost never introduces any significant error 9 9

39 Will you impress your colleagues or your boss if you use the more exact diode equation when V d < -0.5V or V d > +0.5V? Will your colleagues or your boss be unimpressed if you use the more exact diode equation when V d < -0.5V or V d > +0.5V?

40 pn Junctions I Anode V I V Cathode Diode Equation: (good enough for most applications) I JSAe 0 V nv T V 0 V 0 Note: I S =J s A J S = Sat Current Density (in the 1aA/u 2 to 1fA/u 2 range) A= Junction Cross Section Area V T =kt/q (k/q=1.381x10-23 V C/ K/1.6x10-19 C=8.62x10-5 V/ K) n is approximately 1

41 pn Junctions Diode Equation: I J 0 S Ae V nv T V 0 V 0 I Anode J S is strongly temperature dependent With n=1, for V>0, V Cathode -V V G0 D I(T) J T m e V Ae V t t SX Typical values for key parameters: J SX =0.5A/μ 2, V G0 =1.17V, m=2.3

42 Example: pn Junctions -V V G0 I(T) J m Vt T e Ae SX V D t V I What percent change in I S will occur for a 1 C change in temperature at room temperature? -V V -VG0 -V -V -V G0 D G0 G0 G0 V (T ) V Vt T1 V (T ) V (T ) m m m m Vt T1 t 2 t t 2 t 2 J T e Ae - J T e Ae T e - T e SX T SX T T IS I S -VG0 -V -V G0 G0 m Vt T1 V (T ) m Vt T1 t 2 J T e Ae T e SX T T x x x10 I S % 21% I S

43 End of Lecture 12