ECEG 350 Electronics I Fall 2017

Transcription

1 EEG 350 Electronics Fall 07 Final Exam General nformation Rough breakdown of topic coverage: 0-0% JT fundamentals and regions of operation 0-40% MOSFET fundamentals biasing and small-signal modeling 0-5% iodes (pn-junction diodes zener diodes 0-5% asic difference amplifiers instrumentation amplifiers and MRR 0-5% imperfections in op amps (input bias current input offset voltage See the ourse Outcomes section of the ourse escription page at the EEG 350 web site for a more detailed list of specific competencies that are likely to be assessed. The final exam will take place 7:30-0:30 pm on Wednesday ecember 3 in Academic West 6. The exam will be designed to be approximately.5 hours in length but you will have the full three hours to complete it. Please review the Exam Policies section of the Exams page at the course web site and especially note the following:. You will be allowed to use a non-wireless enabled calculator such as a T-99.. You will be allowed to use up to four 8.5 -inch two-sided handwritten help sheets. No photocopied material or copied and pasted text or images are allowed. f there is a table or image from the textbook or some other source that you feel would be helpful during the exam please notify me. 3. All help sheets will be collected at the end of the exam but will be returned to you later or at the beginning of the next semester if you wish to have them back. The final exam score cannot be dropped. Solutions to the final exam will not be posted but you may review your final exam and discuss it with me after it has been graded. Your final exam score will be posted to the course Moodle site. Review Topics for Final Exam The following is a list of topics that could appear in one form or another on the exam. Not all of these topics will be covered and it is possible that an exam problem could cover a detail not specifically listed here. However this list has been made as comprehensive as possible. You should be familiar with the topics on the previous review sheets in addition to those listed below. Although significant effort has been made to ensure that there are no errors in this review sheet some might nevertheless appear. The textbook is the final authority in all factual matters unless errors have been specifically identified there either by the authors (in the form of published errata or by me. You are ultimately responsible for obtaining accurate and authoritative information when preparing for your exam. of 7

2 iasing MOSFET circuits - concept of biasing and why it is necessary - parameters kn kp and Vt decrease with increasing temperature (strong dependence; Vt change is approximately mv/ ( mv/k; parameter values usually exhibit wide variability from device to device due to loose manufacturing tolerances - change in Vt usually dominates at low overvoltages (VOV = VGS Vt and change in kn (or kp usually dominates at high overvoltages - variation in kn and kp is largely dominated by temperature dependence of µn and µp. - design for quiescent output voltage drain current and/or voltage drop across source resistor - usually bias MOSFET for operation in the saturation region if it s used as amplifier - must pay attention to swing range of v (total voltage to avoid cutoff and triode regions o saturation region defined by vs vgs v vs vg vs v vg o in cutoff region i = 0; this is also true at the boundary between the cutoff and saturation regions o saturation-triode boundary defined by (for NMOS devices: V = VG V sat. triode t or (equivalently VS sat. triode = VGS - parameter-independent biasing (source degeneration or 4-resistor biasing V RA R R VG + VGS V = 0.5kn VGS and VGS = VG simultaneously o square-law relationship sometimes leads to solution of quadratic equations o must determine which solution to quadratic equation is the physical solution VG o exact solution: = + + kn ( VG kn kn o design rules of thumb: R = = V and VG = + Vt + kn 3 but V value could be explicitly specified which could mean R V ; 3 other choices for could be used to meet other constraints o establishment of gate bias voltage simplified because G = 0: R VG = V where R is the lower resistor (b/w gate and ground R + R o must satisfy ( A of 7

3 - biasing using a drain-to-gate feedback resistor including variant with gate-to-ground resistor is an alternative approach (covered earlier; its primary advantages are that it one fewer resistor and (sometimes important the source terminal can be connected to ground. - gate biasing resistors should be in the MΩ range or several 00s of kω to avoid excessive current draw from power supply and to avoid loading down signal source applied to amplifier s input blocking capacitors - act as open circuits at - act as short circuits (or very low reactances at signal frequencies - isolate biasing from effects of signal source and/or load - impedance and reactance Z = = and X = = ( Z = jx j ω j π f ω π f A bypass capacitors - act as open circuits at - act as short circuits (or very low reactances at signal frequencies - ensure bypassed nodes are close to ground potential at signal frequencies - commonly connected across power supply nodes and ground and across source (FETs or emitter (JTs degeneration resistors General small-signal modeling of MOSFET circuits - definition of incremental signal or small signal (fluctuations are a small fraction of total voltage or current - separation of bias considerations (quiescent levels; output voltage swing range from small-signal considerations (gain input and output resistance - for small-signal (A analysis using superposition o replace voltage sources with shorts (because voltage across a voltage source can t change; alternative reason: a 0-V A source is a signal short o replace current sources with opens (because current through a current source can t change; alternative reason: a 0-A A source is a signal open o replace large capacitors with shorts (if capacitive reactance is insignificant at operating frequency o replace small capacitors/capacitances with opens (if capacitive reactance is enormous at operating frequency o replace large inductors with opens (if inductive reactance is very large at operating frequency o replace small inductors/inductances with shorts (if inductive reactance is insignificant at operating frequency - voltage sources are typically bypassed at A (i.e. at signal frequencies using large capacitors to ensure that the source acts as an A ground. - small-signal model of MOSFET comprised of gmvgs ro and gap b/w gate and source (the hybrid pi model is only valid when device operates in the saturation region - small-signal model of drain-to-source path represented by rs is only valid when MOSFET operates in the low-vs triode (resistive region - small-signal model of MOSFET in cut-off region consists of open circuits between all terminals (gate source drain - derivation of small-signal voltage gain vo/vin or (vo/vsig - simplifications can sometimes be made in gain expressions when one term is much greater/smaller than another term 3 of 7

4 Small-signal modeling of MOSFET amplifier circuits - gate-source path modeled as an open circuit - small-signal transconductance gm (for NMOS devices; similar for PMOS i o basic definition: g m = ; can also be derived from v GS v GS = V GS ( V + v V = k ( V V + k ( V V + id = kn GS gs t n GS t n GS t kn ( VGS + kn ( VGS vgs id = kn GS t gs m gs n GS t where vgs << (VGS Vt and gm = kn(vgs Vt o equivalent formulas (for NMOS devices; similar for PMOS: g m = knvov = kn ( VGS = VGS = kn W W where kn = k n = µ nox L L ( V V v = g v and = k ( V V o derivations of these formulas - effect of source degeneration resistor ( on gain - incremental drain-source resistance ro o represents non-zero slope of i-vs characteristic in the saturation region due to channel-length modulation (sometimes referred to as the Early effect although that term technically applies only to JTs o i-v characteristic in saturation region that includes λ: knv OV S OV n OV [ + λ ( v v ] k v ( + λv i = S where vov = vgs Vt Note: The approximate form is Equation (5.3 in Sedra & Smith 7 th ed. o channel-length modulation parameter: λ = VA + VOV VA where VA = Early voltage o ro is typically 0-00 kω for MOSFETs but can be much lower for some types o ro is not equal to rs of MOSFET in low-vs triode region! VA o ro where is the quiescent drain current λ ommon-source (S and common-drain (source follower amplifiers - common refers to terminal connected either directly to ground or to ground through a few resistors capacitor and maybe inductors. Signal source and load are connected to other terminals (directly or indirectly that are not common. - S amps and source followers can be biased in multiple ways (e.g. 4-R network drain-to-gate feedback resistor current mirror; the biasing network does not determine the amplifier s nomenclature v gs + k n v gs 4 of 7

5 nternal structure of bipolar junction transistor (JT - npn: thin p-type base sandwiched between n-type emitter and collector - pnp: opposite of npn - base-emitter (E and collector-base ( junctions are regular pn junctions and act the same way (i.e. they can be forward or reverse-biased; they have turn-on voltages - JTs can be modeled as back-to-back diodes (base is the node b/w diodes in some cases NOTE: ONLY NPN JTS WLL E OVERE EXPLTLY ON THE FNAL EXAM. SOME NFORMATON ON PNP JTS S NLUE HERE TO PROVE EXPOSURE TO THER OPERATON. JT circuit symbols - pay attention to directions of arrows (arrow indicates the emitter terminal and JT type; arrow of npn is not pointing in ; arrow points in direction of emitter current ie npn E npn vs. pnp JTs - ve and ve of npn JTs have positive values in normal operation - ve and ve of pnp JTs have negative values in normal operation (use ve and ve which are positive instead - i and i flow into base and collector terminals of npn JTs and out of base and collector terminals of pnp JTs (i and i are positive for both types - i-v characteristics of npn and pnp JTs have voltages of opposite sign Qualitative understanding of operation of JT - turn-on voltage (VF of base-emitter junction (approx. 0.7 V for Si - effect of changing base current i - effect of changing collector-emitter voltage ve (normally junction is reverse biased or at least not heavily forward biased; necessary for collector current to flow and to be proportional to base current as modeled by i = βi - directions and polarities of important currents and voltages (i i ie ve ve - thin base region required to allow electrons (npn or holes (pnp to flow from emitter to collector - emitter more heavily doped than base allows base to fill with minority carriers of mostly one type (electrons for npn; holes for pnp when base current flows - base-emitter (E junction is forward biased if ve is at turn-on voltage (VF - i-v characteristic of E junction is the same as that of a pn-junction diode: v E nv T i = Se where S = saturation current of E junction n = emission coefficient (assumed to equal one in textbook and VT = thermal voltage which is given by T V T = where T = temperature in kelvins (VT = 5 mv at room temp collector-base junction is usually reverse biased or lightly forward biased so that depletion region (and associated built-in field exists 5 of 7 pnp E

6 - collector current related to base current by i = βi in the active region where β = forward current gain (values are typically but vary among JT types even among individual units of a given type within the same manufacturing batch; β varies strongly with temperature JT i-v characteristic (i vs. ve for selected values of i and regions of operation - cut-off region (ve < VF where VF = turn-on voltage of E junction; i = i = 0 - active (constant-current region (ve = VF i = βi ve > V for Si - saturation region (ve = VF ve V and i < βi but i and i are nonzero General analysis techniques for JT circuits - determination of region of operation (cutoff active or saturation o try to determine if base-emitter junction is forward biased if possible; helps to rule out (or not cut-off region o assume JT is in one region and analyze the circuit based on that assumption o check all voltages and currents and determine whether or not their values are consistent with the initial assumption. f so analysis is complete. f not use the results of the initial analysis to determine likely region of operation. Repeat analysis under new assumption and confirm. - ve (for npn JTs is always positive (negative for pnp; i.e. ve is positive - ve 0.7 V (for Si npn in the active and saturation regions - in cut-off region i = i = 0 and ve < 0.7 V (for Si npn - in active region ve 0.7 V i = βi and ve > ve sat V - in saturation region ve 0.7 V i < βi and ve = ve sat V - for more accurate analysis (rarely necessary use v E nv T T i = Se and v E i nv = β Se where S = saturation current n = emission coefficient (value of - for Si typically and VT = thermal voltage Analysis of four-resistor JT biasing circuit V V R R R V equiv. to R V R VE V + VE RE RE - for analysis purposes can represent base biasing network by a Thévenin equivalent R circuit consisting of: V = V and R = R R ; simplifies eval of R + R - the parameter β has strong temperature dependence and device variation - negative feedback via emitter degeneration resistor RE stabilizes - resistors R and R do not behave as a true voltage divider because 0 6 of 7

7 - trade-off: higher current through R and R (i.e. lower resistor values leads to more stable quiescent point but lower input resistance and higher current demand from power supply Relevant course material: HW: #0 Labs: #5 (partly Readings: Assignments from Nov. 8 through ec. 4 including lecture notes: Source egeneration iasing for iscrete MOSFET Amplifiers This exam will cover course outcomes # through #6 (i.e. it is cumulative but a proportionately larger amount of coverage will focus on course outcomes #4 applied to JTs and outcomes #5 and #6 applied to MOSFETs. The course outcomes are listed on the ourse Policies and nformation sheet distributed at the beginning of the semester and also on the ourse escription page of the course web site. 7 of 7