Device Technologies. Yau - 1

Transcription

1 Device Technologies Yau - 1

2 Objectives After studying the material in this chapter, you will be able to: 1. Identify differences between analog and digital devices and passive and active components. Explain the effects of parasitic structures in passive components. 2. Describe the PN junction, why it is important, and explain reverse and forward biasing. 3. State the characteristics of bipolar technology and the bipolar junction transistor in terms of function, biasing, structure and applications. 4. Explain the basic characteristics of CMOS technology, including the field effect transistor, biasing and the CMOS inverter. 5. Explain the difference between enhancement and depletion mode MOSFETs. 6. Explain the effects of parasitic transistors and the implications for CMOS latchup. 7. Give examples of IC products and state some applications of each. Yau - 2

3 Circuit Types Analog Circuits Digital Circuits Yau - 3

4 Components on Printed Circuit Board Photo 3.1 Yau - 4

5 Passive Component Structures IC Resistor Structures Parasitic Resistor Structures IC Capacitor Structures Parasitic Capacitance Structures Yau - 5

6 Examples of Resistor Structures in ICs Metal contact Film type resistor Metal contact n - Substrate SiO 2, dielectric material SiO 2, dielectric material n - p - Diffused resistor Figure 3.1 Yau - 6

7 Cross Section of Parasitic Resistances in a Transistor Base Emitter Collector Metal contact resistance RBC REC RCC RBB REB RCB n + p - p - Substrate n + Bulk resistance Figure 3.2 Yau - 7

8 Examples of Capacitors Structures in ICs Metal contacts Metal contact to 1st poly Substrate Oxide dielectric 2nd doped poly layer Substrate 1st doped poly layer Dielectric material (oxide) Metal contact to diffused region Substrate p - Diffused region Doped poly layer Figure 3.3 1st, n + poly plate Substrate 2nd, n + poly plate Dielectric material (oxide) Yau - 8

9 Parasitic Capacitance in Transistors E B C S G D doped poly n n p n n n oxide p - Substrate Bipolar junction transistor p - Substrate Field effect transistor Figure 3.4 Yau - 9

10 Active Component Structures The pn Junction Diode The Bipolar Junction Transistor Schottky Diode Bipolar IC Technology CMOS IC Technology Enhancement and Depletion-Mode MOSFETs Yau - 10

11 Basic Symbol and Structure of the pn Junction Diode Metal contact pn junction diode Cathode Anode Heavily doped p region Heavily doped n region p - Substrate Figure 3.5 Yau - 11

12 Open-Circuit Condition of a pn Junction Diode p-type Si Depletion region } n-type Si Metal contact Anode Cathode Potential hill Charge distribution of barrier voltage across a pn Junction. 0 Barrier voltage Figure 3.6 Yau - 12

13 Reverse-Biased PN Junction Diode p Open-circuit condition (high resistance) n 3 V Lamp Figure 3.7 Yau - 13

14 Forward-Biased PN Junction Diode p n Hole flow Electron flow 3 V Lamp Figure 3.8 Yau - 14

15 Forward and Reverse Electrical Characteristics of a Silicon Diode + I Forward bias curve V + V Breakdown voltage Leakage current Junction voltage Reverse bias curve -I Figure 3.9 Yau - 15

16 Two Types of Bipolar Transistors npn transistor Collector pnp transistor Collector Physical structure n Physical structure p Base p Base n n p Schematic symbol Emitter C Schematic symbol Emitter C B B E E Figure 3.10 Yau - 16

17 NPN Transistor Biasing Circuit h + C C 1.5 V S 1 B n p n Lamp 3 V 1.5 V S 1 B Electron flow n p n 3 V Lamp E E e - e - Nonconduction mode Conduction mode Figure 3.11 Yau - 17

18 PNP transistor biasing circuit e - C C p Lamp p Lamp S 1 B n S 1 B Hole flow n 1.5 V p 3 V 1.5 V p 3 V E h + E h + Nonconduction mode Conduction mode Figure 3.12 Yau - 18

19 Cross Section of an NPN BJT Metal contact C E B n + p n + p - substrate Figure 3.13 Yau - 19

20 Schematic Symbol and Structural Cross Section of the Schottky Diode Schottky contact Anode Cathode Normal ohmic contact n - n + Figure 3.14 Yau - 20

21 Bipolar Logic Families Bipolar Logic Family Table 3.1 Bipolar Logic Families Abbreviation Direct-Coupled Transistor Logic DCTL 1 Resistor-Transistor Logic RTL 2 Resistor-Capacitor-Transistor Logic RCTL 3 Diode-Transistor Logic DTL 4 Transistor-Transistor Logic* TTL 5 Schottky TTL Logic* STTL 6 Emitter-Coupled Logic* ECL 7 1 G. Deboo and C. Burrous, Integrated Circuits and Semiconductor Devices: Theory and Application, 2 nd edition, McGraw-Hill, New York, NY, 1977, p G. Deboo and C. Burrous, ibid. 3 G. Deboo and C. Burrous, ibid. 4 G. Deboo and C. Burrous, ibid. 5 G. Deboo and C. Burrous, ibid. 6 A. Sedra, K. Smith, Microelectronic Circuits, Oxford University Press, 1998, p A. Sedra, K. Smith, Microelectronic Circuits, Oxford University Press, 1998, p Table 3.1 Yau - 21

22 CMOS IC Technology The Field Effect Transistor MOSFETs nmosfet pmosfet Biasing the nmosfet Biasing the pmosfet CMOS Technology BiCMOS Technology Enhancement and Depletion-Mode Yau - 22

23 Two Types of MOSFETs pmosfet (p-channel) nmosfet (n-channel) Gate Gate Source Drain Source Drain p + p + n + n + n-type silicon substrate p-type silicon substrate Drain Drain Gate Substrate Gate Substrate Source Source Figure 3.15 Yau - 23

24 Biasing Circuit for an NMOS Transistor S 1 V GG = V Open gate (no charge) Gate Source Drain n + n + p-type silicon substrate Lamp (no conduction) V DD = V Figure 3.16 Yau - 24

25 NMOS Transistor in Conduction Mode S 1 V GG = V Positive charge e- Source Gate n + n + Holes p-type silicon substrate Drain I DS Lamp e- e- V DD = V Figure 3.17 Yau - 25

26 Example of Characteristics Curves of an N-channel MOSFET Linear Region Saturation Region V GS = +5V Drain Current, I DS (µa) V GS = +4V V GS = +3V 200 V GS = +2V 100 V GS = +1V Drain-Source Voltage, V DS (volts) Figure 3.18 Yau - 26

27 Biasing Circuit for a P-Channel MOSFET S 1 V GG = V Open gate (no charge) Gate Source p + p + Drain n-type silicon substrate Lamp (no conduction) V DD = -3.0 V Figure 3.19 Yau - 27

28 PMOS Transistor in Conduction Mode S 1 V GG = V Negative charge e- Source Gate Drain I DS p + p + Electrons n-type silicon substrate Lamp e- e- V DD = V Figure 3.20 Yau - 28

29 Schematic of a CMOS Inverter + V DD G S pmosfet D Input Output D G S nmosfet -V SS Figure 3.21 Yau - 29

30 Top View of CMOS Inverter n-type silicon substrate Polysilicon n-well p-well -V SS S G G D D S +V DD Metal p + p + n + n + pmosfet nmosfet Figure 3.22 Yau - 30

31 Cross-section of CMOS Inverter Interlayer Oxide pmosfet Metal nmosfet G G -V SS S D D S +V DD n + p + p + n + n + p + p-well n-type silicon substrate Field oxide Figure 3.23 Yau - 31

32 BiCMOS Chips used in the Control of a Simple Heating System CPU Setpoint Output Digital side BiCMOS DAC 0-5 V + 48 VDC AMP Analog side Drive signal Heating element Process chamber Temperature sensor Input Feedback BiCMOS ADC 0-5 V AMP mv Measured signal Figure 3.24 Yau - 32

33 Simple BiCMOS Inverter CMOS section Bipolar section Q1 Q3 INPUT Q2 OUTPUT Q4 Redrawn from H. Lin, J. Ho, R. Iyer, and K. Kwong, Complementary MOS-Bipolar Transistor Structure, IEEE Transactions Electron Devices, ED-16, 11 Nov. 1969, p Figure 3.25 Yau - 33

34 Comparison of Enhancement and Depletion Mode MOSFETs MOSFET Type Mode Standby Condition V GG Switching Requirements nmos Enhancement Off + nmos Depletion On - Physical Structure Gate Source Drain n + n + p-type silicon substrate Gate Source Drain n p-type + silicon substrate n + p-type silicon substrate pmos Enhancement Off - Gate Source Drain p + p + n-type silicon substrate pmos Depletion On + Gate Source Drain p + p + n-type silicon substrate Figure 3.26 Yau - 34

35 Latchup in CMOS Devices pmosfet nmosfet V SS S G D D G S V DD n+ p+ p+ n+ n+ p+ RW RS T1 p-well T2 n-type substrate Parasitic Junction Transistors within a CMOS Structure Figure 3.27 Yau - 35

36 Integrated Circuit Products Linear IC Products Operational Amplifier Voltage Regulator Stepper Motor Driver Digital IC Products Volatile Memory RAM DRAM SRAM MPU or CPU Digital IC Products (continued) Nonvolatile Memory ROM PROM EPROM EEPROM ASIC PLD PAL PLA MPGA FPGA Yau - 36