Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

Size: px
Start display at page:

Download "Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006"

Transcription

1 Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

2 Lecture 01: the big picture Course objective Brief tour of IC physical design Projects overview Survey of papers and industry products

3 Class objective(s): circuit (gates) masks Study various physical implementation methodologies At 65nm and beyond, discuss some of the latest research challenges and techniques physical design Surveythe main industrial physical implementation tools Conduct a research project on a recent, relevant problem [Photograph courtesy of AMD] Masks for manufacturing ICs

4 What do designers really care about? Design Objectives: Power (dynamic/static) Timing (frequency) Area (cost/yield) Yield (cost) Challenges: Manufacturing technology Leakage power Interconnect delay Variability Reliability

5 Circuit entities eventually are either transistors or interconnects NMOS transistor Metal interconnects How do you manufacture them?

6 How do ICs get manufactured? UV light oxygen Silicon dioxide photoresist Mask exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment and Exposure Exposed Photoresist Photoresist Develop RF RF Power Power RF RF Power Power RF RF Power Power Ionized CF 4 gas photoresist oxide RF RF Power Power Ionized oxygen gas oxide oxygen gate oxide Dopant gas Silane gas polysilicon Ionized CCl 4 gas oxide poly poly gate gate Scanning ion beam ox Oxide Etch S G D Ion Implantation resist resist resist Photoresist Strip S G D Oxidation (Gate oxide) S silicon nitride top nitride G Active Nitride Contact Regions Deposition Etch [Advanced Micro Devices from Quirck/Serda] D Polysilicon Deposition Contact holes S G D Polysilicon Mask and Etch Metal contacts drain G S D Metal Deposition and Etch [Check out this too

7 And the end result is:

8 A very brief tour of physical design gate-level circuit floorplanning placement Timing analysis floorplanning placement repeater insertion Parasitic extraction clock tree synthesis P/G network / routing Power analysis Signal Integrity Clock Tree Metal Wires metal fill insertion mask generation / OPC mask mask after OPC reticles

9 Class breakup Topic i main ideas and techniques (sreda) 5-10 minute break Topic i-1 papers / industrial tool survey (class participation) Topic i+1 main ideas and techniques (sreda) 5-10 minute break Topic i papers / industrial tool survey (class participation) Class participation (30% of final grade) Class project (70% of final grade)

10 Lecture 01: the big picture Course objective Brief tour of IC physical design Projects overview Survey of papers and industry products

11 Topic 01: CMOS scaling theory critical dimension Year CD (nm) How does scaling impact transistor and interconnect performance? How does scaling continuously present new challenges to physical design? And how does it make some techniques obsolete What is the fundamental limits to scaling (how far can we go)?

12 Topic 01: CMOS scaling theory [ITRS 03] [Moore, ISSCC 03] active leakage global (no repeaters) local (scaled) global wires (repeaters) gate delay

13 Topic 02: Process variability At 180nm and beyond, random sources of variation affect IC performance process dopant fluctuations gate oxide thickness gate length/width variations Normalized Frequency random sources runtime temperature IR drop Normalized Leakage [source: 180nm] Performance/power is no longer deterministic, but rather a random variable with an associated probability distribution 20x 30%

14 Topic 03: Static timing analysis (STA) C17 from ISCAS 85 benchmarks I 1 I 2 O 1 I 3 I 4 I 5 I 6 O 2 What is the worst delay of this circuit? determines the frequency of operation What are the critical path(s) that lead to this delay? perhaps timing can be improved if we adjust them

15 Topic 03: Static Timing Analysis (STA) hold time inputs Combinational logic FFs clock outputs clock FF input STA checks for any setup/hold time violations setup time At 130nm and below, transistor performance is no longer deterministic gate delay is not exact Statistical static timing analysis (academic papers survey)

16 Topic 04: Power analysis and optimization Total Power = static + dynamic + short NMOS transistor V dd A Z CMOS inverter factors capacitance switching frequency Leakage factors voltage transistor width/length, threshold Voltage temperature factors voltage trans. time switching freq Optimizations tweak these factors to minimize power with little impact on performance

17 Topic 05: Floorplanning and placement [IBM BigBlue4 2.1M instances] A chip has only a limited resources of metal (for interconnects) minimizing placement total wirelength minimizes chip s area Delay is dominated by interconnects minimizing the wirelength of critical nets optimizes performance Wire capacitance contributes to dynamic power minimizing the wirelength of high-frequency nets reduces power

18 Topic 05: Floorplanning and placement rows I/O pads Floorplanning (chip outlining) is a small scale 2-D assignment problem determines positions for large blocks of logic/memory [legal placement] [illegal placement] Placement of standard cells is a large-scale 2-D assignment problem determines positions for thousands/millions of standard cells

19 Topic 06: Clock tree synthesis Clock net(s) delivers the periodic generated clock signal to FFs Design objectives: minimum (ideally zero) skew minimum wirelength minimize buffers for signal integrity Minimum wirelength zero-skew tree for 64 FFs FF data FF [Kahng et al., TCAS 92] minimize demand on metal resources and reduces power minimize #buffers and maintain SI clock extra delay skew can lead to setup/hold times violations

20 Topic 07: Buffering (repeater insertion) for timing and signal integrity Delay of interconnect is a quadratic function in its length can be an unacceptable for global wires example: Itanium (180nm) requires 6 repeaters to span die Repeater insertion buffers wire capacitance and reduces overall delay x delay Distance x

21 Topic 07: Buffering (repeater insertion) for timing and signal integrity The situation is complicated in case of multi-pin nets: What is the minimum number of repeaters to meet timing on this net? sink source sink Repeater estimation for Itanium Repeater Stations

22 Topic 08: Design and analysis of power supply networks Power supply network delivers Vdd/Gnd signals to all components. [Blaauw et al., DAC98] Main challenges: 1. IR drop: voltage at delivery point is degraded than the ideal voltage performance drop signal integrity problems PowerPC 750 power grid 2. electromigration PowerPC 750 IR-drop map

23 Topic 09: Routing and parasitic extraction Objective: determine routes (tracks, layers, and vias) for each net such that the total wirelength is minimized. Be careful with routing critical nets and clock nets pin p 1 cell congestion pin p 2 Do you want this to happen to a net that belongs to the critical path?!

24 Topic 09: Routing and parasitic extraction Multi-pin nets add more complexity in routing sink create vias map to layers source sink After all routes are determined, you can calculate the parasitic capacitance between each wire and its neighbors

25 Topic 10: Design for manufacturability (DFM) Recent problems at manufacturing such as variability (in polysilicon length control, oxide thickness, dopant) chemical mechanical polishing alter design performance and calls for tighter integration between the manufacturing process and the design process design starting from 180nm manufacturing [Orshansky, TCAD00] DFM is a probably misnomer! (since when were we physically designing circuits that are not for manufacturing!)`

26 Topic 10: Design for Manufacturing example: fill insertion Downforce CMP (chemical mechanical polishing) is executed for each layer before buildup of other layers How can metal fill insertion helps in smoothing surfaces? Features Rotating platen Wafer carrier Wafer Polishing pad Slurry dispenser Polishing slurry Area fill features Post-CMP ILD thickness [(animation is not technically correct!] [Photos are form Quirk/Serda]

27 Topic 11: mask preparation and resolution enhancement techniques (RET) MEBES original layout GDSII fractured layout fractured layout into polygons (rectangles and trapezoids) [mask writer] Did we just forget something?!

28 Topic 11: mask preparation and resolution enhancement techniques (RET) Light source 193nm OPC increases the amount of data generated from fracturing 130nm feature [Schellenberg, IEEE Spectrum 03]

29 Extra topics: FPGA physical design IO assignment and packaging Design rule checking

30 Lecture 01: the big picture Course objective Brief tour of IC physical design Projects overview Survey of papers and industry products

31 Project slides omitted

32 Lecture 01: the big picture Course objective Brief tour of IC physical design Projects overview Survey of papers and industry products

33 Guidelines for academic paper reviews Describe the problem the paper addresses Why is the problem relevant (past/now/future)? Has this problem been addressed before? If yes, what is the new here? If no, is it meaningful? Assume you solve the problem, how will this change the world? Describe the methodology of the solution Why is this a good solution? Are they are any wrong/good assumptions/constraints? Are there any approximations? How good are they? Describe the experimental framework Benchmark / tools used (academic / industrial) Are the results compelling and competitive? Are the results possible to duplicate? Did the results proof beyond doubt that this is a useful approach

34 Guidelines for industry Industrial tool survey Describe the purpose of the tool and how it helps the IC designer. Describe the main inputs/outputs of the tool. Possibly describe the methodology used by the tool (search product sheets / websites / US patent office) Describe the possible options taken by the tool Describe the main strengths/weakness of the tool. (Compare the competitiveness of the tool to other tools.) Be simple and only explain what you understood (product review can be frustrating) Present the tool from a technology point of view, not a software (or marketing) point of view (avoid marketing propaganda) Check the possibility of getting a trial version.

35 Sources for information on tools Company websites US Patent office Google EEtimes Deepchip.com Edn.com

36 References EDA for Integrated Circuits Handbook (Volume 2), Scheffer/Lavagno/G. Martin, CRC Press. Algorithms for VLSI Physical Design Automation, Sherwani, 3 rd Edition, KAP Design of High-Performance Microprocessor Circuits, Chandraksan/Bowhill/Fox, IEEE Press. CMOS VLSI Design, Weste/Harris, 3 rd edition, Addison- Wesley. Semiconductor Manufacturing Technology, Quirk/Serda, Prentice Hall.

37 Key Websites

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University. EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Major Fabrication Steps in MOS Process Flow

Major Fabrication Steps in MOS Process Flow Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

Lecture #2 Solving the Interconnect Problems in VLSI

Lecture #2 Solving the Interconnect Problems in VLSI Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

Photolithography I ( Part 1 )

Photolithography I ( Part 1 ) 1 Photolithography I ( Part 1 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners.

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners. ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and Area Today Coping with Variation (from last time) Layout Transistors Gates Design rules Standard

More information

CS 6135 VLSI Physical Design Automation Fall 2003

CS 6135 VLSI Physical Design Automation Fall 2003 CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline

More information

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements Sign up for Piazza if you haven t already 2 1 Assigned Reading R.H.

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell

More information

VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN

VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN Peter M. Maurer ENG 118 Department of Computer Science & Engineering University of South Florida Tampa, FL 33620 1. The Nature of licon

More information

Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures

Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Chenming Hu and Je Min Park Univ. of California, Berkeley -1- Outline Introduction Background and Motivation MOSFETs with Vacuum-Spacer

More information

Announcements. Advanced Digital Integrated Circuits. Project proposals due today. Homework 1. Lecture 8: Gate delays,

Announcements. Advanced Digital Integrated Circuits. Project proposals due today. Homework 1. Lecture 8: Gate delays, EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture 8: Gate delays, Variability Announcements Project proposals due today Title Team members ½ page ~5 references Post it on your EECS web page

More information

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic

More information

Testing of Complex Digital Chips. Juri Schmidt Advanced Seminar

Testing of Complex Digital Chips. Juri Schmidt Advanced Seminar Testing of Complex Digital Chips Juri Schmidt Advanced Seminar - 11.02.2013 Outline Motivation Why testing is necessary Background Chip manufacturing Yield Reasons for bad Chips Design for Testability

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1 EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules

More information

DATASHEET CADENCE QRC EXTRACTION

DATASHEET CADENCE QRC EXTRACTION DATASHEET Cadence QRC Etraction, the industry s premier 3D fullchip parasitic etractor that is independent of design style or flow, is a fast and accurate RLCK etraction solution used during design implementation

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and

More information

Trends and Challenges in VLSI Technology Scaling Towards 100nm

Trends and Challenges in VLSI Technology Scaling Towards 100nm Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends

More information

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor

More information

Leakage Power Minimization in Deep-Submicron CMOS circuits

Leakage Power Minimization in Deep-Submicron CMOS circuits Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.

More information

Introduction to VLSI ASIC Design and Technology

Introduction to VLSI ASIC Design and Technology Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics

More information

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers

More information

EC 1354-Principles of VLSI Design

EC 1354-Principles of VLSI Design EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

RECENT technology trends have lead to an increase in

RECENT technology trends have lead to an increase in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1581 Noise Analysis Methodology for Partially Depleted SOI Circuits Mini Nanua and David Blaauw Abstract In partially depleted silicon-on-insulator

More information

Modeling the Effects of Systematic Process Variation on Circuit Performance

Modeling the Effects of Systematic Process Variation on Circuit Performance Modeling the Effects of Systematic Process Variation on Circuit Performance by Vikas Mehrotra Bachelor of Science, Wright State University, 1993 Master of Science, The Ohio State University, 1995 Submitted

More information

Interconnect-Power Dissipation in a Microprocessor

Interconnect-Power Dissipation in a Microprocessor 4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 3 Ch.1 The Evolution of The Microprocessor 17-Feb-15 1 Chapter Objectives Introduce the microprocessor evolution from transistors to

More information

EE141-Fall 2009 Digital Integrated Circuits

EE141-Fall 2009 Digital Integrated Circuits EE141-Fall 2009 Digital Integrated Circuits Lecture 2 Integrated Circuit Basics: Manufacturing and Cost 1 1 Administrative Stuff Discussions start this Friday We have a third GSI Richie Przybyla, rjp@eecs

More information

Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology

Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology OUTLINE Understanding Fabrication Imperfections Layout of MOS Transistor Matching Theory and Mismatches Device Matching, Interdigitation

More information

White Paper Stratix III Programmable Power

White Paper Stratix III Programmable Power Introduction White Paper Stratix III Programmable Power Traditionally, digital logic has not consumed significant static power, but this has changed with very small process nodes. Leakage current in digital

More information

32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family

32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family From Sand to Silicon Making of a Chip Illustrations 32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family April 2011 1 The illustrations on the following foils are low resolution

More information

Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion

Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion Fixing Antenna Problem by Dynamic Dropping and Jumper Insertion Peter H. Chen and Sunil Malkani Chun-Mou Peng James Lin TeraLogic, Inc. International Tech. Univ. National Semi. Corp. 1240 Villa Street

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

Sticks Diagram & Layout. Part II

Sticks Diagram & Layout. Part II Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

Wiring Parasitics. Contact Resistance Measurement and Rules

Wiring Parasitics. Contact Resistance Measurement and Rules Wiring Parasitics Contact Resistance Measurement and Rules Connections between metal layers and nonmetal layers are called contacts. Connections between metal layers are called vias. For non-critical design,

More information

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 Dummy Gate-Assisted n-mosfet Layout for a Radiation-Tolerant Integrated Circuit Min Su Lee and Hee Chul Lee Abstract A dummy gate-assisted

More information

FUNDAMENTALS OF MODERN VLSI DEVICES

FUNDAMENTALS OF MODERN VLSI DEVICES 19-13- FUNDAMENTALS OF MODERN VLSI DEVICES YUAN TAUR TAK H. MING CAMBRIDGE UNIVERSITY PRESS Physical Constants and Unit Conversions List of Symbols Preface page xi xiii xxi 1 INTRODUCTION I 1.1 Evolution

More information

Variation-Aware Design for Nanometer Generation LSI

Variation-Aware Design for Nanometer Generation LSI HIRATA Morihisa, SHIMIZU Takashi, YAMADA Kenta Abstract Advancement in the microfabrication of semiconductor chips has made the variations and layout-dependent fluctuations of transistor characteristics

More information

Modeling and CAD Challenges for DFY. Patrick G. Drennan Freescale Semiconductor Tempe, AZ, USA

Modeling and CAD Challenges for DFY. Patrick G. Drennan Freescale Semiconductor Tempe, AZ, USA Modeling and CAD Challenges for DFY Patrick G. Drennan Freescale Semiconductor Tempe, AZ, USA Outline Unphysical casing and statistical models Process gradients Gate protect diodes Shallow trench isolation

More information

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 81 Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness Alpana

More information

Session 3: Solid State Devices. Silicon on Insulator

Session 3: Solid State Devices. Silicon on Insulator Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

Nanometer Technologies: Where Design and Manufacturing Converge. Walden C. Rhines CHAIRMAN & CEO

Nanometer Technologies: Where Design and Manufacturing Converge. Walden C. Rhines CHAIRMAN & CEO Nanometer Technologies: Where Design and Manufacturing Converge Walden C. Rhines CHAIRMAN & CEO Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware

More information

Chapter 1, Introduction

Chapter 1, Introduction Introduction to Semiconductor Manufacturing Technology Chapter 1, Introduction hxiao89@hotmail.com 1 Objective After taking this course, you will able to Use common semiconductor terminology Describe a

More information

ASICs Concept to Product

ASICs Concept to Product ASICs Concept to Product Synopsis This course is aimed to provide an opportunity for the participant to acquire comprehensive technical and business insight into the ASIC world. As most of these aspects

More information

Lecture 0: Introduction

Lecture 0: Introduction Introduction to CMOS VLSI Design Lecture : Introduction David Harris Steven Levitan Harvey Mudd College University of Pittsburgh Spring 24 Fall 28 Administrivia Professor Steven Levitan TA: Bo Zhao Syllabus

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 Paper Setter Detail Name Designation Mobile No. E-mail ID Raina Modak Assistant Professor 6290025725 raina.modak@tib.edu.in

More information

Newer process technology (since 1999) includes :

Newer process technology (since 1999) includes : Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks

More information

! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements

! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams!

More information

Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007

Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 33-1 Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 Contents: 1. MOSFET scaling

More information

The Design and Realization of Basic nmos Digital Devices

The Design and Realization of Basic nmos Digital Devices Proceedings of The National Conference On Undergraduate Research (NCUR) 2004 Indiana University Purdue University Indianapolis, Indiana April 15-17, 2004 The Design and Realization of Basic nmos Digital

More information

EE141-Spring 2007 Digital Integrated Circuits

EE141-Spring 2007 Digital Integrated Circuits EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon

More information

EE 434 ASIC & Digital Systems

EE 434 ASIC & Digital Systems EE 434 ASIC & Digital Systems Dae Hyun Kim EECS Washington State University Spring 2017 Course Website http://eecs.wsu.edu/~ee434 Themes Study how to design, analyze, and test a complex applicationspecific

More information

Digital Integrated Circuits EECS 312

Digital Integrated Circuits EECS 312 14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980

More information

Layers. Layers. Layers. Transistor Manufacturing COMP375 1

Layers. Layers. Layers. Transistor Manufacturing COMP375 1 Layers VLSI COMP370 Intro to Computer Architecture t Applications Middleware other CS classes High level languages Machine Language Microcode Logic circuits Gates Transistors Silicon structures Layers

More information

Processing and Reliability Issues That Impact Design Practice. Overview

Processing and Reliability Issues That Impact Design Practice. Overview Lecture 15 Processing and Reliability Issues That Impact Design Practice Zongjian Chen Zongjian_chen@yahoo.com Copyright 2004 by Zongjian Chen 1 Overview As a maturing industry, semiconductor food chain

More information

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy

More information

Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect

Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Introduction - So far, have considered transistor-based logic in the face of technology scaling - Interconnect effects are also of concern

More information

Lecture Introduction

Lecture Introduction Lecture 1 6.012 Introduction 1. Overview of 6.012 Outline 2. Key conclusions of 6.012 Reading Assignment: Howe and Sodini, Chapter 1 6.012 Electronic Devices and Circuits-Fall 200 Lecture 1 1 Overview

More information

Statistical Static Timing Analysis Technology

Statistical Static Timing Analysis Technology Statistical Static Timing Analysis Technology V Izumi Nitta V Toshiyuki Shibuya V Katsumi Homma (Manuscript received April 9, 007) With CMOS technology scaling down to the nanometer realm, process variations

More information

Impact of Low-Impedance Substrate on Power Supply Integrity

Impact of Low-Impedance Substrate on Power Supply Integrity Impact of Low-Impedance Substrate on Power Supply Integrity Rajendran Panda and Savithri Sundareswaran Motorola, Austin David Blaauw University of Michigan, Ann Arbor Editor s note: Although it is tempting

More information

IFSIN. WEB PAGE Fall ://weble.upc.es/ifsin/

IFSIN. WEB PAGE   Fall ://weble.upc.es/ifsin/ IFSIN IMPLEMENTACIÓ FÍSICA DE SISTEMES INTEGRATS NANOMÈTRICS IMPLEMENTACIÓN N FÍSICA F DE SISTEMAS INTEGRADOS NANOMÉTRICOS PHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS Fall 2008 Prof. Xavier

More information

Semiconductor Devices

Semiconductor Devices Semiconductor Devices - 2014 Lecture Course Part of SS Module PY4P03 Dr. P. Stamenov School of Physics and CRANN, Trinity College, Dublin 2, Ireland Hilary Term, TCD 3 th of Feb 14 MOSFET Unmodified Channel

More information

Lecture 9: Cell Design Issues

Lecture 9: Cell Design Issues Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the

More information

The Physical Design of Long Time Delay-chip

The Physical Design of Long Time Delay-chip 2011 International Conference on Computer Science and Information Technology (ICCSIT 2011) IPCSIT vol. 51 (2012) (2012) IACSIT Press, Singapore DOI: 10.7763/IPCSIT.2012.V51.137 The Physical Design of Long

More information

Layout and technology

Layout and technology INF4420 Layout and technology Dag T. Wisland Spring 2015 Outline CMOS technology Design rules Analog layout Mismatch Spring 2015 Layout and technology 2 Introduction As circuit designers we must carefully

More information

THERE is a growing need for high-performance and. Static Leakage Reduction Through Simultaneous V t /T ox and State Assignment

THERE is a growing need for high-performance and. Static Leakage Reduction Through Simultaneous V t /T ox and State Assignment 1014 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 7, JULY 2005 Static Leakage Reduction Through Simultaneous V t /T ox and State Assignment Dongwoo Lee, Student

More information

EE 410: Integrated Circuit Fabrication Laboratory

EE 410: Integrated Circuit Fabrication Laboratory EE 410: Integrated Circuit Fabrication Laboratory 1 EE 410: Integrated Circuit Fabrication Laboratory Web Site: Instructor: http://www.stanford.edu/class/ee410 https://ccnet.stanford.edu/ee410/ (on CCNET)

More information

Manufacturing Characterization for DFM

Manufacturing Characterization for DFM Manufacturing Characterization for DFM 2006 SW DFT Conference Austin, TX Greg Yeric, Ph. D. Synopsys Outline What is DFM? Today? Tomorrow? Fab Characterization for DFM Information Goals General Infrastructure

More information

Low Power Design of Successive Approximation Registers

Low Power Design of Successive Approximation Registers Low Power Design of Successive Approximation Registers Rabeeh Majidi ECE Department, Worcester Polytechnic Institute, Worcester MA USA rabeehm@ece.wpi.edu Abstract: This paper presents low power design

More information

Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B.

Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B. Silicon VLSI Technology Fundamentals, ractice, and Modeling Class otes For Instructors J. D. lummer, M. D. Deal and. B. Griffin These notes are intended to be used for lectures based on the above text.

More information

Ramon Canal NCD Master MIRI. NCD Master MIRI 1

Ramon Canal NCD Master MIRI. NCD Master MIRI 1 Wattch, Hotspot, Hotleakage, McPAT http://www.eecs.harvard.edu/~dbrooks/wattch-form.html http://lava.cs.virginia.edu/hotspot http://lava.cs.virginia.edu/hotleakage http://www.hpl.hp.com/research/mcpat/

More information

MOSFET & IC Basics - GATE Problems (Part - I)

MOSFET & IC Basics - GATE Problems (Part - I) MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]

More information

MODELING OF DETERMINISTIC WITHIN-DIE VARIATION IN TIMING ANALYSIS, LEAKAGE CURRENT ANALYSIS, AND DELAY FAULT DIAGNOSIS

MODELING OF DETERMINISTIC WITHIN-DIE VARIATION IN TIMING ANALYSIS, LEAKAGE CURRENT ANALYSIS, AND DELAY FAULT DIAGNOSIS MODELING OF DETERMINISTIC WITHIN-DIE VARIATION IN TIMING ANALYSIS, LEAKAGE CURRENT ANALYSIS, AND DELAY FAULT DIAGNOSIS A Thesis Presented to The Academic Faculty by Munkang Choi In Partial Fulfillment

More information