The Design and Realization of Basic nmos Digital Devices

Transcription

1 Proceedings of The National Conference On Undergraduate Research (NCUR) 2004 Indiana University Purdue University Indianapolis, Indiana April 15-17, 2004 The Design and Realization of Basic nmos Digital Devices Wei-Han Jeng and Kan Banchusuwan Department of Electrical and Computer Engineering Virginia Military Institute Lexington, VA USA Faculty Advisor: Dr. J. Shawn Addington Abstract Our study involves the design, fabrication, and characterization of basic nmos digital logic gates, including basic inverter, NAND, and NOR devices on four-inch silicon wafers. Beginning with the fundamental device design rules, our study progresses into mask design and fabrication; semiconductor processing techniques, including wet and dry oxidation processes, positive and negative photolithography, selective diffusion of dopant (phosphorus) impurities, and metal (aluminum) deposition; and device characterization methods. The results of our study will include discussions of the following: 1) basic semiconductor device design and processing procedures using our laboratory facilities within the Department of Electrical and Computer Engineering at the Virginia Military Institute; 2) n-channel enhancement MOSFET (nmos) technology, including device structure, design layout, fabrication procedures, and device characteristics (I-V and transfer characteristics); 3) nmos digital device technology, including basic logic gate design options, and device operation; and 4) an evaluation of the performance characteristics of the basic digital logic devices that are fabricated in our laboratory. As these basic logic gates are the fundamental building blocks used in digital circuit design, a thorough understanding of their design and realization is essential before more complex circuits are attempted. Keywords: nmos, Logic Gate, Semiconductor 1. Basic Semiconductor Device Design The project is based on the characteristics of n-channel enhancement MOSFET (nmos) technology. Three kinds of basic logic gates are produced using nmos technology, that is, Inverter, NAND gate, and NOR gate. The fourmask process follows the same procedure as outlined in section 2.7 of Semiconductor Device Fabrication Study by Tsung-Ta Ho and M. Ryan Shealy [1]. There have been some changes in the processing, which are mentioned in section 2.2 in this paper. 2. nmos Technology 2.1 device structure and layout Figure 1 is the schematic, edge view, and top view of a nmos device. nmos enhancement mode devices may operate as switches by applying a gate (G) voltage to modulate (open and close) the channel between the source (S) and drain (D) regions. When the difference between gate and source voltage (V GS ) is more positive than the threshold voltage (V T ), an inversion layer (p-type material converted to n-type) is created under the gate that completes the channel and allows current (I D ) to flow through the circuit. Otherwise, the channel remains incomplete, and no current may flow.

2 Figure 1 different views of nmos device 2.2 fabrication process The device fabrication in this research is a four-mask process using 200µm design rules. In order to get better performance in a new lab environment, some changes to the original processing guidelines [1] were necessary. In summary, the device fabrication procedure includes: (a) Wet Oxidation: Prior to the wet oxidation, a 7 minute dry oxidation is performed to provide a good Si/SiO 2 interface. Then, a 2.5 hour wet oxidation is processed to grow a thick layer of silicon dioxide serving as a barrier layer for the diffusion process. At last, a 15 minute dry oxidation is performed to provide a quality oxide cap for the subsequent photolithography step. This process creates an average of 651nm SiO 2 barrier. (b) Negative Photolithography (mask 1): Selectively etch off the silicon dioxide in order to expose the regions in which n-wells will be diffused. (c) Diffusion: A phosphorus solid source is used in conjunction with a two-step diffusion profile in order to create n-wells in the p-si wafer. (d) Negative Photolithography (mask 2): Selectively etch off the silicon dioxide in order to expose the gate region of the nmos transistor. (e) Dry oxidation: Grow a thin layer of silicon dioxide serving as the gate oxide. An average of 51.3nm SiO 2 gate oxide is created. (f) Negative Photolithography (mask 3): Selectively etch off the thin silicon dioxide layer in order to expose contact holes for each device. (g) Metal Deposition: Deposit a thin layer of aluminum. (h) Positive Photolithography (mask 4): Selectively etch the aluminum layer and leave the desired interconnection between devices. Figure 2 transistor processing diagram 2

3 2.3 device characteristic Figure 3 shows the ideal transfer characteristic curve between I D and V GS. The important information gained from this curve is the threshold voltage (V T ), which is the voltage necessary to turn the device on. 2.3 nmos Digital Devices Figure 3 transfer characteristic of nmos transistor The design of logic gates is based on several references [2,3]. Figure 4 shows the schematics for inverter, NAND, and NOR gates, with corresponding layouts as introduced in section 2.1. The 4-masks used in the fabrication process are designed based on these three layouts. Figure 4 the symbol, schematic, and layout for logic devices 3

4 The saturated load configuration is used for our three logic gate designs. There are four possible loads that can be used for the logic gates. The other three loads are, resistor load, linear load, and depletion mode load. The disadvantage of the resistor load is its size. It is about 1000 times larger than the other load configurations. The disadvantage of the linear load is that it needs an extra probe connection, making it less convenient for data measurement. The saturated load and depletion mode load are the two choices of most concern in our study. Due to our experience in working with enhancement mode devices, we opted for the saturated load design. Future work, however, is planned in depletion mode devices. The (W/L) factor is also an important issue for the design of load and switching transistors. This ratio between the width and length of the device channel (see Figure 1) influences the ON resistance (on-r) of the device. The value of (on-r) is inversely proportional to (W/L), that is, a large (W/L) has a small (on-r). For the inverter design, the (on-r) of the switching transistor (M S ) is designed to be much less than the resistance of the load transistor (M L ), in order to achieve a small output voltage (V L ), corresponding to the logic 0. The NAND gate design consists of two switching transistors (M A and M B ) in series. Thus, the largest possible ON resistance of this switching structure becomes equal to twice the (on-r) of each individual switching transistor. Therefore, to maintain a low overall (on-r), (W/L) A and (W/L) B should be designed to be twice as large as the switching transistor used in the inverter design. The NOR gate design consists of two switching transistors in parallel. The largest possible ON resistance of this switching structure therefore remains the same as in the inverter design, and the size of the NOR switching transistors should be comparable to the size of the inverter switching transistor. In our study, the inverter design actually used an even larger ratio of switching (W/L) to load (W/L); however, the relationship between the NAND and NOR designs, in terms of (W/L) values, is consistent with the above analysis of (on-r) requirements. 3.1 basic operation The function of the inverter is Yout = Yin. Table 1 is the truth table of inverter. In the truth table, 0 indicates low logic state and 1 indicates high logic state. Table 1 truth table of inverter Inverter Vin Vout The logic function of the NAND gate is Y = (AB). Table 2 is the truth table of the NAND gate. Table 2 truth table of NAND gate NAND gate A B Y The expression of the NOR gate is Y = (A+B). Table 3 is the truth table of the NOR gate. Table 3 truth table of NOR gate NOR gate A B Y In addition to the design and layout options discussed earlier, available power supplies and desired current levels will also determine the voltage levels that correspond to logic 1 (V H ) and logic 0 (V L ). Supply voltages of 3.3V 4

5 and below, as well as the low power dissipation requirements of today s circuitry, are narrowing the difference between the V H and V L values, making noise a more significant concern in digital design. Another concern is the connection of multiple gates in complex logic design. The output of one gate, for example, must have enough voltage to drive/trigger the next gate. Of all of the design options mentioned previously, the saturated load design exhibits the least difference between V H and V L levels. Nevertheless, operational single gates (inverter, NAND, and NOR) have been realized, and are discussed in the next section. 4. Results The devices on the wafer are labeled into 12 positions, that is, 1~4 are Inverter, 5~8 are NAND gate, and 9~12 are NOR gate. The position of the devices is shown as Figure 5: 4.1 truth table a b Figure 5 device order on single wafer; a: device order, b: final product These devices are tested for their logic function by the ProbeStation to check if they are good or bad. After that, further data can be measured. The lab is not a clean room level environment; thus, we are still working on improving the yield. The load is supplied by 5V. The input is supplied by 5V or 0V. 5V and 0V correspond to the logic 1 and 0, respectively. Tables 4, 5, and 6 are the test results for Inverter, NAND gate, and NOR gate. A and B are inputs. Y is the output. Table 4 Inverter test result Inverter test with V DD = 5V Vin Vout(average) Table 5 NAND gate test result NAND gate test with V DD = 5V Table 6 NOR gate test result 5

6 NOR gate test with V DD = 5V A B Y (average) The results compare well with the expected performance of the logic gates. For the inverter, 1.882V and 0.55V correspond to the logic 1 and 0, respectively. The logic function, Vin = Vout, is stated. For the NAND gate, 3.347V, 3.555V, and 3.85V correspond to logic 1, and 1.973V corresponds to logic 0. This matches the expected NAND logic function from the truth table, that is, Y = (AB). For the NOR gate, 2.92V corresponds to the high logic state V, 0.665V, and 0.41V correspond to the low logic state. This also matches the NOR logic function from the truth table, Y = (A+B). 4.2 Observations threshold voltage analysis Ideally, for our circuits, the high logic state (V H ) should be 5V, and the low logic state (V L ) should be 0V. From the discussion in section 3, a lower (on-r) for the switching transistors should lower the V L value this is especially important for the NAND structure, as mentioned in section 3. Due to the special characteristics of the saturated load design, the V H level can be no larger than V DD V T. From this equation, V T is estimated to be 3.118V for the inverter load transistor, and 1.653V and 2.08V for the NAND and NOR load transistors, respectively. Note that these threshold voltage values include the impact of body effect, as discussed in the next section body effect Body effect, or substrate sensitivity, occurs when the source voltage of the transistor is not equal to the base (or substrate) voltage. [2] Note that in Figure 4, some of the transistors will exhibit V SB 0, because, while the B node is grounded, not all of the source nodes are grounded. The impact of body effect on the threshold voltage may be expressed by the following simplified expression, equation (1), where V T is the overall threshold voltage, V TO is the original threshold voltage (without body effect), and B is the body effect. V T = V TO + B (1) An estimate of the threshold voltage, excluding the body effect, may be achieved by evaluating the transfer characteristic of the inverter switching transistor, as shown in Figure 6. ID (ma) Transfer Characteristic of (4/1) transistor VGS (V) Figure 6 transfer characteristic of transistor with W/L = 4/1 6

7 Unlike the theoretical transfer characteristic shown in Figure 3, Figure 6 illustrates the difficulty in estimating the threshold voltage from experimental data. A measurement of our ON current level, however, provides one way of estimating the voltage necessary to turn on the transistor (V TO ). From an average ON current of 0.24mA, the threshold voltage (V TO ) for this transistor is estimated to be approximately 1.5V. Such variations in the overall threshold voltages, as summarized in section 4.2.1, are not unexpected for several reasons. First, the intensity of body effect is somewhat dependent on the physical size of the devices [2], and these digital devices require the use of transistors of different sizes for proper operation. Also, while the inverter and NOR gate designs only have one transistor influenced by base effect, the NAND design has two such transistors. As such, a more precise evaluation of body effect is outside the scope of this work. Nevertheless, one can see the importance of not overlooking body effect in digital design. 5. Conclusion This project involves the design, fabrication, and characterization of basic nmos digital logic gates which include Inverter, NAND and NOR gates on silicon wafers. Despite the inherent limitations of the saturated load design, and the uncertainty in V T due to body effect, operational single logic gates have been realized. Possible future work includes investigating threshold voltage and body effect in more depth, studying depletion mode devices, implementing depletion load configurations in digital device design, and designing for particular current and voltage levels in preparation for more complex digital circuit designs. 6. References [1] Tsung-Ta Ho and Michael R. Shealy, Semiconductor Device Fabrication Study, NCUR 2003 Proceedings, April 2003 [2] Jaeger, R.C. and Blalock, T.N., Microelectronic Circuit Design, 2 nd ed. (2004), McGraw Hill, New York, New York, pp , pp [3] Jaeger, R.C., Introduction to Microelectronic Fabrication, 2 nd ed. (2002), Vol. V of the Modular Series on Solid State Devices, Prentice Hall, Upper Saddle River, New Jersey, pp. 49, pp. 53, pp