Lecture 8. Thin-Body MOSFET s Process II. Source/Drain Technologies Threshold Voltage Engineering
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1 Atom Probe Tomography for Dopants in FinFETs Lecture 8 A.K. Kambham (imec), VLSI-T 2012 Thin-Body MOSFET s Process II Source/Drain Technologies Threshold Voltage Engineering Reading: multiple research articles (reference list at the end of this lecture)
2 FinFET Source/Drain Doping Challenges: I. Fin Amorphization TCAD Simulation Results L. Pelaz, IEDM (2009) After the high energy implantation, Source/Drain regions are always amorphized. Requires annealing for S/D regrowth to prevent leakage and reliability issues. Source/Drain For <110> FinFETs, the (111) planes will eventually prevent the Si re-crystallization. R. Duffy, APL (2007) 2
3 FinFET Source/Drain Doping Challenges: II. Vertical Conformance TCAD Simulation Results Cross-sectional (left) and lateral (right) view of the B concentration in a FinFET implanted region with: L. Pelaz, IEDM (2009) Energy Dose Tilt a o b o c 0.5 5x o d o 3 After 1100 o C Spike Annealing
4 Effective Channel Length (L eff ) Source Drain Gate Overlap Gate Underlap More reasonable (than L g ) parameter to optimize device performance with a certain gate pitch (i.e. technology node). 4
5 H=25nm H=25nm Impacts of Source/Drain Doping Conformance Conformal S/D Doping W=15nm L g =20nm L eff is always 30nm SOI FinFET w/ Uniform doping in S/D region Non-conformal S/D Doping W=15nm L g =20nm L eff starts from 30nm SOI FinFET w/ Gauss doping in S/D region Doping concentration (cm -3 ) Simulated SOI FinFET Performance 1.0E E E E E-15 V -1.0E ds =0.7V Drain Current (A/um) L gate = 20nm Normalized over W eff = 2*H fin + W fin W=1um Planar FinFET w/ Conformal S/D Dop. FinFET w/ Gaussian S/D Dop Gate Voltage (V) S/D doping conformance strongly affects FinFET s L eff and causing performance change. 5
6 Self-Regulatory Plasma Doping in FinFET s S/D Dense Fins High Aspect- Ratio Fins Y. Sasaki, IEDM (2008) 6
7 S/D Doping Optimizations for Improving FinFET Performance -20% -50% A multi-step implantation with different energies and ion species improves the vertical doping conformance. T. Yamashita, VLSI-T (2011) 7
8 In Situ-Doped S/D in FinFETs TCAD Simulation Results of S/D epi-regrowth after etching In Situ-doped Source Drain Simulation shows the final source/drain shape doesn t depend on the initial Si over etch depth. Courtesy of V. Moroz and M. Choi (Synopsys) (100) (111) Boron Doping Concentration (cm -3 ) Retrograde Well ~ 3 nm/dec Distance along Channel (nm) (011) Intel s TriGate FET s S/D 8
9 Impact of FinFET s Raised S/D Shape H. Kawasaki, IEDM (2009) 9
10 Why We Want Multiple V TH? 10
11 11
12 Back Biasing Tuning in UTBB SOI MOSFETs Body Bias V b =2V V b =0V V b =-2V V ds =1.2V 10-5 Drain Current (A/um) V ds =1.2V n-fdsoi L g =10um V ds =10mV n-fdsoi L eff =52nm T. Skotnicki, IEDM SC (2010) Gate Voltage (V) Gate Voltage (V) Reverse Back Biasing: V BG : NMOS(-), PMOS(+) V TH Forward Back Biasing: V BG : NMOS(+), PMOS(-) V TH 12
13 (Back Biasing) Body Coefficient V g Strong Reverse Bias Strong Forward Bias C ox 1 C ox 1 2 C BOX 2 C BOX Define coefficient r : //, //, so that V TH = r V BG V bg Forward Bias Reverse Bias Body Coefficient Simulated t SOI =11nm t SOI =7nm t SOI =4nm t SOI =5nm Measured t BOX =5nm t BOX =11nm Back Bias (V) 13
14 UTBB SOI MOSFET s V TH Engineering T. Skotnicki, IEDM SC (2010) 14
15 Impact of Back Biasing on UTBB SOI MOSFET s Electrostatics Q. Liu, VLSI-T (2011) STMicroelectronics 28nm UTBB FDSOI MOSFETs DIBL (mv/v) N. Xu, VLSI-T (2012) RBB (or counter-type GP): better electrostatics FBB (or same-type GP): worse electrostatics 15
16 Electron Mobility (cm 2 /V.s) Impact of Back Biasing on UTBB SOI MOSFET s Carrier Mobility UTBB s eff vs. E eff Reduction due to HKMG (First) Back Bias +2V +1.5V +1V 0V -1V -2V (100) Si Universal Effective Field (MV/cm) still follows universal mobility curve However, what matters I ON is eff at a certain N inv. Electron Mobility (cm 2 /V.s) UTBB s eff vs. N inv (100)/<110> n-fdsoi T=300K V b =2V V b =1.5V V b =1V V b =0V V b =-1V V b =-2V Inversion Electron Concentration (cm -2 ) RBB (or counter-type GP): lower mobility FBB (or same-type GP): higher mobility 16
17 Back Biasing in Tri-Gate MOSFET TEM of Nanowire Tri-Gate FET BB-V th Tuning vs. W Fin BB-V th Tuning vs. H Fin Si Back Biasing will be ineffective to tune V TH when the back surface area is relatively small. Not an option for typical FinFETs. M. Saitoh, VLSI-T (2012) 17
18 FinFET s V TH Engineering C.-H. Lin, VLSI-T (2012) Normalized Drain Current (A/um) HP: N fin =1e16, L g =14nm LP: N fin =1e18, L g =20nm N peak =1e19cm -3 N peak =3e18cm -3 N peak =2e18cm -3 N peak =1e18cm Gate Voltage (V) The V TH tuning ability of channel doping is limited in FinFET, due to the shrink of Si volume as well as the superposition from PTS doping profile. Multiple gate length (L eff ) has to be used to tune V TH. 18
19 State-of-the-Art FinFET s SoC Intel s 20nm TriGate MOSFET NMOS: I off -I dsat Wordline R. Brain, VLSI-T (2013) Knobs: gate length (L g & L eff ) Doping (PTS, Fin ) C.-J. Jan, IEDM (2012) 19
20 Summary of FinFET and UTBB SOI MOSFET s V TH Engineering Assuming single gate metal (workfunction) for each type (N or P) of MOSFETs. I OFF (na/um) FinFET I OFF (na/um) UTBB SOI MOSFET 100 na SLVT Low Doping SLVT FBB + GP doping 10 na 1 na 100 pa 10 pa LVT Low Doping, Moderate L g RVT High Doping, Moderate L g HVT High Doping, Long L g I EFF LVT ZBB + GP doping RVT RBB + GP doping HVT RBB + GP doping, Long L g I EFF 20
21 FinFET Source/Drain References 1. L. Pelaz, L. Marques, M. Aboy, P. Lopez, I. Santos, R. Duffy, Atomistic Process Modeling Based on Kinetic Mone Carlo and Molecular Dynamics for Optimization of Advanced Devices, IEEE International Electron Device Meeting Tech. Dig., pp , R. Duffy, M.J.H. Van Dal, B.J. Pawlak, M. Kaiser, R.G.R. Weemaes et al., Solid Phase Epitaxy versus Random Nucleation and Growth in sub-20nm Wide Fin Field-Effect Transistors, AIP Applied Physics Letters, Vol.90, , Y. Sasaki, K. Okashita, K. Nakamoto, T. Kitaoka, B. Mizunoet al., Conformal Doping for FinFETs and Precise Controllable Shallow Doping for Planar FET Manufacturing by a Novel B2H6/Helium Self-Regulatory Plasma Doping Process, IEEE International Electron Device Meeting Tech. Dig., pp , T. Yamashita, V.S. Basker, T. Standaert, C.-C. Yeh, T. Yamamoto et al., Sub-25nm FinFET with Advanced Fin Formation and Short Channel Effect Engineering, Symposium on VLSI Technology Dig., pp.14-15, M. Choi, V. Moroz, L. Smith, O. Penzin, 14nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain, International SiGe Technology and Device Meeting Tech. Dig., H. Kawasaki, V.S. Basker, T. Yamashita, C.-H. Lin, Y. Zhu et al., Challenges and Solutions of FinFET Integration in an SRAM Cell and a Logic Circuit for 22nm Node and Beyond, IEEE International Electron Device Meeting Tech. Dig., pp , UTBB SOI V TH Tuning 7. T. Skotnicki, CMOS Technologies Trends, Scaling and Issues, IEEE International Electron Device Meeting Short Course,
22 References 8. Q. Liu, F. Monsieur, A. Kumar, T. Yamamoto, A. Yagishita et al., Impact of Back Bias on Ultra-Thin Body and BOX (UTBB) Devices, Symposium on VLSI Technology Dig., pp , N. Xu, F. Andrieu, B. Ho, B.-Y. Nguyen, O. Weber et al., Impact of Back Biasing on Carrier Transport in Ultra-Thin-Body and BOX (UTBB) Fully Depleted SOI MOSFETs, Symposium on VLSI Technology Dig., pp , FinFET V TH Tuning 10. M. Saitoh, K. Ota, C. Tanaka, K. Uchida, T. Numata, 10nm-Diameter Tri-Gate Silicon Nanowire MOSFETs with Enhanced High-Field Transport and V TH Tunability through Thin BOX, Symposium on VLSI Technology Dig., pp.11-12, C.-H. Lin, R. Kambhampati, R.J. Miler, T.B. Hook, A. Bryant et al., Channel Doping Impact on FinFETs for 22nm and Beyond, Symposium on VLSI Technology Dig., pp.15-16, (Intel s Tri-Gate SoC) C.-H. Jan, U. Bhattacharya, R. Brian, S.-J. Choi, G. Gurello et al., A 22nm SoC Platform Technology Featuring3-DTri-GateandHigh-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications, IEEE International Electron Device Meeting Tech. Dig., pp.44-47, (Intel s Tri-Gate edram) R. Brian, A. Baran, N. Bisnik, H.-P. Chen, S.-J. Choi et al., A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-Gate Transistors and MIMCAP COB, Symposium on VLSI Technology Dig., pp.16-17,
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