III-V CMOS: Quo Vadis?

Transcription

1 III-V CMOS: Quo Vadis? J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology Compound Semiconductor Week 2018 Cambridge, MA, May 29-June 1, 2018 Acknowledgements: Former students and collaborators: D. Antoniadis, E. Fitzgerald, J. Grajal, J. Lin Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung, SRC Labs at MIT: MTL, EBL

2 Quo Vadis? = Where are you going? 2

3 III-V CMOS: The Promise Scaling: Voltage Current density Performance Current density of n-mosfets at nominal voltage: Source injection velocity: Si vs. InGaAs FETs del Alamo, Nature 2011 v inj (InGaAs) > 2v inj (Si) at less than half V DD high current at low voltage 3

4 Transconductance of Planar Si vs. InGaAs MOSFETs n-mosfets in Intel s nodes at nominal voltage Comparisons always fraught with danger 4

5 Transconductance of Planar Si vs. InGaAs MOSFETs n-mosfets in Intel s nodes at nominal voltage Comparisons always fraught with danger InGaAs stagnant for a long time 5

6 Transconductance of Planar Si vs. InGaAs MOSFETs n-mosfets in Intel s nodes at nominal voltage Comparisons always fraught with danger Rapid recent progress InGaAs exceeds Si 6

7 Transconductance of Planar Si vs. InGaAs MOSFETs n-mosfets in Intel s nodes at nominal voltage MIT (V DS =0.5 V) Comparisons always fraught with danger Rapid recent progress InGaAs exceeds Si Lin, IEDM 2014 EDL

8 Many requirements for a successful logic technology 1. ON current 2. OFF current 3. Scalability 4. Stability 5. Manufacturing robustness 6. Si integration 8

9 Evolution of transistor structure for improved scalability Planar bulk MOSFET Thin-body SOI MOSFET FinFET Nanowire MOSFET Enhanced gate control improved scalability 9

10 Evolution of transistor structure for improved scalability FinFET Enhanced gate control improved scalability 10

11 Transconductance of planar Si vs. InGaAs MOSFETs 11

12 Transconductance of Si vs. InGaAs FinFETs 12

13 Transconductance of Si vs. InGaAs FinFETs W f g m normalized by fin width FinFET: large increase in current density per unit footprint over planar MOSFET 13

14 Transconductance of Si vs. InGaAs FinFETs W f MIT (V DS =0.5 V) g m normalized by fin width Best InGaAs FinFETs nearly match 14 nm Si MOSFETs 14

15 Transconductance of Si vs. InGaAs FinFETs 10 nm node Intel (V DS =0.7 V) W f g m normalized by fin width 10 nm node Si MOSFETs a great new challenge! 15

16 InGaAs MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Sub-10 nm fin width Aspect ratio > 20 Vertical sidewalls Vardi, DRC 2014, EDL 2015, IEDM

17 InGaAs MIT High-K SiO 2 W/Mo n + -InGaAs L g Mo HSQ InGaAs δ - Si InAlAs InP HSQ High-K InGaAs Mo InP Vardi, IEDM 2017 Si-compatible process Contact-first, gate-last process Fin etch mask left in place double-gate MOSFET 17

18 Most aggressively scaled FinFET W f =5 nm, L g =50 nm, H c =50 nm (AR=10), EOT=0.8 nm: 150 V GS =-0.2 to 0.5 V V GS =0.1 V 1E-3 1E-4 L g =50 nm W f =5 nm V DS =500 mv 50 mv 1E-5 I d [µa/µm] I d [A/µm] 1E-6 1E-7 1E-8 S sat =75 mv/dec S lin =65 mv/dec Normalized by conducting gate periphery = 2H c Vardi, IEDM V GS [V] At V DS =0.5 V: g m =565 µs/µm R on =660 Ω.µm S sat =75 mv/dec DIBL=22 mv/v g m [µs/µm] 1E V DS =0.5 V L g =50 nm W f =5 nm V GS [V] V GS [V] g m,max =565 µs/µm 18

19 Fin-width scaling of ON-state current 2.0 Vardi, IEDM Normalized by conducting gate periphery = 2H c in planar MOSFETs expect g m independent of W f down to W f =7 nm In planar MOSFET (x=0.53) expect g m ~ 2.2 ms/µm Missing performance hints at sidewall damage g m [ms/µm] 2.2 ms/µm 0.5 L g =40-60 nm R on [Ω-µm] W f [nm] V DS = 0.5 V W f [nm] 19

20 Fin-width scaling of OFF-state current I d [A/µm] 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 L g =50 nm V DS =500 mv W f =5 nm 50 mv S sat =75 mv/dec S lin =65 mv/dec V GS [V] S [mv/dec] S sat (V DS = 0.5 V) S sat S lin S lin (V DS = 50 mv) 60 L g =40-60 nm W f [nm] Excellent subthreshold swing scaling behavior From long L g devices: D it ~ 8x10 11 cm -2.eV -1 Vardi, IEDM

21 Excess OFF-state current Band-to-band tunneling (BTBT) at drain end of channel Zhao, EDL 2018 Classic BTBT behavior in long-channel devices 21

22 Excess OFF-state current Current multiplication through parasitic bipolar transistor -1 slope Large BJT current gain (up to ~100) Short L g : β ~ 1/L g Long L g : β ~ exp(-l g /L d ), L d 2-4 µm Zhao, EDL 2018, CSW

23 Manufacturing robustness: impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Vardi, IEDM 2015 T=90K Strong V T sensitivity for W f < 10 nm; much worse than Si Due to quantum effects Big concern for future manufacturing 23

24 MOSFET threshold voltage stability Planar InGaAs MOSFETs under forward-gate stress (V gs >0): 2.5 nm HfO 2 V t : power law in time and stress voltage Typical of PBTI (Positive Bias Stress Instability) Cai, IEDM

25 MOSFET stability due to oxide traps Planar InGaAs MOSFETs under forward-gate stress: time to 30mV shift (s) V gt = years V gt,stress (V) g m,max and V t,lin correlated Negligible change in S 30 mv shift in 10 years for V gt = 0.4 V Oxide traps = O vacancies in HfO 2 Cai, IEDM 2016 Excellent review by Franco, IEDM

26 Other manifestations of oxide traps C-V frequency dispersion g m frequency dispersion Pulsed vs. DC Cai, CSW 2018 Also: Johansson, ESSDERC 2013 Frequency dispersion in C g and g m Pulsed I-V DC I-V DC underestimates transistor potential Also: Cartier, ESSDERC

27 InGaAs Vertical Nanowire MOSFETs VNW MOSFET Vertical NW MOSFET: uncouples footprint scaling from L g, L spacer, and L c scaling 27

28 InGaAs VNW-MOSFETs by top-down MIT Lu, EDL 2017 Top-down approach: flexible and manufacturable Critical technologies: precision RIE + alcohol-based digital etch 28

29 D=7 nm InGaAs VNW MOSFET I d (µa/µm) V gs = 0 V to 0.8 V in 0.1 V step D = 7 nm Top contact = Drain V ds (V) Single nanowire MOSFET: L ch = 80 nm 2.5 nm Al 2 O 3 (EOT = 1.3 nm) g m,pk =1700 µs/µm Top contact = key problem Zhao, IEDM 2017 I d (A/µm) I d (µa/µm) 10-3 D = 7 nm V ds =0.5 V V ds =0.05 V S lin /S sat = 85/90 mv/dec DIBL = 222 mv/dec V gs (V) 100 Vgs = 0 V to 0.8 V in 0.1 V step D = 7 nm 80 Top contact = Source V ds (V)

30 Benchmark with Si/Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs V DS =0.5 V Zhao, IEDM 2017 First sub-10 nm diameter VNW FET of any kind on any material system InGaAs competitive with Si [hard to add strain] 30

31 InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid (VLS) Technique Selective-Area Epitaxy (SAE) Riel, MRS Bull 2014 VNW MOSFETs: path for III-V integration on Si for future CMOS Riel, IEDM

32 Conclusions 1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for 3D architecture designs severe oxide trapping masks true transistor potential 3. Serious challenges identified: excess off-current, stability, manufacturability, integration with Si 4. Vertical Nanowire MOSFET: ultimate scalable transistor; integrates well on Si 32