InGaAs MOSFET Electronics

Transcription

1 InGaAs MOSFET Electronics J. A. del Alamo Microsystems Technology Laboratories, MIT The 17 th International Symposium Physics of Semiconductors and Applications Jeju, Korea, December 7-11, 2014 Acknowledgements: D. Antoniadis, A. Guo, L. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, W. Lu, A. Vardi, N. Waldron, L. Xia Sponsors: Intel, FCRP-MSD, ARL, SRC, NSF, Sematech, Samsung Labs at MIT: MTL, NSL, SEBL 1

2 InGaAs electronics in your pocket! 2

3 A bit of perspective Invention of AlGaAs/GaAs HEMT: Fujitsu Labs First InAlAs/InGaAs HEMT on InP: Bell Labs First AlGaAs/InGaAs Pseudomorphic HEMT: U. Illinois 1985 Main attraction of InGaAs: RT μ e = 6,000~30,000 cm 2 /V.s Mimura, JJAPL 1980 Chen, EDL 1982 Ketterson, EDL

4 InGaAs High Electron Mobility Transistor (HEMT) Modulation doping: 2-Dimensional Electron Gas in narrow-bandgap channel 4

5 InGaAs HEMT: high-frequency record vs. time f T (GHz) Teledyne/MIT: f T =688 GHz InGaAs HEMT Year Devices fabricated at MIT f T =710 GHz Chang, APEX 2013 (NCTU) Kim, EDL 2010 Highest f T of any FET on any material system 5

6 InGaAs HEMTs: circuit demonstrations 9-stage 850 GHz LNA 80 Gb/s multiplexer IC Deal, MTT-S 2014 Wurfl, GAAS Gb/s wireless data at 113 GHz Sarkozy, IPRM 2013 Thome, MTT-S

7 InGaAs HEMTs map infant universe WMAP=Wilkinson Microwave Anisotropy Probe Launched 2001 Full-sky map of Cosmic Microwave Background radiation (oldest light in Universe) age of Universe: 13.73B years (±1%) µm InGaAs HEMT LNA Pospieszalski, MTT-S

8 Record f T InGaAs HEMTs: megatrends Classic scaling trajectory: L g, t ins Recently: L g, t ins saturated no more progress possible? 8

9 Limit to HEMT barrier scaling: gate leakage current InGaAs HEMTs practical limit L g =40 nm V DS =0.5 V Kim, EDL 2013 At L g =30-40 nm, modern HEMTs are at the limit of scaling! 9

10 Solution: introduce gate oxide! InGaAs HEMTs 10-5 x! L g =40 nm V DS =0.5 V Al 2 O 3 (3 nm)/inp (2 nm)/ingaas MOSFET Kim, EDL 2013 Need high-k gate dielectric: HEMT MOSFET! 10

11 InGaAs MOSFET with f T =370 GHz Channel: 10 nm In 0.7 Ga 0.3 As Barrier: 1 nm InP + 2 nm Al 2 O 3 Kim, APL 2012 L g = 60 nm f T = 370 GHz g m = 2 ms/μm 11

12 InGaAs HEMT vs. MOSFET Since when can we make III-V MOSFETs? 12

13 Historical evolution: InGaAs MOSFETs vs. HEMTs Transconductance (g m ): g m =3.1 ms/μm * *inversion-mode Lin, IEDM 2014 Recent progress due to improvement of oxide/iii-v interface 13

14 What made the difference? Atomic Layer Deposition (ALD) of oxide ALD eliminates native oxides that pin Fermi level Self cleaning Huang, APL 2005 Clean, smooth interface without native oxides First observed with Al 2 O 3, then with other high-k dielectrics First seen in GaAs, then in other III-Vs 14

15 Interface quality: Al 2 O 3 /InGaAs vs. Al 2 O 3 /Si Al 2 O 3 /InGaAs Al 2 O 3 /Si E v E c E v E c Brammertz, APL 2009 Werner, JAP 2011 Close to E c, Al 2 O 3 /InGaAs comparable D it to Al 2 O 3 /Si interface 15

16 Electron velocity: InGaAs vs. Si Measurements of electron injection velocity in HEMTs: del Alamo, Nature 2011 v inj (InGaAs) increases with InAs fraction in channel v inj (InGaAs) > 2v inj (Si) at less than half V DD ~100% ballistic transport at L g ~30 nm 16

17 Logic InGaAs MOSFET: possible designs Enhanced gate control enhanced scalability 17

18 Self-aligned Planar InGaAs MOSFETs W Mo Recess-gate process: CMOS-compatible Refractory ohmic contacts (W/Mo) Extensive use of RIE Lin, IEDM 2012, 2013,

19 Fabrication process Mo/W ohmic contact + SiO 2 hardmask SF 6, CF 4 anisotropic RIE Resist CF 4 :O 2 isotropic RIE SiO 2 W/Mo n + InGaAs/InP InGaAs/InAs InAlAs δ-si InP Waldron, IEDM 2007 Cl 2 :N 2 anisotropic RIE Digital etch O 2 plasma diluted H 2 SO 4 Gate stack and pads Pad Mo HfO 2 Lin, EDL 2014 Ohmic contact first, gate last Precise control of vertical (~1 nm), lateral (~5 nm) dimensions MOS interface exposed late in process 19

20 L g =20 nm InGaAs MOSFET SiO 2 W Mo n + cap Channel Buffer 20 nm Ti/Au pad Gate: Mo Spacer: Oxide Contact: Mo Mo/HfO 2 20 nm 15 nm 1.0 L g =20 nm V gs -V t = 0.5 V 0.8 R on =224 Ω.µm 0.4 V InAs V ds (V) I d (ma/µm) Lin, IEDM 2013 L g = 20 nm, L access = 15 nm MOSFET tightest III-V MOSFET ever made? 20

21 Highest performance InGaAs MOSFET L g =80 nm, EOT=0.5 nm (2.5 nm HfO 2 ), t c =9 nm, L access =15 nm I d (ma/µm) V gs = -0.3 to 0.4 V in 0.1 V step L g = 80 nm R on =190 Ω.µm V ds (V) g m (ms/µm) gm,max = 3.1 ms/µm L g = 80 nm V ds = 0.5 V V gs (V) Record g m,max = 3.1 ms/µm at V ds = 0.5 V R on = 190 Ω.µm Lin, IEDM

22 Subthreshold characteristics L g =80 nm, EOT=0.5 nm (2.5 nm HfO 2 ), t c =9 nm, L access =15 nm V ds =0.5 V I d (A/µm) V ds =0.05 V BTBT V ds =0.5 V: S min =159 mv/dec DIBL=310 mv/v V gs (V) Lin, IEDM 2014 Modest subthreshold swing, DIBL explore channel thickness scaling Excess OFF current at V ds =0.5 V Band-to-Band Tunneling (BTBT) 22

23 Impact of channel thickness scaling Lin, IEDM 2014 S min (mv/dec) t c =12 nm t c 3 nm V ds =0.5 V V ds =0.5 V L g (µm) g m,max (ms/µm) t c =9 nm 8 nm 11 nm 7 nm 12 nm 4 nm 3 nm V ds =0.5 V L g (µm) t c S but also g m,max Even at t c =3 nm, L g,min ~40 nm planar MOSFET at limit of scaling 23

24 Excess OFF-state current Transistor fails to turn off: I d (A/µm) 10-5 L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) OFF-state current enhanced with V ds Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM

25 Excess OFF-state current I d (A/µm) T=200 K V ds =0.7 V L g =80 nm 120 nm 280 nm 500 nm V gs -V t (V) Lin, EDL 2014 L g OFF-state current additional bipolar gain effect due to floating body I d (A/µm) I d (A/µm) 10-5 L g =500 nm w/ W/ BTBT+BJT w/o W/O BTBT+BJT L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) Simulations V ds =0.3~0.7 V step=50 mv V gs (V) 25

26 Planar Regrown-contact InGaAs MOSFET g m =2.5 ms/μm selective MOCVD Lee, EDL 2014 Regrown contact MOSFET: Avoids RIE in intrinsic region Contacts self-aligned to dummy gate 26

27 InGaAs Trigate MOSFET 60 nm Kim, IEDM 2013 L g =60 nm W F =30 nm g m =1.5 ms/µm, S=77 mv/dec, DIBL=10 mv/v L g (µm) S min (mv/dec) t c =12 nm t c V ds =0.5 V 3 nm V ds =0.5 V 27

28 InGaAs double-gate MOSFET 40 nm 30 nm Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE digital etch Zhao, EDL 2014; Vardi, DRC

29 InGaAs double-gate MOSFET Long-channel MOSFET characteristics (W f =12~37 nm): I D [µa/µm] 20 Wf =12 nm L g =5 μm V GS =0.5 V V GS =0 V V DS [V] At sidewall: D it,min ~ 3x10 12 ev -1.cm -2 Vardi, DRC

30 Vertical nanowire InGaAs MOSFET 30 nm diameter InGaAs NW-MOSFET Zhao, IEDM 2013 Zhao, EDL 2014 Nanowire MOSFET: ultimate scalable transistor Vertical NW: uncouples footprint scaling from L g scaling Top-down approach based on RIE + digital etch 30

31 Tomioka, Nature 2012 Persson, DRC 2012 Process flow 31

32 Trade-off between transport and short-channel effects Persson, EDL 2012 Bottom up Top down Persson, DRC 2012 Tomioka, Nature 2012 Tanaka, APEX 2010 D S but also g m 32

33 Si integration: SOI-like InGaAs planar MOSFETs n + cap Mo InGaAs channel BOX p-si III-V bonded SOI process: Czornomaz, IEDM 2012 Lin, DRC 2014 BOX: Al 2 O 3 InP donor wafer InGaAs channel n + cap InP donor wafer InP donor wafer BOX p-si BOX p-si 1. MBE growth 2. ALD Al 2 O 3 3. Wafer bonding 4. InP etch back 33

34 Si integration: SOI-like InGaAs planar MOSFETs SiGe p-mosfet InGaAs n-mosfet Czornomaz, IEDM 2013 CMOS inverter transfer characteristics 34

35 Si integration: InGaAs Trigate MOSFETs by Aspect Ratio Trapping Fin growth in narrow trench Mg-doped InP buffer Si Waldron, VLSI Tech

36 Si integration: InGaAs Vertical Nanowire MOSFETs by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid (VLS) Technique Selective-Area Epitaxy Riel, MRS Bull 2014 Björk, JCG

37 Conclusion: exciting future for InGaAs electronics 37