III-V Vertical Nanowire FETs with Steep Subthreshold Towards Sub-10 nm Diameter Devices

Transcription

1 III-V Vertical Nanowire FETs with Steep Subthreshold Towards Sub-10 nm Diameter Devices Jesús A. del Alamo, Xin Zhao, Wenjie Lu, Alon Vardi Microsystems Technology Laboratories, MIT E 3 S Retreat September 7, 2017 Program leverage: SRC-GRC, Lam Research, Samsung, KIST 1

2 Goals and activities Demonstration of steep-subthreshold III-V vertical nanowire (VNW) transistors: Tunnel FETs SuperLattice-Source FETs Technology for sub-10 nm diameter VNW FETs: Etching technology Sidewall passivation Top contact Device integration Trapping and noise in VNW FETs (Xin Zhao) 2

3 Vertical nanowire FET: ultimate scalable transistor L L c spacer L g Vertical NW FET: uncouples footprint scaling from L g, L spacer, and L c scaling 3

4 1. Progress towards sub-10 nm InGaAs VNW-FETs MIT pursuing top-down approach for VNW fabrication Starting heterostructure: n+ InGaAs: 11 nm n+ InAs: 2 nm n+ In 0.7 Ga 0.3 As: 6 nm n+ InGaAs, 55 nm i InGaAs, 80 nm n+ InGaAs, 300 nm Top-down approach: flexible and manufacturable 4

5 Key enabling technologies: RIE + digital etch RIE = BCl 3 /SiCl 4 /Ar chemistry Digital Etch (DE) = self-limiting O 2 plasma oxidation + H 2 SO 4 or HCl oxide removal Radial etch rate=1 nm/cycle Sub-20 nm NW diameter Aspect ratio > 10 Smooth sidewalls RIE + 5 cycles DE Zhao, IEDM 2013 Zhao, EDL 2014 Zhao, IEDM

6 Alcohol-Based Digital Etch 8 nm InGaAs VNWs after 7 DE cycles: 10% HCl in DI water Yield = 0% 10% HCl in IPA Yield = 97% Broken NW Alcohol-based DE enables D < 10 nm Lu, EDL

7 Alcohol-Based Digital Etch 10% H 2 SO 4 in methanol D=5.5 nm with 90% yield First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40) Lu, EDL

8 III-V VNW MOSFET/TFET process flow New elements: 1. Alcohol-based digital etch 2. Ni contacts 3. Final RTA/FGA 8

9 D=30 nm Mo-contacted VNW MOSFETs I d (µa/µm) V gs = 0 V to 0.7 V in 0.1 V step R on = 1358 Ω µm Mo contact D = 30 nm 300 o C RTA (V) Single nanowire MOSFET: L ch = 80 nm 2.5 nm Al 2 O 3 (EOT = 1.25 nm) 300 o C N 2 RTA, 1 min S lin = 66 mv/dec (near ideal!) g m (µs/µm) I d (A/µm) V gs (V) 10-3 Mo contact 10-4 D = 30 nm 300 o C RTA =0.5 V g m,pk = 600 µs/µm Mo contact D = 30 nm 300 o C RTA =0.5 V =0.05 V S lin = 66 mv/dec S sat = 85 mv/dec DIBL = 67 mv/dec V gs (V) 9

10 Mo-contacted MOSFETs: Diameter Scaling g m,pk (µs/µm) = 0.5 V Mo, 300 C RTA R on (Ω µm) Data represent mean value of 3 devices D (nm) D (nm) D g m, R on due to top contact resistance Minimum D: 15 nm S lin (mv/dec) = 0.05 V D S (improved SCE) D (nm) 10

11 D = 7 nm Ni-contacted MOSFET I d (µa/µm) V gs = 0 V to 0.8 V in 0.1 V step R on = 1100 Ω µm Ni contact D = 7 nm 200 o C FGA (V) Single nanowire MOSFET: L ch = 80 nm 2.5 nm Al 2 O 3 (EOT = 1.25 nm) 200 o C FGA, 1 min g m,pk = 1700 V DD = 0.5 V Final FGA has huge impact! g m (µs/µm) I d (A/µm) =0.5 V g m,pk = 1700 µs/µm Ni contact D = 7 nm 200 o C FGA V gs (V) Ni contact =0.5 V D = 7 nm 200 o C FGA S lin /S sat = 85/90 mv/dec DIBL = 222 mv/dec Before FGA Before FGA =0.5 V =0.05 V =0.5 V V gs (V) 11

12 Ni-contacted MOSFETs: Diameter Scaling g m,pk (µs/µm) = 0.5 V Ni, 200 C FGA Mo, 300 C RTA R on (Ω µm) Data represent mean value of 3 devices D (nm) D (nm) D g m in spite of R on D S but worse than in Mo devices (T FGA <T RTA ) Minimum D: 7 nm S lin (mv/dec) = 0.05 V D (nm) 12

13 Benchmarking g m,pk (µs/µm) Target: D = 7 nm This work - Ni This work - Mo 1.2 V Si/Ge InGaAs This work - Mo This work - Ni 1 V Diameter (nm) g m,pk (µs/µm) This work - Ni This work - Mo Persson EDL 2010 Tomioka IEDM 2011 Tomioka Nature 2012 Persson DRC 2012 Berg IEDM 2015 Kilpi VLSI 2017 Ramesh VLSI 2016, = 0.4 V Zhao IEDM 2013 This work - Mo This work - Ni =0.5 V S sat (mv/dec) First sub-10 nm diameter VNWs in any material system Record performance at most scaled dimensions 13

14 2. Progress on low frequency noise in III-V VNW transistors 1 st generation TFETs, D = 50 m 2 nd generation TFETs, D = 40 m I d (A/µm) =0.05 V 77K 140K 190K 240K 300K V gs (V) I d (A/µm) K 235 K K 120 K K 80 K =0.05 V V gs (V) Suppressed interface trap-assisted tunneling Jump individual defects Goal: role of individual defects in MOSFETs & TFETs 14

15 Noise in array vs single VNW MOSFET 350n = 50 mv V gs = 0.3 V (peak g m ) 110μ = 50 mv V gs = 0.3 V (peak g m ) 300n 108μ I d (A) 250n I d (A) 106μ 200n 150n 100n Time [S] μ 102μ S-NW A-NW 1/f Time [S] SI d /I 2 d (Hz-1 ) nd generation MOSFET D = 40 nm Noise in array NW (100 NW) about 100 times less than S-NW f [Hz] 15

16 V gs dependence in VNW MOSFETs 2 nd generation MOSFET D = 40 nm 350n = 50 mv V gs = 0.3 (peak g m ) 300n 8x I d (A) 250n 200n 150n 100n Time [S] SI d /I 2 d (Hz-1 ) 1/I d V 4x10-4 ds = 50 mv f = 10 Hz I d (A/µm) (g m /I d ) 2 (V -2 ) Appears to be mobility fluctuation above threshold: need spectroscopy to confirm & more devices 16

17 I d (A/µm) Random Telegraph noise (RTN) in TFETs V gs (V) I d (µa/µm) 10-5 Jump S lin = 61 mv/dec S sat = 66 mv/dec V gs = 0.2 V to 0.6 V in 0.1 V step =0.3 V =0.05 V (V) I d (A) I d (A) I d (A) 3n 2n 2n 2n 2n 2n 1n 1n 1n 900p 800p 700p 600p 500p 400p 300p 120p 110p 100p 90p 80p = 50 mv V gs = 0.24 V = 50 mv Time [S] V gs = 0.18 V V Time [S] ds = 50 mv V gs = 0.12 V 70p 2 nd generation TFETs p D = 40 nm Time [S] RTN consistent with the jump in subthreshold SI d /I 2 d (Hz-1 ) SI d /I 2 d (Hz-1 ) SI d /I 2 d (Hz-1 ) Welch 1/f2 1/f f [Hz] Welch 1/f2 1/f f [Hz] Welch 1/f2 1/f f [Hz] 17

18 RTN in TFETs: comparison with Lund s result Memisevic NanoLett Jump 10-6 =0.3 V 900p 800p = 50 mv V gs = 0.18 V 10-2 Welch 1/f2 1/f I d (A/µm) =0.05 V S lin = 61 mv/dec S sat = 66 mv/dec I d (A) V gs (V) 700p 600p 500p 400p 300p Time [S] SI d /I 2 d (Hz-1 ) f [Hz] Key experimental results match qualitatively to be interpreted 18

19 Device technology: Next steps Improve VNW top contact (mushroom shape) D < 10 nm VNW TFETs & SLS-FETs Antimonide-based VNW Esaki diodes and TFETs in collaboration with IMEC Device physics: Trap: Comparison of traps in MOSFETs (sub-10 nm) vs TFETs Interpretation of role of traps Single quantum channel in sub-10 nm MOSFETs GIDL 19