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1 SUPPLEMENTARY INFORMATION doi: /nature Formation of (111)B polar surface on Si(111) for selective-area growth of InGaAs nanowires on Si. Conventional III-V nanowires (NWs) tend to grow in the <111>B or <111>A directions. For example, InGaAs NWs preferentially grow in the <111>B direction, so vertically-aligned InGaAs NWs can be grown on a III-V(111)B substrate. On the III-V(111)A surface, the InAs NWs grow in three equivalent tilted <111>B directions. The <111> direction of group-iv semiconductors, on the other hand, does not show the polarities such as A and B. Thus, in III-V/Si heteroepitaxy equivalent surface orientations and directions always occur on the Si(111) surface and these equivalencies form anti-phase domains. Instead of the anti-phase domain formation, equivalent growth directions always occur for III-V NW/Si integrations. That is, such III-V NWs on Si(111) grow in vertical <111> and three equivalent tilted <111> directions at the same time. The differences result either from the co-existence of (111)A and B surfaces that are formed when Si is eliminated by a metal catalyst during VLS growth, or from termination of group-iii or group-v atoms on the Si(111) surface during selective-area growth. For rational design of NW applications taking advantage of geometries, we have to force such equivalent growth directions into the vertical <111> direction. As shown in Figs. S1a and S1b, once As-incorporating Si 3+ and/or In-terminated Si 1+ has formed on the Si surface, only vertical III-V NWs should grow on the Si(111) substrates. This is because these surfaces are equivalent to a (111)B-oriented surface. Conversely, the growth directions of the III-V NWs can be controlled by optimizing the initial surface and growth conditions. To form an As-incorporating Si 3+ surface, group-v atoms should be replaced with the outermost Si atoms of the 1 1 reconstructed surface because it is equivalent to a V-atoms-terminated Si 3+ surface and a (111)B-oriented surface. The method of forming these (111)B-oriented surface is different for each III-V/Si system because these processes depend on strength of the bond between group-iii atoms and Si atoms. Fig. S1c and S1d depict the growth sequence for aligning vertical InGaAs NWs on Si(111). 1
2 RESEARCH SUPPLEMENTARY INFORMATION Figure S1. Schematics of chemical structure. a Group-V-incorporating Si 3+ structure, b Group-III-terminated Si 1+ surface, c Growth sequence for aligning vertical InGaAs NWs on Si. Thermal cleaning at 900 C in H 2 is used to evaporate native oxide and form 1 1 surface reconstruction. AsH 3 is supplied in order to form V-incorporated Si 3+ surface. The flow-rate modulation epitaxy enhances the formation of group-iii terminated Si 1+. d. Schematic of flow-rate modulation epitaxy. TMGa+TMIn (1 s) and AsH 3 (1 s) are alternately supplied with an interval of H 2 (2 s). This sequence is repeated 30 times. 2
3 SUPPLEMENTARY INFORMATION RESEARCH 2. Selective-area metal-organic vapour phase epitaxy: Process for growing nanowires (NWs). The selective-area metal-organic vapour phase epitaxy (MOVPE) is illustrated in Figure S2. After the substrate was degreased (Fig. S1a), SiO 2 films with thicknesses of 20 nm were formed by thermal oxidation. The thermal oxidation is usually used to form SiO 2 for III-V NW growth on Si because of the thermal tolerance of the film. Next, circular openings arranged in a triangular lattice with a pitch of m were formed on the SiO 2 films by using electron-beam lithography and wet chemical etching. The opening diameter d 0 can be adjusted by the lithography. In this paper, the d 0 was ranged from 60 to 90 nm. A representative scanning electron microscopy (SEM) image of the masked substrate is shown in Fig. S2b. Finally, NWs were grown by MOVPE. The (111)B-oriented surface was used for the InGaAs NW growth because the III-V NWs are preferentially grown in <111>B directions. The (111)B surface has a topmost of the group-v atoms. Figure S2 a Fabrication processes for selective-area MOVPE. After the deposition of SiO 2 film, hole openings were formed by lithography and etching. NWs were grown by metal-organic vapor phase epitaxy. b SEM image of masked substrate with hole openings. 3
4 RESEARCH SUPPLEMENTARY INFORMATION 3. Strain mapping estimated from TEM image of InGaAs nanowire/si interface Strain mapping estimated from displacement of bright spots in the TEM image are shown in Figs. S3b and S3c. Here, the strains, ε xx and ε yy, were calculated from the displacement of bright spots in Fig. 1d by using a peak-pair finding algorithm and the displacements of the bright spots are defined by u xx = Δx a Si(x) for the in-plane <2-1-1> direction and u yy = Δy- a Si(y) for the vertical <111> direction. The Δx and Δy are the displacements of the bright spots for each direction. The a Si(x) and a Si(y) corresponds to the lattice constants in the in-plane and vertical directions of the Si substrate estimated from the TEM image. Also strain ε xx and ε yy are determined by ε xx = u x and ε yy = u y, where u is u. Note that, since the displacement of the atoms is calculated based on 2 2 xx u yy the position of the atoms in crystalline Si, unstrained InGaAs is mapped into a layer with a strain of + 8.1% in definition. The error in the strain calculation is approximately ± 0.5%. Strains ε xx in Fig. S3b were calculated to be very small in the first three monolayers of a InGaAs NW from the hetero-junction and close to the value calculated for the Si substrate. This indicates that the lattice constant of InGaAs in the <2-1-1> direction in the three monolayer-region is consistent with that of Si and the region has compressive strain. The ε yy strain mapping of InGaAs NW, on the other hand, shows lamellar tensile strain in the four ML-region, and the amount is far larger than 8.1%. Figure S3 a High-resolution TEM image of InGaAs nanowire/si heterointerface. b xx strain mapping of the panel a. c yy strain mapping of the panel a. 4
5 SUPPLEMENTARY INFORMATION RESEARCH 4. Details of fabrication procedure for surrounding-gate transistors (SGTs). Figure S4 shows the fabrication processes for NW SGTs. After the InGaAs NW growth [Fig. S4(a)], InGaAs NWs were covered with a Hf 0.8 Al 0.2 O x ( HfAlO = 20.4) film using atomic layer deposition technique. This oxide was used as the gate oxide. The oxide thickness was ranged from 10 nm (EOT = 1.96 nm) to 20 nm (EOT = 3.92 nm). The gate metal, tungsten (W), was deposited by RF sputtering [Fig. S4(b)], and was lithographically defined in NW-grown masks (50 50 µm 2 ). The NWs were spin-coated with benzocyclobutene (BCB) [Fig. S4(c)] and etched back by reactive-ion etching (RIE) with CF 4 /O 2 mixed gas in order to etch the BCB, W, and HfAlO simultaneously [Fig. S4(d)]. After the RIE the NWs were again spin-coated with BCB and etched back by RIE [Fig. S4(e)] in order to isolate the gate and drain metals. A Ni/Ge/Au/Ni/Au multilayer was evaporated onto a lithographically defined region to serve as the drain contact. A Ti/Au multilayer was deposited onto the Si substrate to serve as the source contact [Fig. S4(f)]. The device includes 10 NWs that were parallel-connected to a single drain contact pad. The gate length (L G ) was 200 nm. Finally, the NW-VSGT were annealed at 420ºC in N 2 in order to obtain Ohmic contacts at the source and drain metals. Figure S4. Device fabrication processes. (a) InGaAs NW growth. (b) Atomic layer deposition of Hf 0.8 Al 0.2 O x and sputtering of W-gate metal. (c) spin-coating of BCB polymer. (d) RIE of BCB, gate oxide, and W metal. (e) Spin-coating of BCB and RIE back-etching to electrically isolate between the gate and drain region. (f) Drain and source metal evaporation. 5
6 RESEARCH SUPPLEMENTARY INFORMATION 5. Gate leakage properties of SGTs using InGaAs NW channels on Si. Figure S5 shows the gate-leakage current (I G ) characteristics of SGT of Fig. 2 with various effective-oxide thickness (EOT). The I G depends on the EOT and ranged from the order of 10-5 A/cm 2 to the order of 10-3 A/cm 2. This values are much lower than that of conventional Si-MOSFET. Figure S5. Gate-leakage characteristics of the SGTs using InGaAs NW-channels on Si. 6. EOT dependence of SS and DIBL of InGaAs NW-SGTs Figure S6 shows the SS and DIBL of InGaAs NW-SGTs of Fig. 2 with various EOT. Neither the SS nor the DIBL depend on EOT. The average SS and DIBL was 82 mv/dec and 45 mv/v. Figure S6: SS and DIBL with a variation of EOT for InGaAs NW-SGTs on Si. 6
7 SUPPLEMENTARY INFORMATION RESEARCH 7. Highly Magnified HAADF-STEM image and EDX mappings for Fig.3 Figure S7 depicts HAADF-STEM image and EDX mapping of Fig. 3 for the InGaAs/InP/InAlAs/InGaAs CMS NW. The thicknesses of the InP, InAlAs, and InGaAs layers estimated from these images were 2.6, 16.5, and 5 nm, respectively. Note also that Al-segregation of Al is evident at corner of the NW. Figure S7: (a) HAADF-STEM image of cross-section of InGaAs CMS NW. (b) Magnified HAADF-STEM image of the corner of the NW. EDX mapping for (c) As, (d) In, (e) Ga, (f) Al and (g) P. 7
8 RESEARCH SUPPLEMENTARY INFORMATION 8. Estimation of field-effect mobility for InGaAs NW-SGTs. The transconductance (G m = di DS /dv G ) of the InGaAs NW-SGT was measured at a V DS = 10 mv in order to avoid the contribution of an external electric field. Capacitance-voltage (C-V G ) curve was measured at 10 khz. The field-effect electron mobility was then estimated from the following relation: μ eff L W V G Where V G is gate bias, L is gate length, W is gate perimeter, and C(V G ) is the capacitance curve measured at 10 khz. G Fig. S8 shows the eff as a function of V G for InGaAs NWs with a gate-drain length of 50 nm (black), InGaAs/InAlAs core-shell NWs with a gate-drain length of 50 nm (green), InGaAs/InP/InAlAs/InGaAs CMS NWs with a gate-drain length of 1 m (red), and InGaAs/InP/InAlAs/InGaAs CMS NWs with a gate-drain length of 50 nm (blue). The eff first increases with increasing the V G and then decreases with further increasing the V G because the electron scattering process is enhanced under high electric field. Compared with the field effect mobility of the InGaAs NW-SGT ( eff = 1,170 cm 2 V -11 s -11 ), the eff offered by the CMS structures was approximately seven-folded to an estimated 7,850 cm 2 V -11 s -11. m C V V G G dv G Figure S8. Field-effect mobility of InGaAs NW-SGT as a function of V G at a V DS of 10 mv. 8
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