Zota, Cezar B.; Lindelow, Fredrik; Wernersson, Lars Erik; Lind, Erik

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1 InGaAs tri-gate MOSFETs with record on-current Zota, Cezar B.; Lindelow, Fredrik; Wernersson, Lars Erik; Lind, Erik Published in: 6 IEEE International Electron Devices Meeting, IEDM 6 DOI:.9/IEDM Document Version: Peer reviewed version (aka post-print) Link to publication Citation for published version (APA): Zota, C. B., Lindelow, F., Wernersson, L. E., & Lind, E. (7). InGaAs tri-gate MOSFETs with record oncurrent. In 6 IEEE International Electron Devices Meeting, IEDM 6 (pp...-..). [7886] Institute of Electrical and Electronics Engineers Inc.. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. Users may download and print one copy of any publication from the public portal for the purpose of private study or research. You may not further distribute the material or use it for any profit-making activity or commercial gain You may freely distribute the URL identifying the publication in the public portal Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. L UNDUNI VERS I TY PO Box7 L und +66

2 InGaAs Tri-gate MOSFETs with Record On-Current Cezar B. Zota, Fredrik Lindelow, Lars-Erik Wernersson and Erik Lind Department of Electrical and Information Technology, Lund University, Lund, Sweden Phone: Abstract We demonstrate InGaAs tri-gate MOSFETs with an on-current of = 65 µa/µm at V DD =.5 V and I OFF = na/µm, enabled by an inverse subthreshold slope of SS = 66 mv/decade and transconductance of = ms/µm, a Q- factor of 5. This is the highest reported for both Si-based and III-V MOSFETs. These results continue to push III-V MOSFET experimental performance towards its theoretical limit. We find an improvement in SS from 8 to 75 mv/dec. as the effective oxide thickness (EOT) is scaled down from. to nm, as well as improvements in SS, g d and DIBL from reducing the nanowire width. We also find that electron mobility remains constant as the width is scaled to 8 nm. I. INTRODUCTION An important path for reducing the power density in CMOS technology has been to lower the supply voltage V DD. To maintain sufficient drive current, innovations are required, such as strained channels, novel channel materials and D device architectures []-[]. For this purpose, high indium In x Ga -x As is an attractive channel material due to its excellent electron transport properties, i.e. high electron mobility µ e and lonean free path λ [6]. While the relatively low DOS of indium-rich In x Ga -x As is predicted to limit in highly scaled devices, compared to competing technologies such as Si and Ge, this may be offset by the gain from the long λ and high µ e of In x Ga -x As [5]. Since this technology likely will be implemented in a D channel architecture, such as FinFETs or NWFETs, a further question concerns the dependence of λ on the channel dimensions, i.e. the influence of surface roughness on device performance. In this work, we demonstrate tri-gate MOSFETs utilizing an In.85 Ga.5 As nanowire (NW) as the channel. By gate oxide scaling, improvements of the surface passivation process and optimization of device dimensions, we achieve a drive current of = 65 µa/µm at V DD =.5 V and I OFF = na/µm. This is a record value for both III-V and Si MOSFETs. We also show that, as the NW width,, is scaled down, electrostatic properties significantly improve, while and λ do not degrade. These results continue to push the limits, as well as explore the potential, of III-V FETs. II. DEVICE FABRICATION The process flow and schematic images of the device are shown in Fig. (a)-(f). The nanowires are formed by selective area growth, using hydrogen silsesquioxane (HSQ) as the MOCVD growth mask, as described elsewhere []. Each device consists of a single NW. The composition of the NW is In.85 Ga.5 As, as determined by optical characterization [5]. Fig. (g) shows an SEM image of an NW with = 9 nm, with the sidewall facets denoted [5]. The inset of Fig. (h) shows a schematic figure of the NW crosssection. nm highly doped In.6 Ga.7 As (N D = 5 9 cm - ) is subsequently grown by MOCVD as the contact layer, utilizing HSQ as a dummy gate [Fig. (h)]. After mesa isolation, the InP in the channel is etched by HCl (%) in order to form a ~ nm tall plateau, with the purpose of improving the gate coverage along the bottom of the sides of the NW. cycles of surface oxidation by ozone and diluted HCl etching (digital etching) are performed to reduce the dimensions of the NW. The final height of the NW is H NW = 8 nm, as determined from AFM. Subsequently, Ti/Pd/Au contact metal is evaporated and patterned by lift-off. Surface passivation, by ozone cleaning and (NH) S (%) for min, is followed by deposition of Al O /HfO gate oxide (5/5 cycles and EOT nm, unless otherwise stated). A hour post-deposition anneal step at C in N atmosphere is performed in-situ. Thermal evaporation and patterning by lift-off of //5 nm Ni/Pd/Au as the gate metal complete the process [Fig. (i)]. III. RESULTS Fig. shows transfer characteristics of a tri-gate MOSFET with and = 5 nm. All normalization is done to the total gated NW periphery, i.e. the three sides of the tri-gate. Peak transconductance is. ms/µm at V DS =.5 V. Subthreshold characteristics of the same device are shown in Fig. At V DD =.5 V and I OFF = na/µm, = 65 µa/µm. The gate current is I G < na/µm. Minimum inverse subthreshold slope SS reaches 66 mv/decade (Fig. ) at, and 6 mv/decade at V DS =.5 V. The drain-induced barrier-lowering (DIBL) is 65 mv/v, measured at = µa/µm. The on-resistance of this device is R ON = 75 Ω µm at = V. Output characteristics for = 9 and = 5 nm devices with are shown in Fig. 5 and 6, respectively. The output conductance of these devices is g d =.5 and.5 ms/µm (voltage gain is 5.5 and ) at V T =. Minimum SS versus is shown for = 5 nm and = 9 nm devices at V DS =.5 and.5 V (Fig. 7). The reduced offers improved resilience against short channel effects (SCEs), but at = 5 nm, SS is degraded ( mv/decade) even at = 5 nm. Minimum SS versus is shown in Fig. 8 for devices at. Average minimum SS improves from approximately 95 mv/dec. for > 9 nm to SS < 7 mv/dec. for < nm due to enhanced electrostatic control. The lowest SS of a device at this bias is 6 mv/dec. The theoretical values

3 indicate SS obtained from a solution of Laplace s equation modeling the full D structure of the nanowire using COMSOL. To improve performance at short, must be further reduced. Scaling of H NW will improve SS but reduce the aspect ratio (AR), which is undesirable. Moreover, the implementation of a wider band gap back-barrier, such as InAlAs or a BOX layer, is also expected to improve resilience to SCEs. Fig. 9 shows median (crosses) and mean (squares) minimum SS for four samples with and = 5- nm at both V DS =.5 and.5 V (~ devices each). Sample D has 5/5 cycles Al O /HfO. Sample C has 5/5 cycles Al O /HfO. Sample B and A have 5/5 cycles Al O /HfO. In addition, samples D, C and B where passivated with (NH ) S (%) produced by Merck, while sample A was passivated with (NH ) S (%) produced by Sigma-Aldrich. Fig. shows mean minimum SS of samples D to B versus EOT ( cycle =. Å, κ = 8 and 9 for HfO and Al O ). These results indicate an improvement both from oxide scaling (average SS improves from 8 to 75 mv/dec. for EOT from ~. nm to ~ nm), and from optimization of the surface passivation parameters (mean SS improves from 75 to 7 mv/dec. for sample B to A). The trend indicates that SS may be further improved by scaling of the EOT. We do not observe a clear trend of versus EOT. Fig. shows g d versus at and V T =.5 V for devices. Average g d is reduced from.5 ms/µm at = 9 nm to ~. ms/µm at = 5 nm. The DIBL measured at µa/µm is shown in Fig.. It is similarly reduced from 7 mv/v at = 9 nm, to 8 mv/v at = 5 nm. The threshold voltage (V T ) defined at = µa/µm increases in narrow NWs (Fig. ). The trend approximately follows calculated values from an effective mass quantum wire model, indicating that the V T increase is due to quantum confinement. Fig. shows versus. The highest observed in these devices is ~. ms/µm (SS sat = 9 mv/dec.) at V DS =.5 V and = 5 nm. increases as is scaled down to approximately 5 nm from planar architecture ( = µm). This may be explained by that narrow NWs are more Indiumrich, due to interactions with the HSQ mask during MOCVD growth, which may improve mobility as well as change the D it distribution [5]. This shows that the improvement of g d with, is in fact due to improved electrostatics. The inset of Fig. 5 shows average values of versus for = 5 nm. Dashed traces show an analytical quasi-ballistic model with λ = nm fitted to the measured data. at V DD =.5 V and I OFF = na/µm is shown in Fig. 5 versus both and (inset). increases from to 65 µa/µm as goes from um (planar) to 5 nm, due to the simultaneous improvements of SS ( to 66 mv/dec.) and (. to ms/µm). peaks at, which is explained by the degraded SS (Fig. 7) and that only improves slightly (Fig. ) for shorter. These devices exhibit quantized conductance at K due to subband splitting in a D channel (inset of Fig. 6). From the conductance steps, the transmission is obtained. The device in Fig. shows a transmission of T =.67, which indicates quasi-ballistic transport. Fig. 6 shows electron mobility µ e and λ for NWs with = 8 nm calculated from quantized conductance. To obtain µ e, we use the Einstein relation and a correction factor of.6 to account for degeneracy [5]. We note that this method is not strongly influenced by D it. No dependency versus is observed, which correlates with versus with < 5 nm, explained by small surface scattering. Since is temperature-independent, the same is true for µ e. A benchmark of the (at V DD =.5 V and I OFF = na/µm) for state-of-the-art III-V planar and non-planar MOSFETs is shown in Fig. 7. The value of 65 µa/µm presented in this work is the record value of both categories. The same is true for the quality factor Q = /SS, which is 5 in this work (Fig. 8). Fig. 9 compares at V DD =.5 V and I OFF = na/µm for various technologies.,surface is normalized to the gated channel periphery, while,chip is normalized to the chip surface width including the specified pitch size.,chip in our devices is lower than that of nm FinFET (57 compared to 65 µa/µm for a pitch of nm), which demonstrates the importance of high AR in D channels, but we observe a two-fold increase in,surface over nm FinFET technology, which is due primarily to the high µ e of In x Ga -x As [6]. IV. CONCLUSION We have demonstrated In x Ga -x As tri-gate MOSFETs with a record on-current of 65 µa/µm at V DD =.5 V and = na/µm, SS = 66 mv/decade and =. ms/µm. From data versus NW width, we observed improvements in SS, DIBL and g d for scaled down NWs. Furthermore, we observed improvements both from oxide scaling the surface passivation process. From low-temperature measurements we obtain µ e and λ, which remain high, 75 cm /Vs and 5 nm, respectively, even in scaled NWs. This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research and in part by the European Union H program INSIGHT (Grant Agreement No ). V. REFERENCES [] S. Lee et al., EDL, p. 6 (). [] C. B. Zota et al., VLSI, (6). [] T.-W. Kim et al., EDL, vol. 6, p. (5). [] C. B. Zota et al., IEDM, p. 8 (5). [5] J. Lin et al., EDL, vol 7, p. 8 (6). [6] Radosavljevic et al., IEDM, p. 765 (). [7] T.-W. Kim et al., IEDM, p. 5 (). [8] N. Waldron et al., IEDM, p. 8 (5). [9] P. Chang et al., IEDM, p. 8 (). [] J. Lin et al., IEDM, p. (). [] J. J. Gu et al., IEDM, p. 6 (). [] S. Lee et al., VLSI (). [] Radosavljevic et al., IEDM, p. 9 (9). [] C. Huang et al., IEDM, p. 589 (). [5] C. B. Zota et al., ACS Nano, vol. 9, p. 989 (5). [6] S. Natarajan et al., IEDM, p. 7 ().

4 (a) (b) NW MOCVD growth HSQ InGaAs Nano wire InP:Fe Su bstrate InGaAs n + MOCVD growth n + In.6 Ga.7 As HSQ InGaAs Nano wire InP:Fe Su bstrate (d) S/D contact metallization Ti/Pd/Au n + In.6 Ga.7 As (e) Gate oxide ALD Ti/Pd/Au n + In.6 Ga.7 As Al O /HfO (g) Substrate (i) In.85Ga.5 As nm Gate: Ni/Pd/Au (h) In.85 Ga.5 As Gate Ni/Pd/Au nm InP substrate n + In.6 Ga.7 As [] HfO /Al O InP substrate(s.i.) (c) Digital etching and InP plateau formation (f) Gate metallization S/D: Ti/Pd/Au n + In.6 Ga.7 As Ni/Pd/Au Ti/Pd/Au n + In.6 Ga.7 As Al O /HfO n + In.6 Ga.7 As 5 nm InP substrate Fig. : Schematic figures SEM images of the device fabrication process. (a) NW formation utilizes selective area MOCVD growth with an EBL-defined HSQ hard mask. (b) Contacts are defined using an HSQ dummy gate and MOCVD regrowth of n + In.6Ga.7As. (c) NW is scaled down using digital etching. (d) S/D metal is deposited by evaporation and lift-off. (e) A bilayer of AlO/HfO is used as the gate oxide. (f) Ni/Pd/Au is evaporated as the gate metal. (g) SEM image of a 9 nm wide NW with the side facets denoted. (h) The device after contact regrowth. Inset shows a schematic cross-section of the NW in the finished device. (i) False-color SEM image of the finished device. The NW is located at the center of the µm wide mesa. & Fig.. Transfer characteristics for a device with WNW = 5 nm..5.5 V =. to.9 V GS =. V = 9 nm (A/μm) Fig. : Subthreshold characteristics for the same device as in Fig V =. to. V GS =. V = 5 nm V DS : 5 mv 5 mv = 65 μa/μm SS = 66 mv/dec. DIBL = 65 mv/v SS (mv/dec.) SS mv/dec.) ( Fig. : Subthreshold slope versus VGS for the same device as in Fig.. 8 V DS : 5 mv 5 mv V DS =.5 V = 9 nm = 5 nm V DS Fig. 5: Output characteristics for a device with LG = 75 nm and WNW = 9 nm V DS Fig. 6: Output characteristics for a device with LG = 75 nm and WNW = 5 nm Fig. 7: Subthreshold slope for devices with different WNW and LG.

5 SS mv/dec.) ( g d Fig. 8: Subthreshold slope versus WNW at VDS =.5 V and LG = 75 nm V T =.5 V 6 8 Fig. : Output conductance versus WNW, measured at VDS = VGS VT =.5 V. (μa/μm) Experimental Theoretical [] [] Non-planar = 5 nm [] [] [7] This work [] I OFF = na/μm V DD =.5 V Fig. 7: Benchmark of ION at VDD =.5 V and IOFF = na/µm. [6] λ = nm [] [] Fig. : Peak gm versus WNW and (inset) LG, all measured at VDS =.5 V. SS ( mv/dec.) DIBL (mv/v) V DS =.5 V A B C Sample Fig. 9: Mean (squares) and median (crosses) SS for different samples = μa/μm 6 8 Fig. : DIBL versus WNW measured at IDS = µa/µm Fig. 5: ION versus WNW and LG at IOFF = na/µm. This work [] 5 [] 7 5 [6] [] 5 [] [9] [] [8] [] 5 SS (mv/dec) Fig. 8: Benchmark of the quality factor gm/ss at VDS =.5 V. [5] D = 5 nm 5 5 = 5 nm 5 5 [] 5 Q = Non-planar SS (mv/dec.) V T μ e (cm /Vs) (μa/μm) V DS = 5 mv = 5 - nm EOT Fig. : Average subthreshold slope (each point is ~ devices) versus EOT Theoretical = μa/μm. 6 8 Fig. : Threshold voltage versus WNW. Dashed traces show a QW model (μa) V DS = mv T L = K Fig. 6: µe and λ, measured from quantized current (inset), versus WNW. 8 6 I OFF = na/μm % This work - InGaAs Tri-Gate 6% nm FinFET 77% III-V,Surface 6% Si V DD =.5 nm FinFET,Chip Technology Fig. 9: Benchmark of various technologies. 5 λ