Experimentally reported sub-60mv/dec

Transcription

1 Experimentally reported sub-60mv/dec swing in Tunnel FETs? 1

2 We considered InAs conventional, lateral transistor architectures: GAA nanowire, Fin FETs FETs (Tri gate) UTB,DG SOI Analysis is not directly applicable to vertical tunnel FETs embodiments with gate field aligned to tunnel direction: G. Zhou et al., in IEDM, 2012, pp ; L. Lattanzio et al., IEEE T ED, 2012, vol. 59, pp. 2932; M. Li et al., JAP 2014, p , STEEP Transistors Workshop,

3 Case study: InAs Gate All Around A nanowire MOSFETs and TFETs Quasi 2D, semi analytical models for the potential profile: from [R. H. Yan et al., TED 1992] to very recent contributions [F. Villani et al. ESSDERC 2014] Denoting with φ c the potential at the center of the channel and assuming that the free carrier density in the channel is negligible: Natural length λ for a quadruple gate, square section nanowire: After C W. Lee, et al., Solid State Electronics, pp.505,

4 After C W. Lee et al., Solid State Electronics, pp.505, 2006 STEEP Transistors Workshop, 2015 At small L G / the gate control is deteriorated short channel effects MOSFETs in the plot have negligible sourcedrain tunneling effects Universal curve for thermionic MOSFETs What aboutmosfetswith significant source drain tunneling and Tunnel FETs? 4

5 60 mv/dec InAs Tunnel FETs 60 mv/dec InAs MOSFETs STEEP Transistors Workshop,

6 Known T(E) and the subband profile the I DS is given by the Landauer formula Single mode expression The trasmission coefficient T(E) for tunneling can be obtained with the WKB for both intraband (MOSFET) and band to band tunneling (Tunnel FET): MOSFET, OFF state STEEP Transistors Workshop, 2015 TFET, OFF state 6

7 Analytical k im (E) energy relation in the gap based on two band Flietner s model [Flietner, PSSB 1972]: Eg/2 Numerical k p calculations Maximum K IM (E) results in a minimum i in I TUNN vs. V GS curves for both MOSFETs and Tunnel FETs 7

8 MOSFET: V ds =0.3V, L g = 20nm S deg = 0.2eV t sc = 5nm, N d = 5e19 cm -3 Analysis at 3 bias points: Thermionic emission Minimum I DS Ambipolar region STEEP Transistors Workshop,

9 TFET: V ds= 0.3V, L g = 20nm S deg = 0.05eV, t sc = 5nm Analysis at 3 bias points: Sub threshold region Minimum I DS Ambipolar region STEEP Transistors Workshop,

10 Three dimens. NEGF based numerical simulations Source draind i tunneling degradesd SS w.r.t. to the universal curve of thermionic MOSFETs 10

11 Three dimens. NEGF based numerical simulations Tunnel l FETs have SS<60mV/dec and better than MOSFETs only for relatively large[l G / ] values 11

12 Key points: Suppression of tunneling via gate bias is inherently non monotonic ambipolarity For L G approaching 10nm: Tunnel FETs and MOSFETs have analogies in terms of minimum off current and ambipolarity Electrostatic integrity will not be the only challenge to achieve a good off-state behavior It is dfficult to compete with thermionic MOSFETs, that is with MOSFETs with suppressed S-D tunneling Still a lot of room for material and device design STEEP Transistors Workshop,