Tunnel FET C-V modeling: - Impact of TFET C-V characteristics on inverter circuit performance

Transcription

1 Tunnel FET C-V modeling: - Impact of TFET C-V characteristics on inverter circuit performance Chika Tanaka, Tetsufumi Tanamoto, and Masato Koyama Corporate R&D Center, Toshiba Corporation 2017 Toshiba Corporation MOS-AK Workshop, 2017, Leuven

2 Outline 1. Background i. Device and Circuit Characteristics of TFET ii. Capacitance-Voltage characteristics of TFET iii. Impact of TFET CV characteristics on circuit performance 2. Modeling & Simulation method i. Implementation of C-V threshold voltage (Vth CV ) on BSIM4 parameter ii. Targeted I d -V g and C g -V g characteristics iii. Vth CV optimization and simulated circuit 3. Simulation results i. Influence of Vth CV modulation on inverter delay ii. V dd dependence on t delay with Mirror effect 4. Summary 2017 Toshiba Corporation 2

3 Device and Circuit Characteristics of TFET Tunnel Field Effect Transistor (TFET) vs. Conventional CMOS Circuit Simulation (Ring Osc.) Low Ion TFETs Vdd=1.2V 65nm CMOS Vdd=1.2V Low Vdd operation Steep S.S. TFETs Vdd=0.5V 65nm CMOS Vdd=0.5V TFET Steep Sub-threshold Slope Low Ion dew to band-to-band tunneling Advantage of low-vdd and low-power device 2017 Toshiba Corporation 3

4 Capacitance-Voltage characteristics of TFET Vd=0V Vg=0V S Cgd: response of minority carrier G D Vd=1V Vg=0V S Cgd: response of minority carrier and depletion cap. G D Cgs: depletion cap. Cgs: depletion cap. Asymmetry of Cgs and Cgd by depletion capacitance of source side tunnel junction IEEE TED, 56, 9 (2009) Peak voltage for overshoot (VP) VV P = CC M CC M + CC L CM:mirror cap.(=cgdp+cgdn) For TFT, CM~2Cgg For MOSFET, CM~Cgg CL:load cap.(cap. for next stage) Vp increases as the increase of drain side mirror capacitance 2017 Toshiba Corporation 4

5 Impact of TFET CV characteristics on circuit performance tt delay CC EFF VV dd 22IIon CEFF is function of Cgg: CEFF ~ CM+CL(Cgg) Circuit delay (t delay ) is influenced by both CM and CL NMOS NLTFET NSJL Cgg Cgg Cgg Cgs Cgs Cgs Cgb Cgd Cgb Cgd Cgb Cgd When Vd is applied, (1) V th CV =f(vd) Cgg effectively decreases (2) Cgd>>Cgs CM increasing 2D TCAD simulation results Modeled by voltage dependence on Vth for CV (V th CV ) 2014 Toshiba Corporation 5

6 Outline 1. Background i. Device and Circuit Characteristics of TFET ii. Capacitance-Voltage characteristics of TFET iii. Impact of TFET CV characteristics on circuit performance 2. Modeling & Simulation method i. Implementation of C-V threshold voltage (Vth CV ) on BSIM4 parameter ii. Targeted I d -V g and C g -V g characteristics iii. Vth CV optimization and simulated circuit 3. Simulation results i. Influence of Vth CV modulation on inverter delay ii. V dd dependence on t delay with Mirror effect 4. Summary 2014 Toshiba Corporation 6

7 Implementation of Vth CV (V d ) on BSIM4 parameter Equivalent circuit for N-TFET VOFFCV(Vd):off VOFFCV(Vd):on Cgg [a.u.] D Vd=0 Vd=1 Cgg [a.u.] Vd=0 Vd= Vg [V] Vg [V] BSIM4-based CV model: Implementation of Vd dependence on Vth CV VOFFCV VOFFCV(Vd)=f(Vd) Investigate the influence of effective C gg decrease on inverter circuit delay by CV threshold modulation 2017 Toshiba Corporation 7

8 Targeted I d -V g and C g -V g characteristics Capacitance [ff] Source Boron Gate Lg=120nm, Tox=2nm, Ns=1E16 cm -3 Drain As Vd=0.5V Vd=0.7V Vd=1.0V Cgg Cgd Cgs Vg [V] Capacitance [ff] Id [A/mm] 1E-6 1E-8 1E-10 1E-12 1E-14 Cgg Cgd Cgs Vg [V] Capacitance [ff] Vd=1.0V Vd=0.7V Vd=0.5V 1E Vg [V] Cgg Cgd Cgs Vg [V] Drain voltage (V d ) dependent on V th for C-V 2017 Toshiba Corporation 8

9 V th CV optimization and simulated test circuit V th CV optimization result VOFFCV=f(Vd, voffcv1, voffcv2) Split parameters VOFFCV to have V d dependence Extract to be optimized with each V d for voffcv1 and voffcv2 Simulated circuit configuration 2-stages inverter (output: Vout1) CL=2 Cgg CM=Cgdp+Cgdn 2017 Toshiba Corporation 9

10 Outline 1. Background i. Device and Circuit Characteristics of TFET ii. Capacitance-Voltage characteristics of TFET iii. Impact of TFET CV characteristics on circuit performance 2. Modeling & Simulation method i. Implementation of C-V threshold voltage (Vth CV ) on BSIM4 parameter ii. Targeted I d -V g and C g -V g characteristics iii. Vth CV optimization and simulated circuit 3. Simulation results i. Influence of Vth CV modulation on inverter delay ii. V dd dependence on t delay with Mirror effect 4. Summary 2017 Toshiba Corporation 10

11 Influence of Vth CV modulation on inverter delay t delay = t rise (with V d depend.) t rise (w/o V d depend.) Vout1 [V] Vdd=1.0V t delay time [nsec.] Inverter Delay (t delay ) tt delay CC EFF VV dd 22IIon Vth CV with V d dependence CEFF~CM + CL If load capacitance (CL) becomes small, inverter delay reduced. Vth CV w/o V d dependence t delay shows the effective gate capacitance reduction. t delay [nsec.] Vdd Cgg Effect of C L reduction Vdd [V] 2017 Toshiba Corporation 11

12 V dd dependence on t delay with Mirror effect Normalized t delay Vdd [V] CM = Cgdp + Cgdn ττ delay CC EFF VV dd 22IIon CEFF~ CM + CL t delay increases by C gg reduction Correction by Mirror effect Vdd [V] 1.0 Even when considering Miller effect, the effect 0.0 that the effective C gg reduction is large Increase in t delay becomes prominent as low V dd. Normalized t delay t delay decreases by Mirror effect 2017 Toshiba Corporation 12

13 Summary i. Implementation of the effective C gg reduction on SPICE model was made by parameterizing the BSIM4 C-V parameter. Re-parameterizing of BSIM4 C-V parameter is reasonable approach to analyze the non-si CMOS circuit performance. ii. We investigated the influence of TFET C-V characteristics on inverter circuit delay by using the our proposed (optimized) model. Although the delay increases with the influence of overshoot due to the increase in C M, the effect of decreasing C L is prominent due to the reduction in effective gate capacitance, and then the inverter delay is smaller than the case where TFET C-V characteristics is not considered. Acknowledgements This work was supported by JST CREST Grant Number JPMJCR1332, Japan. We thank K. Adachi, A. Hokazono, M. Fujimatsu, and S. Kawanaka for discussions and supports Toshiba Corporation 13