Beyond Transistor Scaling: New Devices for Ultra Low Energy Information Processing

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1 Beyond Transistor Scaling: New Devices for Ultra Low Energy Information Processing Prof. Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA April 28, th US Korea Nano Forum (Las Vegas, NV, USA)

2 The CMOS Power Crisis

3 The CMOS Power Crisis Due to off state leakage, V TH cannot be scaled down aggressively. Thus, the supply voltage (V DD ) has not been scaled down in proportion to the MOSFET channel length. CMOS power density has increased with transistor scaling! V DD V DD V TH V TH CMOS Voltage Scaling Source: P. Packan (Intel), 2007 IEDM Short Course Power Density (W/cm 2 ) 1E+03 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 Power Density with CMOS Scaling Passive Power Density Active Power Density Gate Length (μm) Source: B. Meyerson (IBM) Semico Conf., January

4 Parallelism Power Density (W/cm2) up Chip Power DensityTrend Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Core Hot Plate P Pentium proc Year Source: S. Borkar (Intel) Normalized Energy/op Operate at a lower energy point Run in parallel to recoup performance /throughput (ps/op) Parallelism is the main technique to improve system performance under a power budget. 4

5 Minimizing Operation Energy CMOS Energy per Operation 100 CMOS Energy vs. Delay 80 E leakage E total E dynamic Normalized Energy/op /throughput (ps/op) E dynamic + E leakage = αl d CV dd2 + L d I OFF V dd t delay t delay = L d CV dd /(2I ON ) CMOS has a fundamental lower limit in energy per operation, due to subthreshold leakage. 5

6 The Need for a New Switch CMOS Energy vs. Delay (normalized) Today: Parallelism lowers E/op Future: Parallelism doesn t help Delay When each core operates at the minimum energy, increasing performance requires more power. 6

7 New Switching Devices

8 MOSFET Subthreshold Swing MOSFET Structure: n(e) exp( E/kT) Electron Energy Band Profile log I D I ON Source Gate Drain increasing E S I OFF VDD Substrate distance V G In the subthreshold region (V GS < V TH ), I S 60mV/dec at room temperature D exp qv nkt GS S must be reduced in order to achieve the desired I ON /I OFF with smaller V DD 8

9 Tunnel FET (TFET) Structure: Energy band Diagrams: OFF STATE: ON STATE: Gate p+ Source n+ Drain Substrate E C E V E C E V tunneling current I D bandgap (E g ) = aξ exp( b / ξ ) Si TFET I V Characteristics W. Y. Choi et al. (Seoul Nat l U. & UC Berkeley) IEEE EDL vol. 28, pp , 2007 Drain Current (A/µm) V D =1 V V D = 0.1 V SS = 52.8 mv/dec T = 300 K L G = 70 nm t ox = 2 nm t SOI = 70 nm W = 10 µm Gate Voltage (V) ξ = a V A GS + V κt ox tunnel m * / E g b m * / E 3 g 9

10 Energy Performance Comparison H. Kam et al. (UCB, Stanford U.), 2008 IEDM 1.E-15 ] [J 1.E-16 y rg e n E1.E-17 CMOS TFET Si TFETs appear promising for sub 1GHz applications 1.E-18 1.E-02 1.E-01 1.E+00 1.E+01 Performance (GHz) 30-stage 65nm CMOS inverter chain (transition probability=0.01, capacitance per stage=2.4ff) 10

11 TFET Technology Challenges Increased I ON to expand range of applications Advanced semiconductor materials to achieve smaller effective E g V TH control TFET based integrated circuit design 11

12 MOSFET Inspired Relay OFF state V GB < V TH F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD ON state V GB V TH The mechanical gate is electrostatically actuated by a voltage applied between the gate and body electrode, to bring the channel into contact with the source and drain electrodes. Plan View Micrograph Measured I V 1.E-2 Ideal switching behavior: Zero off state leakage Abrupt turn on low V TH (and V DD ) possible! I DS (A) 1.E-6 1.E-10 1.E-14 V DS = 0.5V V Body =0V Gate: W =2µm L=20µm H =200nm actuation gap = 400nm V GB (V) L 12

13 Relay Scaling F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD Scaling has similar benefits for relays as for MOSFETs. Pull in Voltage with Beam Scaling Measured pull in voltages scale linearly {W,L,t gap } = {90nm,2.3um,10nm} V pi = 200mV Mechanical delay also scales linearly 90nm) 13

14 Relay Based Circuit Design F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD Relays have small RC delay but large mechanical delay Complete all logic in a single complex (pass transistor) gate Example of CMOS to Relay Logic Mapping: Energy vs. Delay Comparison: (32 bit adders, 90nm technology) 10x reduction CMOS fundamental limit A relay adder can be : ~10x more energy efficient at the same delay as a CMOS adder. 14

15 Relay Technology Challenges Surface adhesion force Mechanical contact resistance Relay I-V Characteristic Reliability I DS hysteresis due to surface force V rel V pi V GS 15

16 Summary

17 Summary Due to subthreshold leakage, CMOS technology has a fundamental limit in energy efficiency. New switching devices with steeper switching behavior are needed to achieve lower energy per operation. Examples: tunnel FET, relay Note: Such devices may have very different characteristics than the MOSFET. Thus, they will require new circuit and system architectures to fully realize their potential energyefficiency (and hence performance) benefits. 17

18 Acknowledgements Collaborators: Faculty: Elad Alon (UCB), Dejan Markovic (UCLA), Vladimir Stojanovic (MIT) Students: Hei Kam, Fred Chen (MIT) Research funding:» DARPA STEEP Program» DARPA/MARCO Focus Center Research Program: Center for Circuits and Systems Solutions (C2S2) Center for Materials, Structures, and Devices (MSD) UC Berkeley Microfabrication Laboratory 18